1 /*
2  * Copyright (c) 2015 - 2016, Freescale Semiconductor, Inc.
3  * Copyright 2016 - 2018 NXP
4  * All rights reserved.
5  *
6  * SPDX-License-Identifier: BSD-3-Clause
7  */
8 
9 #ifndef __SERIAL_PORT_USB_H__
10 #define __SERIAL_PORT_USB_H__
11 
12 #if defined(SDK_OS_FREE_RTOS)
13 #include "FreeRTOS.h"
14 #endif
15 
16 /*!
17  * @addtogroup serial_port_usb
18  * @ingroup serialmanager
19  * @{
20  */
21 
22 /*******************************************************************************
23  * Definitions
24  ******************************************************************************/
25 /*! @brief serial port usb handle size*/
26 #define SERIAL_PORT_USB_CDC_HANDLE_SIZE (72U)
27 
28 /*! @brief USB interrupt priority*/
29 #if defined(__GIC_PRIO_BITS)
30 #ifndef USB_DEVICE_INTERRUPT_PRIORITY
31 #define USB_DEVICE_INTERRUPT_PRIORITY (25U)
32 #endif
33 #else
34 #if defined(configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY)
35 #ifndef USB_DEVICE_INTERRUPT_PRIORITY
36 #define USB_DEVICE_INTERRUPT_PRIORITY (configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY)
37 #endif
38 #else
39 /* The default value 3 is used to support different ARM Core, such as CM0P, CM4, CM7, and CM33, etc.
40  * The minimum number of priority bits implemented in the NVIC is 2 on these SOCs. The value of mininum
41  * priority is 3 (2^2 - 1). So, the default value is 3.
42  */
43 #ifndef USB_DEVICE_INTERRUPT_PRIORITY
44 #define USB_DEVICE_INTERRUPT_PRIORITY (3U)
45 #endif
46 #endif
47 #endif
48 
49 /*! @brief USB controller ID */
50 typedef enum _serial_port_usb_cdc_controller_index
51 {
52     kSerialManager_UsbControllerKhci0 = 0U, /*!< KHCI 0U */
53     kSerialManager_UsbControllerKhci1 = 1U, /*!< KHCI 1U, Currently, there are no platforms which have two KHCI IPs,
54                                   this is reserved to be used in the future. */
55     kSerialManager_UsbControllerEhci0 = 2U, /*!< EHCI 0U */
56     kSerialManager_UsbControllerEhci1 = 3U, /*!< EHCI 1U, Currently, there are no platforms which have two EHCI IPs,
57                                   this is reserved to be used in the future. */
58 
59     kSerialManager_UsbControllerLpcIp3511Fs0 = 4U, /*!< LPC USB IP3511 FS controller 0 */
60     kSerialManager_UsbControllerLpcIp3511Fs1 = 5U, /*!< LPC USB IP3511 FS controller 1, there are no platforms which
61                                                      have two IP3511 IPs, this is reserved to be used in the future. */
62 
63     kSerialManager_UsbControllerLpcIp3511Hs0 = 6U, /*!< LPC USB IP3511 HS controller 0 */
64     kSerialManager_UsbControllerLpcIp3511Hs1 = 7U, /*!< LPC USB IP3511 HS controller 1, there are no platforms which
65                                                      have two IP3511 IPs, this is reserved to be used in the future. */
66 
67     kSerialManager_UsbControllerOhci0 = 8U,        /*!< OHCI 0U */
68     kSerialManager_UsbControllerOhci1 = 9U, /*!< OHCI 1U, Currently, there are no platforms which have two OHCI IPs,
69                                   this is reserved to be used in the future. */
70 
71     kSerialManager_UsbControllerIp3516Hs0 = 10U, /*!< IP3516HS 0U */
72     kSerialManager_UsbControllerIp3516Hs1 = 11U, /*!< IP3516HS 1U, Currently, there are no platforms which have two
73                                                IP3516HS IPs, this is reserved to be used in the future. */
74 } serial_port_usb_cdc_controller_index_t;
75 
76 /*! @brief serial port usb config struct*/
77 typedef struct _serial_port_usb_cdc_config
78 {
79     serial_port_usb_cdc_controller_index_t controllerIndex; /*!< controller index */
80 } serial_port_usb_cdc_config_t;
81 
82 /*! @} */
83 #endif /* __SERIAL_PORT_USB_H__ */
84