1 /*
2 * Copyright 2020-2023 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8 #ifndef FSL_CCM32K_H_
9 #define FSL_CCM32K_H_
10
11 #include "fsl_common.h"
12
13 /*!
14 * @addtogroup ccm32k
15 * @{
16 */
17
18 /*******************************************************************************
19 * Definitions
20 ******************************************************************************/
21
22 /*! @name Driver version */
23 /*! @{ */
24 /*! @brief CCM32K driver version 2.2.0. */
25 #define FSL_CCM32K_DRIVER_VERSION (MAKE_VERSION(2, 2, 0))
26 /*! @} */
27
28 #define CCM32K_OSC32K_CTRL_OSC_MODE_MASK (0x3U)
29 #define CCM32K_OSC32K_CTRL_OSC_MODE_SHIFT (0U)
30 #define CCM32K_OSC32K_CTRL_OSC_MODE(x) \
31 (((uint32_t)(((uint32_t)(x)) << CCM32K_OSC32K_CTRL_OSC_MODE_SHIFT)) & CCM32K_OSC32K_CTRL_OSC_MODE_MASK)
32
33 /*!
34 * @brief The enumerator of internal capacitance of OSC's XTAL pin.
35 */
36 typedef enum _ccm32k_osc_xtal_cap
37 {
38 kCCM32K_OscXtal0pFCap = 0x0U, /*!< The internal capacitance for XTAL pin is 0pF. */
39 kCCM32K_OscXtal2pFCap = 0x1U, /*!< The internal capacitance for XTAL pin is 2pF. */
40 kCCM32K_OscXtal4pFCap = 0x2U, /*!< The internal capacitance for XTAL pin is 4pF. */
41 kCCM32K_OscXtal6pFCap = 0x3U, /*!< The internal capacitance for XTAL pin is 6pF. */
42 kCCM32K_OscXtal8pFCap = 0x4U, /*!< The internal capacitance for XTAL pin is 8pF. */
43 kCCM32K_OscXtal10pFCap = 0x5U, /*!< The internal capacitance for XTAL pin is 10pF. */
44 kCCM32K_OscXtal12pFCap = 0x6U, /*!< The internal capacitance for XTAL pin is 12pF. */
45 kCCM32K_OscXtal14pFCap = 0x7U, /*!< The internal capacitance for XTAL pin is 14pF. */
46 kCCM32K_OscXtal16pFCap = 0x8U, /*!< The internal capacitance for XTAL pin is 16pF. */
47 kCCM32K_OscXtal18pFCap = 0x9U, /*!< The internal capacitance for XTAL pin is 18pF. */
48 kCCM32K_OscXtal20pFCap = 0xAU, /*!< The internal capacitance for XTAL pin is 20pF. */
49 kCCM32K_OscXtal22pFCap = 0xBU, /*!< The internal capacitance for XTAL pin is 22pF. */
50 kCCM32K_OscXtal24pFCap = 0xCU, /*!< The internal capacitance for XTAL pin is 24pF. */
51 kCCM32K_OscXtal26pFCap = 0xDU, /*!< The internal capacitance for XTAL pin is 26pF. */
52 kCCM32K_OscXtal28pFCap = 0xEU, /*!< The internal capacitance for XTAL pin is 28pF. */
53 kCCM32K_OscXtal30pFCap = 0xFU, /*!< The internal capacitance for XTAL pin is 30pF. */
54 } ccm32k_osc_xtal_cap_t;
55
56 /*!
57 * @brief The enumerator of internal capacitance of OSC's EXTAL pin.
58 */
59 typedef enum _ccm32k_osc_extal_cap
60 {
61 kCCM32K_OscExtal0pFCap = 0x0U, /*!< The internal capacitance for EXTAL pin is 0pF. */
62 kCCM32K_OscExtal2pFCap = 0x1U, /*!< The internal capacitance for EXTAL pin is 2pF. */
63 kCCM32K_OscExtal4pFCap = 0x2U, /*!< The internal capacitance for EXTAL pin is 4pF. */
64 kCCM32K_OscExtal6pFCap = 0x3U, /*!< The internal capacitance for EXTAL pin is 6pF. */
65 kCCM32K_OscExtal8pFCap = 0x4U, /*!< The internal capacitance for EXTAL pin is 8pF. */
66 kCCM32K_OscExtal10pFCap = 0x5U, /*!< The internal capacitance for EXTAL pin is 10pF. */
67 kCCM32K_OscExtal12pFCap = 0x6U, /*!< The internal capacitance for EXTAL pin is 12pF. */
68 kCCM32K_OscExtal14pFCap = 0x7U, /*!< The internal capacitance for EXTAL pin is 14pF. */
69 kCCM32K_OscExtal16pFCap = 0x8U, /*!< The internal capacitance for EXTAL pin is 16pF. */
70 kCCM32K_OscExtal18pFCap = 0x9U, /*!< The internal capacitance for EXTAL pin is 18pF. */
71 kCCM32K_OscExtal20pFCap = 0xAU, /*!< The internal capacitance for EXTAL pin is 20pF. */
72 kCCM32K_OscExtal22pFCap = 0xBU, /*!< The internal capacitance for EXTAL pin is 22pF. */
73 kCCM32K_OscExtal24pFCap = 0xCU, /*!< The internal capacitance for EXTAL pin is 24pF. */
74 kCCM32K_OscExtal26pFCap = 0xDU, /*!< The internal capacitance for EXTAL pin is 26pF. */
75 kCCM32K_OscExtal28pFCap = 0xEU, /*!< The internal capacitance for EXTAL pin is 28pF. */
76 kCCM32K_OscExtal30pFCap = 0xFU, /*!< The internal capacitance for EXTAL pin is 30pF. */
77 } ccm32k_osc_extal_cap_t;
78
79 #if (defined(FSL_FEATURE_CCM32K_HAS_FINE_AMP_GAIN) && FSL_FEATURE_CCM32K_HAS_FINE_AMP_GAIN)
80 /*!
81 * @brief The enumerator of osc amplifier gain fine adjustment.
82 * Changes the oscillator amplitude by modifying the automatic gain control (AGC).
83 */
84 typedef enum _ccm32k_osc_fine_adjustment_value
85 {
86 kCCM32K_OscFineAdjustmentRange0 = 0U,
87 } ccm32k_osc_fine_adjustment_value_t;
88 #endif /* FSL_FEATURE_CCM32K_HAS_FINE_AMP_GAIN */
89
90 /*!
91 * @brief The enumerator of osc amplifier coarse fine adjustment.
92 * Tunes the internal transconductance (gm) by increasing the current.
93 */
94 typedef enum _ccm32k_osc_coarse_adjustment_value
95 {
96 kCCM32K_OscCoarseAdjustmentRange0 = 0U,
97 kCCM32K_OscCoarseAdjustmentRange1 = 1U,
98 kCCM32K_OscCoarseAdjustmentRange2 = 2U,
99 kCCM32K_OscCoarseAdjustmentRange3 = 3U
100 } ccm32k_osc_coarse_adjustment_value_t;
101
102 /*!
103 * @brief The enumerator of 32kHz oscillator.
104 */
105 typedef enum _ccm32k_osc_mode
106 {
107 kCCM32K_Disable32kHzCrystalOsc = 0x0U, /*!< Disable 32kHz Crystal Oscillator. */
108 kCCM32K_Enable32kHzCrystalOsc = 0x1U, /*!< Enable 32kHz Crystal Oscillator. */
109 kCCM32K_Bypass32kHzCrystalOsc = 0x3U, /*!< Bypass 32kHz Crystal Oscillator,
110 use the 32kHz Oscillator or external 32kHz clock. */
111 } ccm32k_osc_mode_t;
112
113 /*!
114 * @brief The enumerator of CCM32K status flag.
115 */
116 enum
117 {
118 kCCM32K_32kOscReadyStatusFlag = CCM32K_STATUS_OSC32K_RDY_MASK, /*!< Indicates the 32kHz crystal
119 oscillator is stable. */
120 kCCM32K_32kOscActiveStatusFlag = CCM32K_STATUS_OSC32K_ACTIVE_MASK, /*!< Indicates the 32kHz crystal
121 oscillator is active and in use. */
122 kCCM32K_32kFroActiveStatusFlag = CCM32K_STATUS_FRO32K_ACTIVE_MASK, /*!< Indicates the 32kHz free running
123 oscillator is active and in use. */
124 #if (defined(FSL_FEATURE_CCM32K_HAS_CGC32K) && FSL_FEATURE_CCM32K_HAS_CGC32K)
125 kCCM32K_ClockDetectStatusFlag = CCM32K_STATUS_CLOCK_DET_MASK, /*!< Indicates the clock monitor has
126 detected an error. */
127 #endif /* FSL_FEATURE_CCM32K_HAS_CGC32K */
128 };
129
130 /*!
131 * @brief The enumerator of module state.
132 */
133 typedef enum _ccm32k_state
134 {
135 kCCM32K_Both32kFro32kOscDisabled =
136 0x0U, /*!< Indicates both 32kHz free running oscillator and 32kHz crystal oscillator are disabled. */
137 kCCM32K_Only32kFroEnabled = 0x1U, /*!< Indicates only 32kHz free running oscillator is enabled. */
138 kCCM32K_Only32kOscEnabled = 0x2U, /*!< Indicates only 32kHz crystal oscillator is enabled. */
139 kCCM32K_Both32kFro32kOscEnabled = ((uint8_t)kCCM32K_Only32kFroEnabled | (uint8_t)kCCM32K_Only32kOscEnabled),
140 /*!< Indicates both 32kHz free running oscillator and 32kHz crystal oscillator are enabled. */
141 } ccm32k_state_t;
142
143 /*!
144 * @brief The enumerator of clock source.
145 */
146 typedef enum _ccm32k_clock_source
147 {
148 kCCM32K_ClockSourceNone = 0x0U, /*!< None clock source. */
149 kCCM32K_ClockSource32kFro = 0x1U, /*!< 32kHz free running oscillator is the clock source. */
150 kCCM32K_ClockSource32kOsc = 0x2U, /*!< 32kHz crystal oscillator is the clock source. */
151 } ccm32k_clock_source_t;
152
153 #if (defined(FSL_FEATURE_CCM32K_HAS_CLKMON_CTRL) && FSL_FEATURE_CCM32K_HAS_CLKMON_CTRL)
154 /*!
155 * @brief Clock monitor frequency trim values.
156 */
157 typedef enum _ccm32k_clock_monitor_freq_trim_value
158 {
159 kCCM32K_ClockMonitor2CycleAssert = 0x0U, /*!< Clock monitor asserts 2 cycle after
160 expected edge (assert after 10 cycles with no edge). */
161 kCCM32K_ClockMonitor4CycleAssert, /*!< Clock monitor asserts 4 cycle after
162 expected edge (assert after 12 cycles with no edge). */
163 kCCM32K_ClockMonitor6CycleAssert, /*!< Clock monitor asserts 6 cycle after
164 expected edge (assert after 14 cycles with no edge). */
165 kCCM32K_ClockMonitor8CycleAssert, /*!< Clock monitor asserts 8 cycle after
166 expected edge (assert after 16 cycles with no edge). */
167 } ccm32k_clock_monitor_freq_trim_value_t;
168
169 /*!
170 * @brief Clock monitor divide trim values.
171 */
172 typedef enum _ccm32k_clock_monitor_divide_trim_value
173 {
174 kCCM32K_ClockMonitor_1kHzFro32k_1kHzOsc32k = 0x0U, /*!< Clock monitor operates at 1 kHz
175 for both FRO32K and OSC32K. */
176 kCCM32K_ClockMonitor_64HzFro32k_1kHzOsc32k = 0x1U, /*!< Clock monitor operates at 64 Hz for FRO32K and
177 clock monitor operates at 1 kHz for OSC32K. */
178 kCCM32K_ClockMonitor_1KHzFro32k_64HzOsc32k = 0x2U, /*!< Clock monitor operates at 1K Hz for FRO32K and
179 clock monitor operates at 64 Hz for OSC32K. */
180 kCCM32K_ClockMonitor_64HzFro32k_64HzOsc32k = 0x3U, /*!< Clock monitor operates at 64 Hz for FRO32K and
181 clock monitor operates at 64 Hz for OSC32K. */
182 } ccm32k_clock_monitor_divide_trim_value_t;
183
184 /*!
185 * @brief Clock monitor configuration structure.
186 */
187 typedef struct _ccm32k_clock_monitor_config
188 {
189 bool enableClockMonitor; /*!< Used to enable/disable clock monitor. */
190 ccm32k_clock_monitor_freq_trim_value_t freqTrimValue; /*!< Clock minitor frequency trim value. */
191 ccm32k_clock_monitor_divide_trim_value_t divideTrimValue; /*!< Clock minitor divide trim value. */
192 } ccm32k_clock_monitor_config_t;
193 #endif /* FSL_FEATURE_CCM32K_HAS_CLKMON_CTRL */
194
195 #if (defined(FSL_FEATURE_CCM32K_HAS_CGC32K) && FSL_FEATURE_CCM32K_HAS_CGC32K)
196 /*!
197 * @brief CCM32K clock source enumeration.
198 */
199 typedef enum _ccm32k_clock_source_select
200 {
201 kCCM32K_ClockSourceSelectFro32k = 0x0U, /*!< FRO32K clock output is selected as clock source. */
202 kCCM32K_ClockSourceSelectOsc32k, /*!< OSC32K clock output is selected as clock source. */
203 } ccm32k_clock_source_select_t;
204
205 /*!
206 * @brief 32kHz clock output peripheral bit map.
207 */
208 typedef enum _ccm32k_clock_output_peripheral
209 {
210 kCCM32K_ClockOutToRtc = 1U << 0U, /*!< 32kHz clock output to RTC. */
211 kCCM32K_ClockOutToRfmc = 1U << 1U, /*!< 32kHz clock output to Rfmc. */
212 kCCM32K_ClockOutToNbu = 1U << 2U, /*!< 32kHz clock output to NBU. */
213 kCCM32K_ClockOutToWuuRmcPortD = 1U << 3U, /*!< 32kHz clock output to WUU/RMC/PORTD. */
214 kCCM32K_ClockOutToOtherModules = 1U << 4U, /*!< 32kHz clock output to Other modules. */
215 } ccm32k_clock_output_peripheral_t;
216
217 #endif /* FSL_FEATURE_CCM32K_HAS_CGC32K */
218
219 /*!
220 * @brief The structure of oscillator configuration.
221 */
222 typedef struct _ccm32k_osc_config
223 {
224 bool enableInternalCapBank; /*!< enable/disable the internal capacitance bank. */
225 ccm32k_osc_xtal_cap_t xtalCap; /*!< The internal capacitance for the OSC XTAL pin from the capacitor bank,
226 only useful when the internal capacitance bank is enabled. */
227 ccm32k_osc_extal_cap_t extalCap; /*!< The internal capacitance for the OSC EXTAL pin from the capacitor bank,
228 only useful when the internal capacitance bank is enabled. */
229 #if (defined(FSL_FEATURE_CCM32K_HAS_FINE_AMP_GAIN) && FSL_FEATURE_CCM32K_HAS_FINE_AMP_GAIN)
230 ccm32k_osc_fine_adjustment_value_t fineAdjustment; /*!< 32kHz crystal oscillator amplifier fine adjustment value. */
231 #endif /* FSL_FEATURE_CCM32K_HAS_FINE_AMP_GAIN */
232 ccm32k_osc_coarse_adjustment_value_t
233 coarseAdjustment; /*!< 32kHz crystal oscillator amplifier coarse adjustment value. */
234 } ccm32k_osc_config_t;
235
236 /*******************************************************************************
237 * API
238 ******************************************************************************/
239
240 #if defined(__cplusplus)
241 extern "C" {
242 #endif
243
244 /*!
245 * @name 32kHz Free-running Oscillator Interfaces
246 * @{
247 */
248
249 /*!
250 * @brief Enable/Disable 32kHz free-running oscillator.
251 *
252 * @note There is a start up time before clocks are output from the FRO.
253 * @note To enable FRO32k and set it as 32kHz clock source please follow steps:
254 * @code
255 * CCM32K_Enable32kFro(base, true); //Enable FRO analog oscillator.
256 * CCM32K_DisableCLKOutToPeripherals(base, mask); //Disable clock out.
257 * CCM32K_SelectClockSource(base, kCCM32K_ClockSourceSelectFro32k); //Select FRO32k as clock source.
258 * while(CCM32K_GetStatus(base) != kCCM32K_32kFroActiveStatusFlag); //Check FOR32k is active and in used.
259 * CCM32K_EnableCLKOutToPeripherals(base, mask); //Enable clock out if needed.
260 * @endcode
261 *
262 * @param base CCM32K peripheral base address.
263 * @param enable Boolean value to enable or disable the 32kHz free-running oscillator.
264 * true -- Enable 32kHz free-running oscillator.
265 * false -- Disable 32kHz free-running oscillator.
266 */
267 void CCM32K_Enable32kFro(CCM32K_Type *base, bool enable);
268
269 /*!
270 * @brief Lock all further write accesses to the FRO32K_CTRL register until a POR occurs.
271 *
272 * @param base CCM32K peripheral base address.
273 */
CCM32K_Lock32kFroWriteAccess(CCM32K_Type * base)274 static inline void CCM32K_Lock32kFroWriteAccess(CCM32K_Type *base)
275 {
276 base->FRO32K_CTRL |= CCM32K_FRO32K_CTRL_LOCK_EN_MASK;
277 }
278
279 /*!
280 * @brief Get frequency trim value of 32kHz free-running oscillator.
281 *
282 * @param base CCM32K peripheral base address.
283 * @return The current trim value.
284 */
CCM32K_Get32kFroTrimValue(CCM32K_Type * base)285 static inline uint16_t CCM32K_Get32kFroTrimValue(CCM32K_Type *base)
286 {
287 return ((uint16_t)(((base->FRO32K_TRIM) & CCM32K_FRO32K_TRIM_FREQ_TRIM_MASK) >>
288 (uint32_t)CCM32K_FRO32K_TRIM_FREQ_TRIM_SHIFT));
289 }
290
291 /*!
292 * @brief Set the frequency trim value of 32kHz free-running oscillator by software.
293 *
294 * @note The frequency is decreased monotonically when the trimValue is changed progressively
295 * from 0x0U to 0x7FFU.
296 *
297 * @note If the FRO32 is enabled before invoking this function, then in this function the FRO32 will be disabled,
298 * after updating trim value the FRO32 will be re-enabled.
299 *
300 * @param base CCM32K peripheral base address.
301 * @param trimValue The frequency trim value.
302 */
303 void CCM32K_Set32kFroTrimValue(CCM32K_Type *base, uint16_t trimValue);
304
305 /*!
306 * @brief Disable/Enable the function of setting 32kHz free-running oscillator trim value
307 * when IFR value gets loaded in the SOC.
308 *
309 * @param base CCM32K peripheral base address.
310 * @param disable Boolean value to disable or enable IFR loading function.
311 * true -- Disable IFR loading function.
312 * false -- Enable IFR loading function.
313 */
CCM32K_Disable32kFroIFRLoad(CCM32K_Type * base,bool disable)314 static inline void CCM32K_Disable32kFroIFRLoad(CCM32K_Type *base, bool disable)
315 {
316 if (disable)
317 {
318 base->FRO32K_TRIM |= CCM32K_FRO32K_TRIM_IFR_DIS_MASK;
319 }
320 else
321 {
322 base->FRO32K_TRIM &= ~CCM32K_FRO32K_TRIM_IFR_DIS_MASK;
323 }
324 }
325
326 /*!
327 * @brief Lock all further write accesses to the FRO32K_TRIM register until a POR occurs.
328 *
329 * @param base CCM32K peripheral base address.
330 */
CCM32K_Lock32kFroTrimWriteAccess(CCM32K_Type * base)331 static inline void CCM32K_Lock32kFroTrimWriteAccess(CCM32K_Type *base)
332 {
333 base->FRO32K_TRIM |= CCM32K_FRO32K_TRIM_LOCK_EN_MASK;
334 }
335
336 /*! @} */
337
338 /*!
339 * @name 32kHz Crystal Oscillator Interfaces
340 * @{
341 */
342
343 /*!
344 * @brief Config 32k Crystal Oscillator.
345 *
346 * @note When the mode selected as \ref kCCM32K_Disable32kHzCrystalOsc or \ref kCCM32K_Bypass32kHzCrystalOsc
347 * the parameter config is useless, so it can be set as "NULL".
348 *
349 * @note To enable OSC32K and select it as clock source of 32kHz please follow steps:
350 * @code
351 * CCM32K_Set32kOscConfig(base, kCCM32K_Enable32kHzCrystalOsc, config); //Enable OSC32k and set config.
352 * while((CCM32K_GetStatus(base) & kCCM32K_32kOscReadyStatusFlag) == 0UL); //Check if OSC32K is stable.
353 * CCM32K_DisableCLKOutToPeripherals(base, mask); //Disable clock out.
354 * CCM32K_SelectClockSource(base, kCCM32K_ClockSourceSelectOsc32k); //Select OSC32k as clock source.
355 * while((CCM32K_GetStatus(base) & kCCM32K_32kOscActiveStatusFlag) == 0UL); //Check if OSC32K is used as clock source.
356 * CCM32K_EnableCLKOutToPeripherals(base, mask); //Enable clock out.
357 * @endcode
358 *
359 * @param base CCM32K peripheral base address.
360 * @param mode The mode of 32k crystal oscillator.
361 * @param config The pointer to the structure \ref ccm32k_osc_config_t.
362 */
363 void CCM32K_Set32kOscConfig(CCM32K_Type *base, ccm32k_osc_mode_t mode, const ccm32k_osc_config_t *config);
364
365 /*!
366 * @brief Lock all further write accesses to the OSC32K_CTRL register until a POR occurs.
367 *
368 * @param base CCM32K peripheral base address.
369 */
CCM32K_Lock32kOscWriteAccess(CCM32K_Type * base)370 static inline void CCM32K_Lock32kOscWriteAccess(CCM32K_Type *base)
371 {
372 base->OSC32K_CTRL |= CCM32K_OSC32K_CTRL_LOCK_EN_MASK;
373 }
374
375 /*! @} */
376
377 #if (defined(FSL_FEATURE_CCM32K_HAS_CLKMON_CTRL) && FSL_FEATURE_CCM32K_HAS_CLKMON_CTRL)
378 /*!
379 * @name Clock Monitor Control Interfaces
380 * @{
381 */
382
383 /*!
384 * @brief Enable/disable clock monitor.
385 *
386 * @param base CCM32K peripheral base address.
387 * @param enable Used to enable/disable clock monitor.
388 * - \b turn Enable clock monitor.
389 * - \b false Disable clock monitor.
390 */
391 void CCM32K_EnableClockMonitor(CCM32K_Type *base, bool enable);
392
393 /*!
394 * @brief Set clock monitor frequency trim value.
395 *
396 * @param base CCM32K peripheral base address.
397 * @param trimValue Clock minitor frequency trim value, please refer to @ref ccm32k_clock_monitor_freq_trim_value_t.
398 */
CCM32K_SetClockMonitorFreqTrimValue(CCM32K_Type * base,ccm32k_clock_monitor_freq_trim_value_t trimValue)399 static inline void CCM32K_SetClockMonitorFreqTrimValue(CCM32K_Type *base,
400 ccm32k_clock_monitor_freq_trim_value_t trimValue)
401 {
402 base->CLKMON_CTRL =
403 (base->CLKMON_CTRL & ~CCM32K_CLKMON_CTRL_FREQ_TRIM_MASK) | CCM32K_CLKMON_CTRL_FREQ_TRIM(trimValue);
404 }
405
406 /*!
407 * @brief Set clock monitor divide trim value.
408 *
409 * @param base CCM32K peripheral base address.
410 * @param trimValue Clock minitor divide trim value, please refer to @ref ccm32k_clock_monitor_divide_trim_value_t.
411 */
CCM32K_SetClockMonitorDivideTrimValue(CCM32K_Type * base,ccm32k_clock_monitor_divide_trim_value_t trimValue)412 static inline void CCM32K_SetClockMonitorDivideTrimValue(CCM32K_Type *base,
413 ccm32k_clock_monitor_divide_trim_value_t trimValue)
414 {
415 base->CLKMON_CTRL =
416 (base->CLKMON_CTRL & ~CCM32K_CLKMON_CTRL_DIVIDE_TRIM_MASK) | CCM32K_CLKMON_CTRL_DIVIDE_TRIM(trimValue);
417 }
418
419 /*!
420 * @brief Config clock monitor one time, including frequency trim value, divide trim value.
421 *
422 * @param base CCM32K peripheral base address.
423 * @param config Pointer to @ref ccm32k_clock_monitor_config_t structure.
424 */
425 void CCM32K_SetClockMonitorConfig(CCM32K_Type *base, const ccm32k_clock_monitor_config_t *config);
426
427 /*!
428 * @brief Lock all further write accesses to the CLKMON_CTRL register until a POR occurs.
429 *
430 * @param base CCM32K peripheral base address.
431 */
CCM32K_LockClockMonitorWriteAccess(CCM32K_Type * base)432 static inline void CCM32K_LockClockMonitorWriteAccess(CCM32K_Type *base)
433 {
434 base->CLKMON_CTRL |= CCM32K_CLKMON_CTRL_LOCK_EN_MASK;
435 }
436
437 /*!
438 * @}
439 */
440 #endif /* FSL_FEATURE_CCM32K_HAS_CLKMON_CTRL */
441
442 #if (defined(FSL_FEATURE_CCM32K_HAS_CGC32K) && FSL_FEATURE_CCM32K_HAS_CGC32K)
443 /*!
444 * @name Clock Gate Control Interfaces
445 * @{
446 */
447
448 /*!
449 * @brief Enable 32kHz clock output to selected peripherals.
450 *
451 * @param base CCM32K peripheral base address.
452 * @param peripheralMask The mask of peripherals to enable 32kHz clock output,
453 * should be the OR'ed value of @ref ccm32k_clock_output_peripheral_t.
454 */
CCM32K_EnableCLKOutToPeripherals(CCM32K_Type * base,uint8_t peripheralMask)455 static inline void CCM32K_EnableCLKOutToPeripherals(CCM32K_Type *base, uint8_t peripheralMask)
456 {
457 base->CGC32K |= CCM32K_CGC32K_CLK_OE_32K(peripheralMask);
458 }
459
460 /*!
461 * @brief Disable 32kHz clock output to selected peripherals.
462 *
463 * @param base CCM32K peripheral base address.
464 * @param peripheralMask The mask of peripherals to disable 32kHz clock output,
465 * should be the OR'ed value of @ref ccm32k_clock_output_peripheral_t.
466 */
CCM32K_DisableCLKOutToPeripherals(CCM32K_Type * base,uint8_t peripheralMask)467 static inline void CCM32K_DisableCLKOutToPeripherals(CCM32K_Type *base, uint8_t peripheralMask)
468 {
469 base->CGC32K &= ~CCM32K_CGC32K_CLK_OE_32K(peripheralMask);
470 }
471
472 /*!
473 * @brief Select CCM32K module's clock source which will be provide to the device.
474 *
475 * @param base CCM32K peripheral base address.
476 * @param clockSource Used to select clock source, please refer to @ref ccm32k_clock_source_select_t for details.
477 */
CCM32K_SelectClockSource(CCM32K_Type * base,ccm32k_clock_source_select_t clockSource)478 static inline void CCM32K_SelectClockSource(CCM32K_Type *base, ccm32k_clock_source_select_t clockSource)
479 {
480 /* To select OSC32K as clock source, OSC32k must be stable, to select FRO32K as clock source, it must be enabled. */
481 assert(((clockSource == kCCM32K_ClockSourceSelectOsc32k) && \
482 ((base->STATUS & CCM32K_STATUS_OSC32K_RDY_MASK) == 1UL)) \
483 || ((clockSource == kCCM32K_ClockSourceSelectFro32k) && \
484 ((base->FRO32K_CTRL & CCM32K_FRO32K_CTRL_FRO_EN_MASK) != 0UL)));
485
486 base->CGC32K = (base->CGC32K & ~CCM32K_CGC32K_CLK_SEL_32K_MASK) | CCM32K_CGC32K_CLK_SEL_32K(clockSource);
487 }
488
489 /*!
490 * @brief Lock all further write access to the CGC32K register until a POR occurs.
491 *
492 * @param base CCM32K peripheral base address.
493 */
CCM32K_LockClockGateWriteAccess(CCM32K_Type * base)494 static inline void CCM32K_LockClockGateWriteAccess(CCM32K_Type *base)
495 {
496 base->CGC32K |= CCM32K_CGC32K_LOCK_EN_MASK;
497 }
498 /*!
499 * @}
500 */
501 #endif /* FSL_FEATURE_CCM32K_HAS_CGC32K */
502
503 /*!
504 * @name Status Interface
505 * @{
506 */
507
508 /*!
509 * @brief Get the status flag.
510 *
511 * @param base CCM32K peripheral base address.
512 * @return The status flag of the current node. The enumerator of status flags have been provided, please see the
513 * Enumerations title for details.
514 */
CCM32K_GetStatusFlag(CCM32K_Type * base)515 static inline uint32_t CCM32K_GetStatusFlag(CCM32K_Type *base)
516 {
517 return base->STATUS;
518 }
519
520 /*! @} */
521
522 /*!
523 * @name State/Clock Source Interfaces
524 */
525 /*!
526 * @brief Get current state.
527 *
528 * @param base CCM32K peripheral base address.
529 * @return The CCM32K's current state, please refer to \ref ccm32k_state_t for details.
530 */
531 ccm32k_state_t CCM32K_GetCurrentState(CCM32K_Type *base);
532
533 /*!
534 * @brief Return current clock source.
535 *
536 * @param base CCM32K peripheral base address.
537 * @retval kCCM32K_ClockSourceNone The none clock source is selected.
538 * @retval kCCM32K_ClockSource32kFro 32kHz free-running oscillator is selected as clock source.
539 * @retval kCCM32K_ClockSource32kOsc 32kHz crystal oscillator is selected as clock source..
540 */
541 ccm32k_clock_source_t CCM32K_GetClockSource(CCM32K_Type *base);
542
543 /*! @} */
544
545 #if defined(__cplusplus)
546 }
547 #endif
548
549 /*! @} */
550
551 #endif /* FSL_CCM32K_H_ */
552
