1 /*
2 * Copyright 2019 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8 #include "fsl_anatop_ai.h"
9 /* Component ID definition, used by tools. */
10 #ifndef FSL_COMPONENT_ID
11 #define FSL_COMPONENT_ID "platform.drivers.anatop_ai"
12 #endif
13
ANATOP_AI_Access(anatop_ai_itf_t itf,bool isWrite,anatop_ai_reg_t addr,uint32_t wdata)14 uint32_t ANATOP_AI_Access(anatop_ai_itf_t itf, bool isWrite, anatop_ai_reg_t addr, uint32_t wdata)
15 {
16 uint32_t temp;
17 uint32_t rdata;
18 uint32_t pre_toggle_done;
19 uint32_t toggle_done;
20
21 switch (itf)
22 {
23 case kAI_Itf_Ldo:
24 if (isWrite)
25 {
26 ANADIG_MISC->VDDSOC_AI_CTRL &= ~ANADIG_MISC_VDDSOC_AI_CTRL_VDDSOC_AIRWB_MASK;
27 temp = ANADIG_MISC->VDDSOC_AI_CTRL;
28 temp &= ~ANADIG_MISC_VDDSOC_AI_CTRL_VDDSOC_AI_ADDR_MASK;
29 temp |= ((uint32_t)addr << ANADIG_MISC_VDDSOC_AI_CTRL_VDDSOC_AI_ADDR_SHIFT) &
30 ANADIG_MISC_VDDSOC_AI_CTRL_VDDSOC_AI_ADDR_MASK;
31 ANADIG_MISC->VDDSOC_AI_CTRL = temp;
32 ANADIG_MISC->VDDSOC_AI_WDATA = wdata; /* write ai data */
33 ANADIG_PMU->PMU_LDO_PLL ^= ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_AI_TOGGLE_MASK; /* toggle */
34 }
35 else /* read */
36 {
37 temp = ANADIG_MISC->VDDSOC_AI_CTRL;
38 temp &= ~ANADIG_MISC_VDDSOC_AI_CTRL_VDDSOC_AIRWB_MASK;
39 temp |= (1UL << ANADIG_MISC_VDDSOC_AI_CTRL_VDDSOC_AIRWB_SHIFT) &
40 ANADIG_MISC_VDDSOC_AI_CTRL_VDDSOC_AIRWB_MASK;
41 ANADIG_MISC->VDDSOC_AI_CTRL = temp;
42 temp = ANADIG_MISC->VDDSOC_AI_CTRL;
43 temp &= ~ANADIG_MISC_VDDSOC_AI_CTRL_VDDSOC_AI_ADDR_MASK;
44 temp |= ((uint32_t)addr << ANADIG_MISC_VDDSOC_AI_CTRL_VDDSOC_AI_ADDR_SHIFT) &
45 ANADIG_MISC_VDDSOC_AI_CTRL_VDDSOC_AI_ADDR_MASK;
46 ANADIG_MISC->VDDSOC_AI_CTRL = temp;
47 ANADIG_PMU->PMU_LDO_PLL ^= ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_AI_TOGGLE_MASK; /* toggle */
48 rdata = ANADIG_MISC->VDDSOC_AI_RDATA; /* read data */
49 return rdata;
50 }
51 break;
52 case kAI_Itf_1g:
53 if (isWrite)
54 {
55 pre_toggle_done =
56 ANADIG_MISC->VDDSOC2PLL_AI_CTRL_1G &
57 ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AITOGGLE_DONE_1G_MASK; /* get pre_toggle_done */
58 ANADIG_MISC->VDDSOC2PLL_AI_CTRL_1G &= ~ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AIRWB_1G_MASK;
59 temp = ANADIG_MISC->VDDSOC2PLL_AI_CTRL_1G;
60 temp &= ~ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AIADDR_1G_MASK;
61 temp |= ((uint32_t)addr << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AIADDR_1G_SHIFT) &
62 ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AIADDR_1G_MASK;
63 ANADIG_MISC->VDDSOC2PLL_AI_CTRL_1G = temp;
64 ANADIG_MISC->VDDSOC2PLL_AI_WDATA_1G = wdata; /* write ai data */
65 ANADIG_MISC->VDDSOC2PLL_AI_CTRL_1G ^=
66 ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AITOGGLE_1G_MASK; /* toggle */
67 do
68 {
69 toggle_done =
70 (ANADIG_MISC->VDDSOC2PLL_AI_CTRL_1G &
71 ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AITOGGLE_DONE_1G_MASK); /* wait toggle done
72 toggle */
73 } while (toggle_done == pre_toggle_done);
74 }
75 else
76 {
77 pre_toggle_done =
78 (ANADIG_MISC->VDDSOC2PLL_AI_CTRL_1G &
79 ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AITOGGLE_DONE_1G_MASK); /* get pre_toggle_done */
80 temp = ANADIG_MISC->VDDSOC2PLL_AI_CTRL_1G;
81 temp &= ~ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AIRWB_1G_MASK;
82 temp |= (1UL << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AIRWB_1G_SHIFT) &
83 ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AIRWB_1G_MASK;
84 ANADIG_MISC->VDDSOC2PLL_AI_CTRL_1G = temp;
85 temp = ANADIG_MISC->VDDSOC2PLL_AI_CTRL_1G;
86 temp &= ~ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AIADDR_1G_MASK;
87 temp |= ((uint32_t)addr << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AIADDR_1G_SHIFT) &
88 ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AIADDR_1G_MASK;
89 ANADIG_MISC->VDDSOC2PLL_AI_CTRL_1G = temp;
90 ANADIG_MISC->VDDSOC2PLL_AI_CTRL_1G ^=
91 ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AITOGGLE_1G_MASK; /* toggle */
92 do
93 {
94 toggle_done =
95 (ANADIG_MISC->VDDSOC2PLL_AI_CTRL_1G &
96 ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AITOGGLE_DONE_1G_MASK); /* wait toggle done
97 toggle */
98 } while (toggle_done == pre_toggle_done);
99 rdata = ANADIG_MISC->VDDSOC2PLL_AI_RDATA_1G; /* read data */
100 return rdata;
101 }
102 break;
103 case kAI_Itf_Audio:
104 if (isWrite)
105 {
106 pre_toggle_done =
107 ANADIG_MISC->VDDSOC2PLL_AI_CTRL_AUDIO &
108 ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AITOGGLE_DONE_AUDIO_MASK; /* get pre_toggle_done */
109 ANADIG_MISC->VDDSOC2PLL_AI_CTRL_AUDIO &=
110 ~ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AIRWB_AUDIO_MASK;
111 temp = ANADIG_MISC->VDDSOC2PLL_AI_CTRL_AUDIO;
112 temp &= ~ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AI_ADDR_AUDIO_MASK;
113 temp |= ((uint32_t)addr << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AI_ADDR_AUDIO_SHIFT) &
114 ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AI_ADDR_AUDIO_MASK;
115 ANADIG_MISC->VDDSOC2PLL_AI_CTRL_AUDIO = temp;
116 ANADIG_MISC->VDDSOC2PLL_AI_WDATA_AUDIO = wdata; /* write ai data */
117 ANADIG_MISC->VDDSOC2PLL_AI_CTRL_AUDIO ^=
118 ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AITOGGLE_AUDIO_MASK; /* toggle */
119 do
120 {
121 toggle_done =
122 (ANADIG_MISC->VDDSOC2PLL_AI_CTRL_AUDIO &
123 ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AITOGGLE_DONE_AUDIO_MASK); /* wait toggle done
124 toggle */
125 } while (toggle_done == pre_toggle_done);
126 ANADIG_MISC->VDDSOC2PLL_AI_CTRL_AUDIO &=
127 ~ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AIRWB_AUDIO_MASK;
128 }
129 else
130 {
131 pre_toggle_done =
132 (ANADIG_MISC->VDDSOC2PLL_AI_CTRL_AUDIO &
133 ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AITOGGLE_DONE_AUDIO_MASK); /* get pre_toggle_done
134 */
135
136 temp = ANADIG_MISC->VDDSOC2PLL_AI_CTRL_AUDIO;
137 temp &= ~ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AIRWB_AUDIO_MASK;
138 temp |= (1UL << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AIRWB_AUDIO_SHIFT) &
139 ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AIRWB_AUDIO_MASK;
140 ANADIG_MISC->VDDSOC2PLL_AI_CTRL_AUDIO = temp;
141
142 temp = ANADIG_MISC->VDDSOC2PLL_AI_CTRL_AUDIO;
143 temp &= ~ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AI_ADDR_AUDIO_MASK;
144 temp |= ((uint32_t)addr << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AI_ADDR_AUDIO_SHIFT) &
145 ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AI_ADDR_AUDIO_MASK;
146 ANADIG_MISC->VDDSOC2PLL_AI_CTRL_AUDIO = temp;
147 ANADIG_MISC->VDDSOC2PLL_AI_CTRL_AUDIO ^=
148 ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AITOGGLE_AUDIO_MASK; /* toggle */
149 do
150 {
151 toggle_done =
152 ANADIG_MISC->VDDSOC2PLL_AI_CTRL_AUDIO &
153 ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AITOGGLE_DONE_AUDIO_MASK; /* wait toggle done
154 toggle */
155 } while (toggle_done == pre_toggle_done);
156 rdata = ANADIG_MISC->VDDSOC2PLL_AI_RDATA_AUDIO; /* read data */
157 return rdata;
158 }
159 break;
160 case kAI_Itf_Video:
161 if (isWrite)
162 {
163 pre_toggle_done =
164 ANADIG_MISC->VDDSOC2PLL_AI_CTRL_VIDEO &
165 ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AITOGGLE_DONE_VIDEO_MASK; /* get pre_toggle_done */
166
167 ANADIG_MISC->VDDSOC2PLL_AI_CTRL_VIDEO &=
168 ~ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIRWB_VIDEO_MASK;
169
170 temp = ANADIG_MISC->VDDSOC2PLL_AI_CTRL_VIDEO;
171 temp &= ~ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIADDR_VIDEO_MASK;
172 temp |= ((uint32_t)addr << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIADDR_VIDEO_SHIFT) &
173 ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIADDR_VIDEO_MASK;
174 ANADIG_MISC->VDDSOC2PLL_AI_CTRL_VIDEO = temp;
175 ANADIG_MISC->VDDSOC2PLL_AI_WDATA_VIDEO = wdata; /* write ai data */
176 ANADIG_MISC->VDDSOC2PLL_AI_CTRL_VIDEO ^=
177 ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AITOGGLE_VIDEO_MASK; /* toggle */
178 do
179 {
180 toggle_done =
181 ANADIG_MISC->VDDSOC2PLL_AI_CTRL_VIDEO &
182 ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AITOGGLE_DONE_VIDEO_MASK; /* wait toggle done
183 toggle */
184 } while (toggle_done == pre_toggle_done);
185 ANADIG_MISC->VDDSOC2PLL_AI_CTRL_VIDEO &=
186 ~ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIRWB_VIDEO_MASK;
187 }
188 else
189 {
190 pre_toggle_done =
191 ANADIG_MISC->VDDSOC2PLL_AI_CTRL_VIDEO &
192 ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AITOGGLE_DONE_VIDEO_MASK; /* get pre_toggle_done */
193 temp = ANADIG_MISC->VDDSOC2PLL_AI_CTRL_VIDEO;
194 temp &= ~ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIRWB_VIDEO_MASK;
195 temp |= (1UL << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIRWB_VIDEO_SHIFT) &
196 ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIRWB_VIDEO_MASK;
197 ANADIG_MISC->VDDSOC2PLL_AI_CTRL_VIDEO = temp;
198
199 temp = ANADIG_MISC->VDDSOC2PLL_AI_CTRL_VIDEO;
200 temp &= ~ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIADDR_VIDEO_MASK;
201 temp |= ((uint32_t)addr << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIADDR_VIDEO_SHIFT) &
202 ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIADDR_VIDEO_MASK;
203 ANADIG_MISC->VDDSOC2PLL_AI_CTRL_VIDEO = temp;
204 ANADIG_MISC->VDDSOC2PLL_AI_CTRL_VIDEO ^=
205 ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AITOGGLE_VIDEO_MASK; /* toggle */
206 do
207 {
208 toggle_done =
209 ANADIG_MISC->VDDSOC2PLL_AI_CTRL_VIDEO &
210 ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AITOGGLE_DONE_VIDEO_MASK; /* wait toggle done
211 toggle */
212 } while (toggle_done == pre_toggle_done);
213 rdata = ANADIG_MISC->VDDSOC2PLL_AI_RDATA_VIDEO; /* read data */
214 return rdata;
215 }
216 break;
217 case kAI_Itf_400m:
218 if (isWrite)
219 {
220 pre_toggle_done =
221 ANADIG_MISC->VDDLPSR_AI400M_CTRL &
222 ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AITOGGLE_DONE_400M_MASK; /* get pre_toggle_done */
223 ANADIG_MISC->VDDLPSR_AI400M_CTRL &= ~ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AI400M_RWB_MASK;
224
225 temp = ANADIG_MISC->VDDLPSR_AI400M_CTRL;
226 temp &= ~ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AI400M_ADDR_MASK;
227 temp |= ((uint32_t)addr << ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AI400M_ADDR_SHIFT) &
228 ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AI400M_ADDR_MASK;
229 ANADIG_MISC->VDDLPSR_AI400M_CTRL = temp;
230 ANADIG_MISC->VDDLPSR_AI400M_WDATA = wdata; /* write ai data */
231 ANADIG_MISC->VDDLPSR_AI400M_CTRL ^=
232 ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AITOGGLE_400M_MASK; /* toggle */
233 do
234 {
235 toggle_done =
236 ANADIG_MISC->VDDLPSR_AI400M_CTRL &
237 ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AITOGGLE_DONE_400M_MASK; /* wait toggle done toggle */
238 } while (toggle_done == pre_toggle_done);
239 }
240 else
241 {
242 pre_toggle_done =
243 ANADIG_MISC->VDDLPSR_AI400M_CTRL &
244 ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AITOGGLE_DONE_400M_MASK; /* get pre_toggle_done */
245
246 temp = ANADIG_MISC->VDDLPSR_AI400M_CTRL;
247 temp &= ~ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AI400M_RWB_MASK;
248 temp |= (1UL << ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AI400M_RWB_SHIFT) &
249 ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AI400M_RWB_MASK;
250 ANADIG_MISC->VDDLPSR_AI400M_CTRL = temp;
251
252 temp = ANADIG_MISC->VDDLPSR_AI400M_CTRL;
253 temp &= ~ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AI400M_ADDR_MASK;
254 temp |= ((uint32_t)addr << ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AI400M_ADDR_SHIFT) &
255 ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AI400M_ADDR_MASK;
256 ANADIG_MISC->VDDLPSR_AI400M_CTRL = temp;
257 ANADIG_MISC->VDDLPSR_AI400M_CTRL ^=
258 ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AITOGGLE_400M_MASK; /* toggle */
259 do
260 {
261 toggle_done =
262 ANADIG_MISC->VDDLPSR_AI400M_CTRL &
263 ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AITOGGLE_DONE_400M_MASK; /* wait toggle done toggle */
264 } while (toggle_done == pre_toggle_done);
265 rdata = ANADIG_MISC->VDDLPSR_AI400M_RDATA; /* read data */
266 return rdata;
267 }
268 break;
269 case kAI_Itf_Temp:
270 if (isWrite)
271 {
272 ANADIG_MISC->VDDLPSR_AI_CTRL &= ~ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AIRWB_MASK;
273
274 temp = ANADIG_MISC->VDDLPSR_AI_CTRL;
275 temp &= ~ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AI_ADDR_MASK;
276 temp |= ((uint32_t)addr << ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AI_ADDR_SHIFT) &
277 ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AI_ADDR_MASK;
278 ANADIG_MISC->VDDLPSR_AI_CTRL = temp;
279 ANADIG_MISC->VDDLPSR_AI_WDATA = wdata; /* write ai data */
280 ANADIG_TEMPSENSOR->TEMPSENSOR ^= ANADIG_TEMPSENSOR_TEMPSENSOR_TEMPSNS_AI_TOGGLE_MASK; /* toggle */
281 }
282 else
283 {
284 temp = ANADIG_MISC->VDDLPSR_AI_CTRL;
285 temp &= ~ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AIRWB_MASK;
286 temp |= (1UL << ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AIRWB_SHIFT) &
287 ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AIRWB_MASK;
288 ANADIG_MISC->VDDLPSR_AI_CTRL = temp;
289
290 temp = ANADIG_MISC->VDDLPSR_AI_CTRL;
291 temp &= ~ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AI_ADDR_MASK;
292 temp |= ((uint32_t)addr << ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AI_ADDR_SHIFT) &
293 ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AI_ADDR_MASK;
294 ANADIG_MISC->VDDLPSR_AI_CTRL = temp;
295 ANADIG_TEMPSENSOR->TEMPSENSOR ^= ANADIG_TEMPSENSOR_TEMPSENSOR_TEMPSNS_AI_TOGGLE_MASK; /* toggle */
296 rdata = ANADIG_MISC->VDDLPSR_AI_RDATA_TMPSNS; /* read data */
297 return rdata;
298 }
299 break;
300 case kAI_Itf_Bandgap:
301 if (isWrite)
302 {
303 ANADIG_MISC->VDDLPSR_AI_CTRL &= ~ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AIRWB_MASK;
304
305 temp = ANADIG_MISC->VDDLPSR_AI_CTRL;
306 temp &= ~ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AI_ADDR_MASK;
307 temp |= ((uint32_t)addr << ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AI_ADDR_SHIFT) &
308 ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AI_ADDR_MASK;
309 ANADIG_MISC->VDDLPSR_AI_CTRL = temp;
310 ANADIG_MISC->VDDLPSR_AI_WDATA = wdata; /* write ai data */
311 ANADIG_PMU->PMU_REF_CTRL ^= ANADIG_PMU_PMU_REF_CTRL_REF_AI_TOGGLE_MASK; /* toggle */
312 }
313 else
314 {
315 temp = ANADIG_MISC->VDDLPSR_AI_CTRL;
316 temp &= ~ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AIRWB_MASK;
317 temp |= (1UL << ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AIRWB_SHIFT) &
318 ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AIRWB_MASK;
319 ANADIG_MISC->VDDLPSR_AI_CTRL = temp;
320
321 temp = ANADIG_MISC->VDDLPSR_AI_CTRL;
322 temp &= ~ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AI_ADDR_MASK;
323 temp |= ((uint32_t)addr << ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AI_ADDR_SHIFT) &
324 ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AI_ADDR_MASK;
325 ANADIG_MISC->VDDLPSR_AI_CTRL = temp;
326 ANADIG_PMU->PMU_REF_CTRL ^= ANADIG_PMU_PMU_REF_CTRL_REF_AI_TOGGLE_MASK; /* toggle */
327 rdata = ANADIG_MISC->VDDLPSR_AI_RDATA_REFTOP; /* read data */
328 return rdata;
329 }
330 break;
331 default:
332 /* This branch should never be hit. */
333 break;
334 }
335 return 0;
336 }
337
ANATOP_AI_Write(anatop_ai_itf_t itf,anatop_ai_reg_t addr,uint32_t wdata)338 void ANATOP_AI_Write(anatop_ai_itf_t itf, anatop_ai_reg_t addr, uint32_t wdata)
339 {
340 (void)ANATOP_AI_Access(itf, true, addr, wdata);
341 }
342
ANATOP_AI_Read(anatop_ai_itf_t itf,anatop_ai_reg_t addr)343 uint32_t ANATOP_AI_Read(anatop_ai_itf_t itf, anatop_ai_reg_t addr)
344 {
345 uint32_t rdata;
346 rdata = ANATOP_AI_Access(itf, false, addr, 0);
347 return rdata;
348 }
349
ANATOP_AI_WriteWithMaskShift(anatop_ai_itf_t itf,anatop_ai_reg_t addr,uint32_t wdata,uint32_t mask,uint32_t shift)350 void ANATOP_AI_WriteWithMaskShift(
351 anatop_ai_itf_t itf, anatop_ai_reg_t addr, uint32_t wdata, uint32_t mask, uint32_t shift)
352 {
353 uint32_t rdata;
354 rdata = ANATOP_AI_Read(itf, addr);
355 rdata = (rdata & (~mask)) | ((wdata << shift) & mask);
356 ANATOP_AI_Write(itf, addr, rdata);
357 }
358
