1 /*
2 * Copyright 2021, 2024 NXP
3 * All rights reserved.
4 *
5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8
9 #include "fsl_adapter_rfcommon.h"
10 #include "fsl_adapter_rpmsg.h"
11 #include "fsl_adapter_rfimu.h"
12 #if defined(IMU_GDMA_ENABLE) && (IMU_GDMA_ENABLE == 1)
13 #include "fsl_gdma.h"
14 #endif
15
16 /*******************************************************************************
17 * Definitions
18 ******************************************************************************/
19 #if defined(configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY)
20 #ifndef IMU_ISR_PRIORITY
21 #define IMU_ISR_PRIORITY (configLIBRARY_MAX_SYSCALL_INTERRUPT_PRIORITY)
22 #endif
23 #else
24 #ifndef IMU_ISR_PRIORITY
25 #define IMU_ISR_PRIORITY (2U)
26 #endif
27 #endif
28
29 #ifndef IMU_LINK_WAIT_DELAY_MS
30 #define IMU_LINK_WAIT_DELAY_MS 1U
31 #endif
32
33 #ifndef RPMSG_ALLOC_FAILED_DELAY_MS
34 #define RPMSG_ALLOC_FAILED_DELAY_MS 1U
35 #endif
36
37 #ifndef RPMSG_ALLOC_RETRY_COUNT
38 #define RPMSG_ALLOC_RETRY_COUNT 10U
39 #endif
40
41 #if defined(CPU2)
42 #define os_InterruptMaskClear(irq_num) DisableIRQ((IRQn_Type)irq_num)
43 #define os_InterruptMaskSet(irq_num) EnableIRQ((IRQn_Type)irq_num)
44 #define os_ClearPendingISR(irq_num) NVIC_ClearPendingIRQ((IRQn_Type)irq_num)
45 #else
46 #define os_InterruptMaskClear(irq_num) DisableIRQ(irq_num)
47 #define os_InterruptMaskSet(irq_num) EnableIRQ(irq_num)
48 #define os_ClearPendingISR(irq_num) NVIC_ClearPendingIRQ(irq_num)
49 #endif
50
51 #if defined(IMU_GDMA_ENABLE) && (IMU_GDMA_ENABLE == 1)
52 #define HAL_GDMA GDMA
53 #define HAL_GDMA_CH 0
54 #define HAL_GDMA_IRQn GDMA_IRQn
55 #define HAL_GDMA_DONE_EVENT (1U << 0U)
56 #define GDMA_ISR_PRIORITY IMU_ISR_PRIORITY
57 #define HAL_IMU_MEMCPY HAL_ImuGdmaCopyData
58 #else
59 #define HAL_IMU_MEMCPY memcpy
60 #endif
61
62 /*******************************************************************************
63 * Declaration
64 ******************************************************************************/
65 /*! IMU handle instance for each IMU link */
66 static hal_imu_handle_t imuHandleCh[kIMU_LinkMax];
67
68 /*! IMU interrput callback for each IMU link */
69 static imu_irq_callback_t imuIrqCallback[kIMU_LinkMax];
70
71 /*! IMU message sequence number */
72 static uint8_t seq_num = 0;
73
74 /*! IMU initializtion flag
75 bit 0: flag for IMU link #0
76 bit 1: flag for IMU link #1
77 */
78 static uint8_t imu_init_flag = 0;
79
80 /*! RPMSG initializtion flag
81 */
82 static uint8_t rpmsg_init_flag = 0;
83
84 /*! imu task created flag
85 */
86 static uint8_t imu_task_flag = 0;
87
88 #ifndef CPU2
89 /*! Sleep flag address between CPU1 and CPU3 or CPU2 and CPU3 */
90 #define IMU_SLEEP_FLAG13 0x4138248C
91 #define IMU_SLEEP_FLAG23 0x443C2588
92 #define IMU_SLEEP_FLAG_ADDR(imuLinkId) \
93 (((imuLinkId) == kIMU_LinkCpu1Cpu3) ? ((uint32_t *)IMU_SLEEP_FLAG13) : ((uint32_t *)IMU_SLEEP_FLAG23))
94 #endif
95
96 /*! wait imu task lock
97 */
98 #if (defined(USE_RTOS) && (USE_RTOS > 0U))
99 #ifdef __ZEPHYR__
100 struct k_mutex imu_task_lock;
101 #else
102 static OSA_MUTEX_HANDLE_DEFINE(imu_task_lock);
103 #endif
104 #endif
105 /*******************************************************************************
106 * Code
107 ******************************************************************************/
108 #if defined(CPU2)
109 extern IMU_Msg_Wrapper_short_t __attribute__((aligned(4))) SQRAM_CPU12_MBOX;
110 extern IMU_Msg_Wrapper_long_t __attribute__((aligned(4))) SQRAM_CPU23_MBOX;
111 volatile static IMU_Msg_Wrapper_short_t *imuMsgQ12 = &SQRAM_CPU12_MBOX;
112 volatile static IMU_Msg_Wrapper_long_t *imuMsgQ23 = &SQRAM_CPU23_MBOX;
113 __attribute__((section(".smu_cpu23_txq"))) volatile static uint8_t __attribute__((aligned(4)))
114 rpmsgTxBuf23[RPMSG_TXQ23_BUFSIZE][RPMSG_TXQ23_BUFLENGTH];
115
116 static void HAL_ImuMain(void *argv);
117 static OSA_TASK_HANDLE_DEFINE(ImuTaskHandle);
118 static OSA_TASK_DEFINE(HAL_ImuMain, IMU_TASK_PRIORITY, 1, IMU_TASK_STACK_SIZE, 0);
119 OSA_EVENT_HANDLE_DEFINE(ImuQFlagsRef);
120 #else
121 __attribute__((section(".smu_cpu13_mbox"))) static volatile IMU_Msg_Wrapper_long_t __attribute__((aligned(4)))
122 SQRAM_CPU13_MBOX;
123 __attribute__((section(".smu_cpu23_mbox"))) static volatile IMU_Msg_Wrapper_long_t __attribute__((aligned(4)))
124 SQRAM_CPU23_MBOX;
125 static volatile IMU_Msg_Wrapper_long_t *imuMsgQ13 = &SQRAM_CPU13_MBOX;
126 static volatile IMU_Msg_Wrapper_long_t *imuMsgQ23 = &SQRAM_CPU23_MBOX;
127 __attribute__((section(".smu_cpu31_txq"))) static volatile uint8_t __attribute__((aligned(4)))
128 rpmsgTxBuf13[RPMSG_TXQ13_BUFSIZE][RPMSG_TXQ13_BUFLENGTH];
129 __attribute__((section(".smu_cpu32_txq"))) static volatile uint8_t __attribute__((aligned(4)))
130 rpmsgTxBuf23[RPMSG_TXQ23_BUFSIZE][RPMSG_TXQ23_BUFLENGTH];
131
132 /* seperate CPU2 to CPU3 and CPU1 to CPU3 IMU RX tasks */
133 #ifdef __ZEPHYR__
134 static void HAL_ImuMainCpu13(void *argv1, void *argv2, void *argv3);
135 static void HAL_ImuMainCpu23(void *argv1, void *argv2, void *argv3);
136
137 K_THREAD_STACK_DEFINE(ImuTaskStackCpu13, IMU_TASK_STACK_SIZE);
138 K_THREAD_STACK_DEFINE(ImuTaskStackCpu23, IMU_TASK_STACK_SIZE);
139
140 k_tid_t ImuTaskCpu13;
141 k_tid_t ImuTaskCpu23;
142
143 K_EVENT_DEFINE(ImuQ13FlagsRef);
144 K_EVENT_DEFINE(ImuQ23FlagsRef);
145
146 struct k_thread ImuTaskHandleCpu13;
147 struct k_thread ImuTaskHandleCpu23;
148 #else
149 static void HAL_ImuMainCpu13(void *argv);
150 static void HAL_ImuMainCpu23(void *argv);
151
152 static OSA_TASK_HANDLE_DEFINE(ImuTaskHandleCpu13);
153 static OSA_TASK_HANDLE_DEFINE(ImuTaskHandleCpu23);
154 static OSA_TASK_DEFINE(HAL_ImuMainCpu13, IMU_TASK_PRIORITY, 1, IMU_TASK_STACK_SIZE, 0);
155 static OSA_TASK_DEFINE(HAL_ImuMainCpu23, IMU_TASK_PRIORITY, 1, IMU_TASK_STACK_SIZE, 0);
156 OSA_EVENT_HANDLE_DEFINE(ImuQ13FlagsRef);
157 OSA_EVENT_HANDLE_DEFINE(ImuQ23FlagsRef);
158 #endif /* __ZEPHYR__ */
159 #endif
160
161 #ifdef __ZEPHYR__
162 struct k_event rpmsgQFlagsRef;
163 #else
164 OSA_EVENT_HANDLE_DEFINE(rpmsgQFlagsRef);
165 #endif /* __ZEPHYR__ */
166
167 #if defined(IMU_GDMA_ENABLE) && (IMU_GDMA_ENABLE == 1)
168 static gdma_handle_t gdmaHandle;
169 OSA_SEMAPHORE_HANDLE_DEFINE(gdmaSemHandle);
170 OSA_EVENT_HANDLE_DEFINE(gdmaFlagsRef);
171 #endif
172
173 /**************Internal helper functions***********************/
174 /// \cond
175 #if defined(IMU_GDMA_ENABLE) && (IMU_GDMA_ENABLE == 1)
HAL_GdmaCallback(gdma_handle_t * handle,void * userData,uint32_t interrupts)176 static void HAL_GdmaCallback(gdma_handle_t *handle, void *userData, uint32_t interrupts)
177 {
178 if (0UL != (interrupts & kGDMA_TransferDoneFlag))
179 {
180 (void)OSA_EventSet((osa_event_handle_t)gdmaFlagsRef, HAL_GDMA_DONE_EVENT);
181 }
182 }
183
HAL_InitGdma(void)184 static void HAL_InitGdma(void)
185 {
186 if (gdmaHandle.callback)
187 return;
188
189 GDMA_Init(HAL_GDMA);
190 GDMA_CreateHandle(&gdmaHandle, HAL_GDMA, HAL_GDMA_CH);
191 GDMA_SetCallback(&gdmaHandle, HAL_GdmaCallback, NULL);
192 OSA_SemaphoreCreate(gdmaSemHandle, 1U);
193 (void)OSA_EventCreate(gdmaFlagsRef, 1U);
194 NVIC_SetPriority(GDMA_IRQn, GDMA_ISR_PRIORITY);
195 }
196
HAL_ImuGdmaCopyData(void * destAddr,void * srcAddr,uint32_t len)197 void HAL_ImuGdmaCopyData(void *destAddr, void *srcAddr, uint32_t len)
198 {
199 uint32_t Events;
200 gdma_channel_xfer_config_t xferConfig = {0};
201
202 xferConfig.srcAddr = (uint32_t)srcAddr;
203 xferConfig.destAddr = (uint32_t)destAddr;
204 xferConfig.linkListAddr = 0; /* Don't use LLI */
205 xferConfig.ahbProt = kGDMA_ProtPrevilegedMode;
206 xferConfig.srcBurstSize = kGDMA_BurstSize16;
207 xferConfig.destBurstSize = kGDMA_BurstSize16;
208 xferConfig.srcWidth = kGDMA_TransferWidth1Byte;
209 xferConfig.destWidth = kGDMA_TransferWidth1Byte;
210 xferConfig.srcAddrInc = true;
211 xferConfig.destAddrInc = true;
212 xferConfig.transferLen = len;
213 xferConfig.enableLinkList = false;
214
215 if (KOSA_StatusSuccess == OSA_SemaphoreWait(gdmaSemHandle, osaWaitForever_c))
216 {
217 GDMA_SubmitTransfer(&gdmaHandle, &xferConfig);
218 GDMA_StartTransfer(&gdmaHandle);
219 /* Wait for GMDA transfer done. */
220 (void)OSA_EventWait((osa_event_handle_t)gdmaFlagsRef, HAL_GDMA_DONE_EVENT, 0, osaWaitForever_c, &Events);
221 OSA_SemaphorePost(gdmaSemHandle);
222 }
223 }
224 #endif
225
HAL_ImuSetCpuReadyFlag(uint8_t cpuId)226 static void HAL_ImuSetCpuReadyFlag(uint8_t cpuId)
227 {
228 }
229
HAL_ImuGetCpuReadyFlag(uint8_t cpuId)230 bool HAL_ImuGetCpuReadyFlag(uint8_t cpuId)
231 {
232 return TRUE;
233 }
234
235 /*!
236 * @brief
237 * Create a new rpmsg endpoint, which can be used
238 * for communication.
239 *
240 * @param handle RPMsg instance
241 * @param addr source endpoint address
242 *
243 * @return RL_NULL if not found, node pointer containing the ept on success
244 *
245 */
HAL_RpmsgGetEndpointFromAddr(hal_imu_handle_t * imuHandle,uint32_t addr)246 static hal_rpmsg_handle_t HAL_RpmsgGetEndpointFromAddr(hal_imu_handle_t *imuHandle, uint32_t addr)
247 {
248 LIST_ELEM_st *cur;
249 hal_rpmsg_state_t *pEnd;
250
251 assert(NULL != imuHandle);
252
253 list_for_each(cur, &imuHandle->eptList)
254 {
255 pEnd = (hal_rpmsg_state_t *)cur;
256 if (pEnd->local_addr == addr)
257 {
258 return pEnd;
259 }
260 }
261
262 return NULL;
263 }
264
HAL_RpmsgCreateEndpoint(hal_rpmsg_handle_t handle)265 static hal_rpmsg_handle_t HAL_RpmsgCreateEndpoint(hal_rpmsg_handle_t handle)
266 {
267 hal_imu_handle_t *imuHandle;
268 hal_rpmsg_state_t *rpmsgHandle;
269 assert(NULL != handle);
270
271 rpmsgHandle = (hal_rpmsg_state_t *)handle;
272 imuHandle = &imuHandleCh[rpmsgHandle->imuLink];
273 // env_lock_mutex(rpmsgHandle->lock);
274 {
275 if (NULL == HAL_RpmsgGetEndpointFromAddr(imuHandle, rpmsgHandle->local_addr))
276 {
277 LIST_addTail(&imuHandle->eptList, &rpmsgHandle->eptLink);
278 // env_unlock_mutex(rpmsgHandle->lock);
279 return rpmsgHandle;
280 }
281 }
282 // env_unlock_mutex(rpmsgHandle->lock);
283 return NULL;
284 }
285
HAL_RpmsgDestroyEndpoint(hal_rpmsg_handle_t handle)286 static hal_rpmsg_status_t HAL_RpmsgDestroyEndpoint(hal_rpmsg_handle_t handle)
287 {
288 hal_imu_handle_t *imuHandle;
289 hal_rpmsg_state_t *rpmsgHandle;
290 assert(NULL != handle);
291
292 rpmsgHandle = (hal_rpmsg_state_t *)handle;
293 imuHandle = &imuHandleCh[rpmsgHandle->imuLink];
294
295 // env_lock_mutex(rpmsgHandle->lock);
296 {
297 rpmsgHandle = HAL_RpmsgGetEndpointFromAddr(imuHandle, rpmsgHandle->local_addr);
298
299 if (NULL == rpmsgHandle)
300 {
301 // env_unlock_mutex(rpmsgHandle->lock);
302 return kStatus_HAL_RpmsgError;
303 }
304 LIST_remove(&imuHandle->eptList, &rpmsgHandle->eptLink);
305 }
306 // env_unlock_mutex(rpmsgHandle->lock);
307 return kStatus_HAL_RpmsgSuccess;
308 }
309
HAL_ImuGetWlanTxBuf(hal_imu_handle_t * imuHandle)310 static uint8_t *HAL_ImuGetWlanTxBuf(hal_imu_handle_t *imuHandle)
311 {
312 uint32_t wlanTxBuf;
313 IMU_WLAN_TXQ_CTRL_st *wlanTxqCtl;
314
315 assert(NULL != imuHandle);
316 wlanTxqCtl = &imuHandle->wlanTxqCtl;
317
318 if (IS_WLAN_TXBQ_EMPTY(wlanTxqCtl))
319 {
320 return NULL;
321 }
322 else
323 {
324 wlanTxBuf = wlanTxqCtl->txBufQue[wlanTxqCtl->readIndex & IMU_TXQ_ENTRY_MASK];
325 INCR_WLAN_TXBQ_RD_INDEX(wlanTxqCtl, 1U);
326 return (uint8_t *)wlanTxBuf;
327 }
328 }
329
HAL_ImuPutWlanTxBuf(hal_imu_handle_t * imuHandle,uint8_t * txBuf)330 static hal_rpmsg_status_t HAL_ImuPutWlanTxBuf(hal_imu_handle_t *imuHandle, uint8_t *txBuf)
331 {
332 hal_rpmsg_status_t state = kStatus_HAL_RpmsgSuccess;
333 IMU_WLAN_TXQ_CTRL_st *wlanTxqCtl;
334
335 assert(NULL != imuHandle);
336 wlanTxqCtl = &imuHandle->wlanTxqCtl;
337
338 if (IS_WLAN_TXBQ_FULL(wlanTxqCtl))
339 {
340 state = kStatus_HAL_RpmsgError;
341 }
342 else
343 {
344 wlanTxqCtl->txBufQue[wlanTxqCtl->writeIndex & IMU_TXQ_ENTRY_MASK] = (uint32_t)txBuf;
345 INCR_WLAN_TXBQ_WR_INDEX(wlanTxqCtl, 1U);
346 }
347
348 return state;
349 }
350
HAL_RpmsgGetTxBuf(hal_imu_handle_t * imuHandle)351 static uint8_t *HAL_RpmsgGetTxBuf(hal_imu_handle_t *imuHandle)
352 {
353 uint8_t *rpmsgTxBuf = NULL;
354 RPMSG_TXQ_CTRL_st *rpmsgTxqCtl;
355 OSA_SR_ALLOC();
356
357 assert(NULL != imuHandle);
358 rpmsgTxqCtl = &imuHandle->rpmsgTxqCtl;
359
360 OSA_ENTER_CRITICAL();
361
362 do
363 {
364 if (imuHandle->imuLink == (uint8_t)kIMU_LinkCpu2Cpu3)
365 {
366 if (IS_RPMSG_TXBQ23_EMPTY(rpmsgTxqCtl))
367 {
368 break;
369 }
370 else
371 {
372 rpmsgTxBuf = (uint8_t *)(rpmsgTxqCtl->txBufQue[rpmsgTxqCtl->readIndex & RPMSG_TXQ23_ENTRY_MASK]);
373 INCR_RPMSG_TXBQ23_RD_INDEX(rpmsgTxqCtl, 1U);
374 }
375 }
376 else
377 {
378 if (IS_RPMSG_TXBQ13_EMPTY(rpmsgTxqCtl))
379 {
380 break;
381 }
382 else
383 {
384 rpmsgTxBuf = (uint8_t *)(rpmsgTxqCtl->txBufQue[rpmsgTxqCtl->readIndex & RPMSG_TXQ13_ENTRY_MASK]);
385 INCR_RPMSG_TXBQ13_RD_INDEX(rpmsgTxqCtl, 1U);
386 }
387 }
388 } while (false);
389
390 OSA_EXIT_CRITICAL();
391
392 return rpmsgTxBuf;
393 }
394
HAL_RpmsgPutTxBuf(hal_imu_handle_t * imuHandle,uint8_t * txBuf)395 static hal_rpmsg_status_t HAL_RpmsgPutTxBuf(hal_imu_handle_t *imuHandle, uint8_t *txBuf)
396 {
397 hal_rpmsg_status_t state = kStatus_HAL_RpmsgSuccess;
398 RPMSG_TXQ_CTRL_st *rpmsgTxqCtl;
399 OSA_SR_ALLOC();
400
401 assert(NULL != imuHandle);
402 rpmsgTxqCtl = &imuHandle->rpmsgTxqCtl;
403
404 OSA_ENTER_CRITICAL();
405
406 if (imuHandle->imuLink == (uint8_t)kIMU_LinkCpu2Cpu3)
407 {
408 if (IS_RPMSG_TXBQ23_FULL(rpmsgTxqCtl))
409 {
410 state = kStatus_HAL_RpmsgError;
411 }
412 else
413 {
414 rpmsgTxqCtl->txBufQue[rpmsgTxqCtl->writeIndex & RPMSG_TXQ23_ENTRY_MASK] = (uint32_t)txBuf;
415 INCR_RPMSG_TXBQ23_WR_INDEX(rpmsgTxqCtl, 1U);
416 }
417 }
418 else
419 {
420 if (IS_RPMSG_TXBQ13_FULL(rpmsgTxqCtl))
421 {
422 state = kStatus_HAL_RpmsgError;
423 }
424 else
425 {
426 rpmsgTxqCtl->txBufQue[rpmsgTxqCtl->writeIndex & RPMSG_TXQ13_ENTRY_MASK] = (uint32_t)txBuf;
427 INCR_RPMSG_TXBQ13_WR_INDEX(rpmsgTxqCtl, 1U);
428 }
429 }
430
431 OSA_EXIT_CRITICAL();
432
433 return state;
434 }
435
HAL_ImuLinkIsUp(uint8_t imuLink)436 hal_rpmsg_status_t HAL_ImuLinkIsUp(uint8_t imuLink)
437 {
438 hal_imu_handle_t *imuHandle;
439
440 assert((uint8_t)kIMU_LinkMax > imuLink);
441 imuHandle = &imuHandleCh[imuLink];
442
443 if ((uint8_t)IMU_INITIALIZED == imuHandle->imuSyncState)
444 {
445 return kStatus_HAL_RpmsgSuccess;
446 }
447 else
448 {
449 return kStatus_HAL_RpmsgError;
450 }
451 }
452
HAL_ImuResetWlanTxq(uint8_t imuLink)453 void HAL_ImuResetWlanTxq(uint8_t imuLink)
454 {
455 hal_imu_handle_t *imuHandle = NULL;
456
457 imuHandle = &imuHandleCh[imuLink];
458 imuHandle->wlanTxqCtl.writeIndex = 0;
459 imuHandle->wlanTxqCtl.readIndex = 0;
460 }
461
HAL_ImuSendMsgBlockingCommon(hal_imu_handle_t * imuHandle,uint8_t type,uint8_t subtype,uint8_t * data,uint32_t length,bool lockTxFifo)462 static hal_rpmsg_status_t HAL_ImuSendMsgBlockingCommon(
463 hal_imu_handle_t *imuHandle, uint8_t type, uint8_t subtype, uint8_t *data, uint32_t length, bool lockTxFifo)
464 {
465 IMU_Msg_t *imuMsg;
466 IMU_Msg_t localImuMsg;
467 OSA_SR_ALLOC();
468 int32_t ret = 0;
469
470 assert(NULL != imuHandle);
471 assert(IMU_PAYLOAD_SIZE >= length);
472
473 (void)memset((void *)&localImuMsg, 0, sizeof(IMU_Msg_t));
474
475 localImuMsg.Hdr.type = type;
476 localImuMsg.Hdr.sub_type = subtype;
477 localImuMsg.Hdr.seq_num = seq_num & (uint8_t)0xff;
478
479 switch ((imu_msg_type_t)type)
480 {
481 case IMU_MSG_CONTROL:
482 if (((uint8_t)IMU_MSG_CONTROL_TX_BUF_ADDR == subtype) ||
483 ((uint8_t)IMU_MSG_CONTROL_FREE_RX_BUF == subtype) ||
484 ((uint8_t)IMU_MSG_CONTROL_CMD_BUF_ADDR == subtype) || ((uint8_t)IMU_MSG_CONTROL_EVT_ACK == subtype) ||
485 ((uint8_t)IMU_MSG_CONTROL_COMMAND_RSP_ACK == subtype) ||
486 ((uint8_t)IMU_MSG_CONTROL_RPMSG_EPT_QUIRY == subtype) ||
487 ((uint8_t)IMU_MSG_CONTROL_RPMSG_EPT_QUIRY_RSP == subtype) ||
488 ((uint8_t)IMU_MSG_CONTROL_RPMSG_BUF_FREE == subtype) ||
489 ((uint8_t)IMU_MSG_CONTROL_EVT_DUMP == subtype) || ((uint8_t)IMU_MSG_CONTROL_ERROR == subtype))
490 {
491 (void)memcpy((void *)&localImuMsg.PayloadPtr[0], data, length << 2U);
492 localImuMsg.Hdr.length = (uint8_t)length;
493 }
494 break;
495 case IMU_MSG_COMMAND:
496 if (imuHandle->cmd_buffer_available)
497 {
498 localImuMsg.Hdr.length = 1;
499 localImuMsg.PayloadPtr[0] = (uint32_t)imuHandle->cmd_buffer;
500 }
501 else
502 {
503 return kStatus_HAL_RpmsgError;
504 }
505 break;
506 case IMU_MSG_TX_DATA:
507 localImuMsg.Hdr.length = 1;
508 localImuMsg.PayloadPtr[0] = (uint32_t)data;
509 break;
510 case IMU_MSG_MULTI_TX_DATA:
511 (void)memcpy((void *)&localImuMsg.PayloadPtr[0], imuHandle->imuMsgBuf, (imuHandle->imuMsgBufIdx) << 2U);
512 localImuMsg.Hdr.length = imuHandle->imuMsgBufIdx;
513 imuHandle->imuMsgBufIdx = 0;
514 break;
515 case IMU_MSG_RPMSG:
516 (void)memcpy((void *)&localImuMsg.PayloadPtr[0], data, length << 2U);
517 localImuMsg.Hdr.length = length;
518 break;
519 default:
520 // Do nothing for the commands without expansion.
521 break;
522 }
523
524 /* Added at 02/18/2022, in case second task overwriting imuMsg*/
525 while (IMU_TX_FIFO_ALMOST_FULL((imu_link_t)imuHandle->imuLink))
526 {
527 }
528
529 OSA_ENTER_CRITICAL();
530 imuMsg = (IMU_Msg_t *)&((IMU_MSG_SND_Q(imuHandle->imuLink))[IMU_WR_PTR(imuHandle->imuLink)]);
531 (void)memcpy(imuMsg, &localImuMsg, sizeof(IMU_Hdr_t) + ((uint32_t)localImuMsg.Hdr.length << 2U));
532 ret = IMU_SendMsgPtrBlocking((imu_link_t)imuHandle->imuLink, (uint32_t)imuMsg, lockTxFifo);
533 OSA_EXIT_CRITICAL();
534
535 if (0 == ret)
536 {
537 return kStatus_HAL_RpmsgSuccess;
538 }
539 else
540 {
541 return kStatus_HAL_RpmsgError;
542 }
543 }
544
HAL_ImuSendMsgBlocking(hal_imu_handle_t * imuHandle,uint8_t type,uint8_t subtype,uint8_t * data,uint32_t length)545 static hal_rpmsg_status_t HAL_ImuSendMsgBlocking(
546 hal_imu_handle_t *imuHandle, uint8_t type, uint8_t subtype, uint8_t *data, uint32_t length)
547 {
548 return HAL_ImuSendMsgBlockingCommon(imuHandle, type, subtype, data, length, FALSE);
549 }
550
HAL_ImuSendSync(hal_imu_handle_t * imuHandle)551 static hal_rpmsg_status_t HAL_ImuSendSync(hal_imu_handle_t *imuHandle)
552 {
553 hal_rpmsg_status_t rpmsgStatus = kStatus_HAL_RpmsgSuccess;
554 OSA_SR_ALLOC();
555 assert(NULL != imuHandle);
556
557 *IMU_MSG_CUR_MAGIC_P(imuHandle->imuLink) = IMU_SYNC_MAGIC_PATTERN;
558 while (IMU_SYNC_MAGIC_PATTERN != (*IMU_MSG_CUR_MAGIC_P((imu_link_t)imuHandle->imuLink)))
559 {
560 }
561
562 OSA_ENTER_CRITICAL();
563 if (((uint8_t)IMU_UNINITIALIZED == imuHandle->imuSyncState) &&
564 (IMU_SYNC_MAGIC_PATTERN == (*IMU_MSG_PEER_MAGIC_P(imuHandle->imuLink))))
565 {
566 if (kStatus_HAL_RpmsgSuccess ==
567 HAL_ImuSendMsgBlocking(imuHandle, (uint8_t)IMU_MSG_CONTROL, (uint8_t)IMU_MSG_CONTROL_SYNC, NULL, 0))
568 {
569 imuHandle->imuSyncState = (uint8_t)IMU_INITIALIZING;
570 seq_num++;
571 }
572 else
573 {
574 rpmsgStatus = kStatus_HAL_RpmsgError;
575 }
576 }
577 OSA_EXIT_CRITICAL();
578
579 return rpmsgStatus;
580 }
581
HAL_ImuSendRpmsgEptQuiry(hal_imu_handle_t * imuHandle,uint32_t addr)582 static hal_rpmsg_status_t HAL_ImuSendRpmsgEptQuiry(hal_imu_handle_t *imuHandle, uint32_t addr)
583 {
584 hal_rpmsg_status_t rpmsgStatus = kStatus_HAL_RpmsgSuccess;
585 OSA_SR_ALLOC();
586 assert(NULL != imuHandle);
587
588 if (kStatus_HAL_RpmsgError == HAL_ImuLinkIsUp(imuHandle->imuLink))
589 {
590 return kStatus_HAL_RpmsgError;
591 }
592
593 OSA_ENTER_CRITICAL();
594 if (kStatus_HAL_RpmsgSuccess == HAL_ImuSendMsgBlocking(imuHandle, (uint8_t)IMU_MSG_CONTROL,
595 (uint8_t)IMU_MSG_CONTROL_RPMSG_EPT_QUIRY, (uint8_t *)&addr,
596 1))
597 {
598 seq_num++;
599 }
600 else
601 {
602 rpmsgStatus = kStatus_HAL_RpmsgError;
603 }
604 OSA_EXIT_CRITICAL();
605
606 return rpmsgStatus;
607 }
608
HAL_ImuSendRpmsgEptQuiryRsp(hal_imu_handle_t * imuHandle,uint32_t addr,bool found)609 static hal_rpmsg_status_t HAL_ImuSendRpmsgEptQuiryRsp(hal_imu_handle_t *imuHandle, uint32_t addr, bool found)
610 {
611 hal_rpmsg_status_t rpmsgStatus = kStatus_HAL_RpmsgSuccess;
612 uint32_t quiryRsp[2];
613 OSA_SR_ALLOC();
614
615 assert(NULL != imuHandle);
616
617 if (kStatus_HAL_RpmsgError == HAL_ImuLinkIsUp(imuHandle->imuLink))
618 {
619 return kStatus_HAL_RpmsgError;
620 }
621
622 OSA_ENTER_CRITICAL();
623 quiryRsp[0] = addr;
624 if (TRUE == found)
625 {
626 quiryRsp[1] = 1;
627 }
628 else
629 {
630 quiryRsp[1] = 0;
631 }
632
633 if (kStatus_HAL_RpmsgSuccess == HAL_ImuSendMsgBlocking(imuHandle, (uint8_t)IMU_MSG_CONTROL,
634 (uint8_t)IMU_MSG_CONTROL_RPMSG_EPT_QUIRY_RSP,
635 (uint8_t *)&quiryRsp[0], 2))
636 {
637 seq_num++;
638 }
639 else
640 {
641 rpmsgStatus = kStatus_HAL_RpmsgError;
642 }
643 OSA_EXIT_CRITICAL();
644
645 return rpmsgStatus;
646 }
647
HAL_ImuSendRpmsgFreeBuf(hal_imu_handle_t * imuHandle,uint8_t * buf)648 static hal_rpmsg_status_t HAL_ImuSendRpmsgFreeBuf(hal_imu_handle_t *imuHandle, uint8_t *buf)
649 {
650 hal_rpmsg_status_t rpmsgStatus = kStatus_HAL_RpmsgSuccess;
651 OSA_SR_ALLOC();
652 assert(NULL != imuHandle);
653
654 if (kStatus_HAL_RpmsgError == HAL_ImuLinkIsUp(imuHandle->imuLink))
655 {
656 return kStatus_HAL_RpmsgError;
657 }
658
659 OSA_ENTER_CRITICAL();
660 if (kStatus_HAL_RpmsgSuccess ==
661 HAL_ImuSendMsgBlocking(imuHandle, (uint8_t)IMU_MSG_CONTROL, (uint8_t)IMU_MSG_CONTROL_RPMSG_BUF_FREE, buf, 1U))
662 {
663 seq_num++;
664 }
665 else
666 {
667 rpmsgStatus = kStatus_HAL_RpmsgError;
668 }
669 OSA_EXIT_CRITICAL();
670
671 return rpmsgStatus;
672 }
673
HAL_ImuSendEventAck(hal_imu_handle_t * imuHandle,uint8_t * rxBuf,uint8_t length)674 static hal_rpmsg_status_t HAL_ImuSendEventAck(hal_imu_handle_t *imuHandle, uint8_t *rxBuf, uint8_t length)
675 {
676 hal_rpmsg_status_t rpmsgStatus = kStatus_HAL_RpmsgSuccess;
677 OSA_SR_ALLOC();
678 assert(NULL != imuHandle);
679
680 if (kStatus_HAL_RpmsgError == HAL_ImuLinkIsUp(imuHandle->imuLink))
681 {
682 return kStatus_HAL_RpmsgError;
683 }
684
685 OSA_ENTER_CRITICAL();
686 if (kStatus_HAL_RpmsgSuccess ==
687 HAL_ImuSendMsgBlocking(imuHandle, (uint8_t)IMU_MSG_CONTROL, (uint8_t)IMU_MSG_CONTROL_EVT_ACK, rxBuf, length))
688 {
689 seq_num++;
690 }
691 else
692 {
693 rpmsgStatus = kStatus_HAL_RpmsgError;
694 }
695 OSA_EXIT_CRITICAL();
696
697 return rpmsgStatus;
698 }
699
HAL_ImuSendEventDumpAck(imu_link_t link,uint8_t * rxBuf,uint8_t length)700 hal_rpmsg_status_t HAL_ImuSendEventDumpAck(imu_link_t link, uint8_t *rxBuf, uint8_t length)
701 {
702 hal_imu_handle_t *imuHandle;
703 hal_rpmsg_status_t rpmsgStatus = kStatus_HAL_RpmsgSuccess;
704 OSA_SR_ALLOC();
705
706 assert(kIMU_LinkMax > link);
707 imuHandle = &imuHandleCh[link];
708
709 if (kStatus_HAL_RpmsgError == HAL_ImuLinkIsUp(imuHandle->imuLink))
710 {
711 return kStatus_HAL_RpmsgError;
712 }
713
714 OSA_ENTER_CRITICAL();
715 if (kStatus_HAL_RpmsgSuccess ==
716 HAL_ImuSendMsgBlocking(imuHandle, (uint8_t)IMU_MSG_CONTROL, (uint8_t)IMU_MSG_CONTROL_EVT_DUMP, rxBuf, length))
717 {
718 seq_num++;
719 }
720 else
721 {
722 rpmsgStatus = kStatus_HAL_RpmsgError;
723 }
724
725 OSA_EXIT_CRITICAL();
726
727 return rpmsgStatus;
728 }
729
HAL_ImuSendCommandRspAck(hal_imu_handle_t * imuHandle,uint8_t * rxBuf,uint8_t length)730 static hal_rpmsg_status_t HAL_ImuSendCommandRspAck(hal_imu_handle_t *imuHandle, uint8_t *rxBuf, uint8_t length)
731 {
732 hal_rpmsg_status_t rpmsgStatus = kStatus_HAL_RpmsgSuccess;
733 OSA_SR_ALLOC();
734 assert(NULL != imuHandle);
735
736 if (kStatus_HAL_RpmsgError == HAL_ImuLinkIsUp(imuHandle->imuLink))
737 {
738 return kStatus_HAL_RpmsgError;
739 }
740
741 OSA_ENTER_CRITICAL();
742 if (kStatus_HAL_RpmsgSuccess == HAL_ImuSendMsgBlocking(imuHandle, (uint8_t)IMU_MSG_CONTROL,
743 (uint8_t)IMU_MSG_CONTROL_COMMAND_RSP_ACK, rxBuf, length))
744 {
745 seq_num++;
746 }
747 else
748 {
749 rpmsgStatus = kStatus_HAL_RpmsgError;
750 }
751 OSA_EXIT_CRITICAL();
752
753 return rpmsgStatus;
754 }
755
HAL_ImuFreeRxBuf(hal_imu_handle_t * imuHandle,uint8_t * rxBuf,uint8_t length)756 static hal_rpmsg_status_t HAL_ImuFreeRxBuf(hal_imu_handle_t *imuHandle, uint8_t *rxBuf, uint8_t length)
757 {
758 hal_rpmsg_status_t rpmsgStatus = kStatus_HAL_RpmsgSuccess;
759 OSA_SR_ALLOC();
760 assert(NULL != imuHandle);
761
762 if (kStatus_HAL_RpmsgError == HAL_ImuLinkIsUp(imuHandle->imuLink))
763 {
764 return kStatus_HAL_RpmsgError;
765 }
766
767 OSA_ENTER_CRITICAL();
768 if (kStatus_HAL_RpmsgSuccess == HAL_ImuSendMsgBlocking(imuHandle, (uint8_t)IMU_MSG_CONTROL,
769 (uint8_t)IMU_MSG_CONTROL_FREE_RX_BUF, rxBuf, length))
770 {
771 seq_num++;
772 }
773 else
774 {
775 rpmsgStatus = kStatus_HAL_RpmsgError;
776 }
777 OSA_EXIT_CRITICAL();
778
779 return rpmsgStatus;
780 }
781
HAL_ImuSendCommand(uint8_t imuLink,uint8_t * cmdBuf,uint32_t length)782 hal_rpmsg_status_t HAL_ImuSendCommand(uint8_t imuLink, uint8_t *cmdBuf, uint32_t length)
783 {
784 hal_rpmsg_status_t rpmsgStatus = kStatus_HAL_RpmsgSuccess;
785 hal_imu_handle_t *imuHandle;
786 OSA_SR_ALLOC();
787
788 assert((uint8_t)kIMU_LinkMax > imuLink);
789 imuHandle = &imuHandleCh[imuLink];
790
791 if (kStatus_HAL_RpmsgError == HAL_ImuLinkIsUp(imuHandle->imuLink) || FALSE == imuHandle->cmd_buffer_available)
792 {
793 return kStatus_HAL_RpmsgError;
794 }
795
796 if (length != 0U)
797 {
798 // To be DMAed
799 (void)HAL_IMU_MEMCPY((void *)imuHandle->cmd_buffer, cmdBuf, length);
800 }
801 else
802 {
803 return kStatus_HAL_RpmsgError;
804 }
805
806 OSA_ENTER_CRITICAL();
807 if (kStatus_HAL_RpmsgSuccess == HAL_ImuSendMsgBlocking(imuHandle, (uint8_t)IMU_MSG_COMMAND, 0U, NULL, 0))
808 {
809 seq_num++;
810 imuHandle->cmd_buffer_available = FALSE;
811 }
812 else
813 {
814 rpmsgStatus = kStatus_HAL_RpmsgError;
815 }
816 OSA_EXIT_CRITICAL();
817
818 return rpmsgStatus;
819 }
820
HAL_ImuSendTxData(uint8_t imuLink,uint8_t * txBuf,uint32_t length)821 hal_rpmsg_status_t HAL_ImuSendTxData(uint8_t imuLink, uint8_t *txBuf, uint32_t length)
822 {
823 hal_rpmsg_status_t rpmsgStatus = kStatus_HAL_RpmsgSuccess;
824 hal_imu_handle_t *imuHandle;
825 uint8_t *wlan_tx_buf;
826 OSA_SR_ALLOC();
827
828 assert((uint8_t)kIMU_LinkMax > imuLink);
829 imuHandle = &imuHandleCh[imuLink];
830
831 if (kStatus_HAL_RpmsgError == HAL_ImuLinkIsUp(imuHandle->imuLink))
832 {
833 return kStatus_HAL_RpmsgError;
834 }
835
836 wlan_tx_buf = HAL_ImuGetWlanTxBuf(imuHandle);
837 if ((wlan_tx_buf != NULL) && (length != 0U))
838 {
839 // To be DMAed
840 (void)HAL_IMU_MEMCPY(wlan_tx_buf, txBuf, length);
841 }
842 else
843 {
844 return kStatus_HAL_RpmsgError;
845 }
846
847 OSA_ENTER_CRITICAL();
848 if (kStatus_HAL_RpmsgSuccess == HAL_ImuSendMsgBlocking(imuHandle, (uint8_t)IMU_MSG_TX_DATA, 0U, wlan_tx_buf, 1U))
849 {
850 seq_num++;
851 }
852 else
853 {
854 (void)HAL_ImuPutWlanTxBuf(imuHandle, wlan_tx_buf);
855 rpmsgStatus = kStatus_HAL_RpmsgError;
856 }
857 OSA_EXIT_CRITICAL();
858
859 return rpmsgStatus;
860 }
861
HAL_ImuAddWlanTxPacket(uint8_t imuLink,uint8_t * txBuf,uint32_t length)862 hal_rpmsg_status_t HAL_ImuAddWlanTxPacket(uint8_t imuLink, uint8_t *txBuf, uint32_t length)
863 {
864 hal_rpmsg_status_t rpmsgStatus = kStatus_HAL_RpmsgSuccess;
865 hal_imu_handle_t *imuHandle;
866 uint8_t *wlan_tx_buf;
867
868 assert((uint8_t)kIMU_LinkMax > imuLink);
869 assert(NULL != txBuf);
870 assert(0U != length);
871 imuHandle = &imuHandleCh[imuLink];
872
873 if (imuHandle->imuMsgBufIdx > IMU_PAYLOAD_SIZE - 1U)
874 {
875 return kStatus_HAL_RpmsgError;
876 }
877
878 wlan_tx_buf = HAL_ImuGetWlanTxBuf(imuHandle);
879
880 if (NULL == wlan_tx_buf)
881 {
882 return kStatus_HAL_RpmsgError;
883 }
884
885 // To be DMAed
886 (void)HAL_IMU_MEMCPY(wlan_tx_buf, txBuf, length);
887
888 imuHandle->imuMsgBuf[imuHandle->imuMsgBufIdx] = (uint32_t)wlan_tx_buf;
889 imuHandle->imuMsgBufIdx++;
890
891 return rpmsgStatus;
892 }
893
HAL_ImuAddWlanTxPacketExt(uint8_t imuLink,uint8_t * txBuf,uint32_t length,void (* cb)(void * destAddr,void * srcAddr,uint32_t len))894 hal_rpmsg_status_t HAL_ImuAddWlanTxPacketExt(uint8_t imuLink,
895 uint8_t *txBuf,
896 uint32_t length,
897 void (*cb)(void *destAddr, void *srcAddr, uint32_t len))
898 {
899 hal_rpmsg_status_t rpmsgStatus = kStatus_HAL_RpmsgSuccess;
900 hal_imu_handle_t *imuHandle;
901 uint8_t *wlan_tx_buf;
902
903 assert((uint8_t)kIMU_LinkMax > imuLink);
904 assert(NULL != txBuf);
905 assert(0U != length);
906 imuHandle = &imuHandleCh[imuLink];
907
908 if (imuHandle->imuMsgBufIdx > IMU_PAYLOAD_SIZE - 1U)
909 {
910 return kStatus_HAL_RpmsgError;
911 }
912
913 wlan_tx_buf = HAL_ImuGetWlanTxBuf(imuHandle);
914
915 if (NULL == wlan_tx_buf)
916 {
917 return kStatus_HAL_RpmsgError;
918 }
919
920 // To be DMAed
921 cb(wlan_tx_buf, txBuf, length);
922
923 imuHandle->imuMsgBuf[imuHandle->imuMsgBufIdx] = (uint32_t)wlan_tx_buf;
924 imuHandle->imuMsgBufIdx++;
925
926 return rpmsgStatus;
927 }
928
HAL_ImuSendMultiTxData(uint8_t imuLink)929 hal_rpmsg_status_t HAL_ImuSendMultiTxData(uint8_t imuLink)
930 {
931 hal_rpmsg_status_t rpmsgStatus = kStatus_HAL_RpmsgSuccess;
932 hal_imu_handle_t *imuHandle;
933 OSA_SR_ALLOC();
934
935 assert((uint8_t)kIMU_LinkMax > imuLink);
936 imuHandle = &imuHandleCh[imuLink];
937
938 if (kStatus_HAL_RpmsgError == HAL_ImuLinkIsUp(imuHandle->imuLink))
939 {
940 return kStatus_HAL_RpmsgError;
941 }
942
943 OSA_ENTER_CRITICAL();
944 if (kStatus_HAL_RpmsgSuccess == HAL_ImuSendMsgBlocking(imuHandle, (uint8_t)IMU_MSG_MULTI_TX_DATA, 0U, NULL, 0U))
945 {
946 seq_num++;
947 imuHandle->imuMsgBufIdx = 0;
948 }
949 else
950 {
951 rpmsgStatus = kStatus_HAL_RpmsgError;
952 }
953 OSA_EXIT_CRITICAL();
954
955 return rpmsgStatus;
956 }
957
HAL_ImuSendSyncAck(hal_imu_handle_t * imuHandle)958 static hal_rpmsg_status_t HAL_ImuSendSyncAck(hal_imu_handle_t *imuHandle)
959 {
960 hal_rpmsg_status_t rpmsgStatus = kStatus_HAL_RpmsgSuccess;
961 OSA_SR_ALLOC();
962 assert(NULL != imuHandle);
963
964 OSA_ENTER_CRITICAL();
965 if (kStatus_HAL_RpmsgSuccess ==
966 HAL_ImuSendMsgBlocking(imuHandle, (uint8_t)IMU_MSG_CONTROL, (uint8_t)IMU_MSG_CONTROL_SYNC_ACK, NULL, 0U))
967 {
968 seq_num++;
969 }
970 else
971 {
972 rpmsgStatus = kStatus_HAL_RpmsgError;
973 }
974 OSA_EXIT_CRITICAL();
975
976 return rpmsgStatus;
977 }
978
HAL_ImuSendUnlock(hal_imu_handle_t * imuHandle)979 static hal_rpmsg_status_t HAL_ImuSendUnlock(hal_imu_handle_t *imuHandle)
980 {
981 hal_rpmsg_status_t rpmsgStatus = kStatus_HAL_RpmsgSuccess;
982 OSA_SR_ALLOC();
983 assert(NULL != imuHandle);
984
985 if (kStatus_HAL_RpmsgError == HAL_ImuLinkIsUp(imuHandle->imuLink))
986 {
987 return kStatus_HAL_RpmsgError;
988 }
989
990 OSA_ENTER_CRITICAL();
991 if (kStatus_HAL_RpmsgSuccess ==
992 HAL_ImuSendMsgBlocking(imuHandle, (uint8_t)IMU_MSG_CONTROL, (uint8_t)IMU_MSG_CONTROL_ACK_FOR_UNLOCK, NULL, 0U))
993 {
994 seq_num++;
995 }
996 else
997 {
998 rpmsgStatus = kStatus_HAL_RpmsgError;
999 }
1000 OSA_EXIT_CRITICAL();
1001
1002 return rpmsgStatus;
1003 }
1004
HAL_ImuReturnAllTxBuf(imu_link_t link)1005 hal_rpmsg_status_t HAL_ImuReturnAllTxBuf(imu_link_t link)
1006 {
1007 hal_imu_handle_t *imuHandle;
1008 hal_rpmsg_status_t rpmsgStatus = kStatus_HAL_RpmsgSuccess;
1009 uint8_t txBufCnt;
1010 uint8_t *wlan_tx_buf;
1011 OSA_SR_ALLOC();
1012
1013 assert(kIMU_LinkMax > link);
1014 imuHandle = &imuHandleCh[link];
1015
1016 txBufCnt = 0;
1017 while (TRUE)
1018 {
1019 wlan_tx_buf = HAL_ImuGetWlanTxBuf(imuHandle);
1020 if (NULL == wlan_tx_buf) /*! all Tx buffers are consumed */
1021 {
1022 break;
1023 }
1024
1025 imuHandle->imuMsgBuf[txBufCnt] = (uint32_t)wlan_tx_buf;
1026 txBufCnt++;
1027
1028 if (IMU_PAYLOAD_SIZE == txBufCnt)
1029 {
1030 OSA_ENTER_CRITICAL();
1031 if (kStatus_HAL_RpmsgSuccess !=
1032 HAL_ImuSendMsgBlocking(imuHandle, (uint8_t)IMU_MSG_CONTROL, (uint8_t)IMU_MSG_CONTROL_TX_BUF_ADDR,
1033 (uint8_t *)&imuHandle->imuMsgBuf[0], (uint32_t)IMU_PAYLOAD_SIZE))
1034 {
1035 OSA_EXIT_CRITICAL();
1036 return kStatus_HAL_RpmsgError;
1037 }
1038 else
1039 {
1040 seq_num++;
1041 }
1042 txBufCnt = 0;
1043 OSA_EXIT_CRITICAL();
1044 }
1045 }
1046
1047 if (txBufCnt != 0U)
1048 {
1049 OSA_ENTER_CRITICAL();
1050 if (kStatus_HAL_RpmsgSuccess != HAL_ImuSendMsgBlocking(imuHandle, (uint8_t)IMU_MSG_CONTROL,
1051 (uint8_t)IMU_MSG_CONTROL_TX_BUF_ADDR,
1052 (uint8_t *)&imuHandle->imuMsgBuf[0], txBufCnt))
1053 {
1054 OSA_EXIT_CRITICAL();
1055 return kStatus_HAL_RpmsgError;
1056 }
1057 else
1058 {
1059 seq_num++;
1060 }
1061 OSA_EXIT_CRITICAL();
1062 }
1063
1064 return rpmsgStatus;
1065 }
1066
HAL_ImuSendShutdown(hal_imu_handle_t * imuHandle)1067 static hal_rpmsg_status_t HAL_ImuSendShutdown(hal_imu_handle_t *imuHandle)
1068 {
1069 hal_rpmsg_status_t rpmsgStatus = kStatus_HAL_RpmsgSuccess;
1070 OSA_SR_ALLOC();
1071 assert(NULL != imuHandle);
1072
1073 if (kStatus_HAL_RpmsgError == HAL_ImuLinkIsUp(imuHandle->imuLink))
1074 {
1075 return kStatus_HAL_RpmsgError;
1076 }
1077
1078 OSA_ENTER_CRITICAL();
1079 if (kStatus_HAL_RpmsgSuccess ==
1080 HAL_ImuSendMsgBlocking(imuHandle, (uint8_t)IMU_MSG_CONTROL, (uint8_t)IMU_MSG_CONTROL_SHUTDOWN, NULL, 0U))
1081 {
1082 seq_num++;
1083 }
1084 else
1085 {
1086 rpmsgStatus = kStatus_HAL_RpmsgError;
1087 }
1088 OSA_EXIT_CRITICAL();
1089
1090 return rpmsgStatus;
1091 }
1092
HAL_ImuCtrlHandler(hal_imu_handle_t * imuHandle,IMU_Msg_t * data,uint32_t len)1093 static hal_rpmsg_status_t HAL_ImuCtrlHandler(hal_imu_handle_t *imuHandle, IMU_Msg_t *data, uint32_t len)
1094 {
1095 imu_ctrl_msg_subtype_t imuControlType;
1096 IMU_Msg_t *pImuMsg = data;
1097 hal_rpmsg_status_t rpmsgStatus = kStatus_HAL_RpmsgSuccess;
1098 hal_rpmsg_state_t *rpmsgHandle;
1099 OSA_SR_ALLOC();
1100 LIST_ELEM_st *cur;
1101 uint8_t eptQuiryRspAck;
1102
1103 assert(NULL != imuHandle);
1104 imuControlType = (imu_ctrl_msg_subtype_t)pImuMsg->Hdr.sub_type;
1105 OSA_ENTER_CRITICAL();
1106
1107 switch (imuControlType)
1108 {
1109 case IMU_MSG_CONTROL_ACK_FOR_UNLOCK:
1110 IMU_UNLOCK_TX_FIFO(imuHandle->imuLink);
1111 break;
1112 case IMU_MSG_CONTROL_SYNC:
1113 (void)HAL_ImuSendSyncAck(imuHandle);
1114 if ((uint8_t)kIMU_LinkCpu2Cpu3 == imuHandle->imuLink)
1115 {
1116 imuHandle->imuSyncState = (uint8_t)IMU_INITIALIZED;
1117 }
1118 (void)HAL_ImuSendSyncAck(imuHandle);
1119 imuHandle->imuSyncState = (uint8_t)IMU_INITIALIZED;
1120 break;
1121 case IMU_MSG_CONTROL_SYNC_ACK:
1122 imuHandle->imuSyncState = (uint8_t)IMU_INITIALIZED;
1123 break;
1124 case IMU_MSG_CONTROL_CMD_BUF_ADDR:
1125 imuHandle->cmd_buffer = (uint32_t *)pImuMsg->PayloadPtr[0];
1126 imuHandle->cmd_buffer_available = TRUE;
1127 if ((uint8_t)IMU_INITIALIZED != imuHandle->imuSyncState)
1128 {
1129 imuHandle->imuSyncState = (uint8_t)IMU_INITIALIZED;
1130 }
1131 break;
1132 case IMU_MSG_CONTROL_TX_BUF_ADDR:
1133 for (uint8_t i = 0; i < pImuMsg->Hdr.length; i++)
1134 {
1135 (void)HAL_ImuPutWlanTxBuf(imuHandle, (uint8_t *)pImuMsg->PayloadPtr[i]);
1136 }
1137 break;
1138 case IMU_MSG_CONTROL_ERROR:
1139 break;
1140 case IMU_MSG_CONTROL_SHUTDOWN:
1141 imuHandle->imuSyncState = (uint8_t)IMU_UNINITIALIZED;
1142 IMU_ClearPendingInterrupts((imu_link_t)imuHandle->imuLink, IMU_MSG_FIFO_CNTL_MSG_RDY_INT_CLR_MASK);
1143 IMU_ClearPendingInterrupts((imu_link_t)imuHandle->imuLink, IMU_MSG_FIFO_CNTL_SP_AV_INT_CLR_MASK);
1144 (void)os_InterruptMaskClear(IMULINKID_TO_IRQID((imu_link_t)imuHandle->imuLink));
1145 IMU_Deinit((imu_link_t)imuHandle->imuLink);
1146 *IMU_MSG_CUR_MAGIC_P(imuHandle->imuLink) = 0;
1147 imuHandle->wlanTxqCtl.writeIndex = 0;
1148 imuHandle->wlanTxqCtl.readIndex = 0;
1149 break;
1150 case IMU_MSG_CONTROL_RPMSG_EPT_QUIRY:
1151 {
1152 hal_rpmsg_state_t *rpmsgHandle = HAL_RpmsgGetEndpointFromAddr(imuHandle, pImuMsg->PayloadPtr[0]);
1153 if (rpmsgHandle != NULL)
1154 {
1155 /* The remote CPU is sending an endpoint query so it implies the rpmsg link is ready */
1156 rpmsgHandle->eptLinkIsReady = TRUE;
1157 /* Confirm the local endpoint is ready too */
1158 rpmsgStatus = HAL_ImuSendRpmsgEptQuiryRsp(imuHandle, pImuMsg->PayloadPtr[0], TRUE);
1159 /* Make sure to unblock the task calling HAL_RpmsgInit */
1160 #ifdef __ZEPHYR__
1161 k_event_set(&rpmsgQFlagsRef, RPMSG_EVENT_ENDPOINT_QUERY_RSP << imuHandle->imuLink);
1162 #else
1163 (void)OSA_EventSet((osa_event_handle_t)rpmsgQFlagsRef,
1164 RPMSG_EVENT_ENDPOINT_QUERY_RSP << imuHandle->imuLink);
1165 #endif
1166 }
1167 else
1168 {
1169 /* Local endpoint doesn't exist yet, the remote CPU needs to wait until the local CPU initializes
1170 * the targeted endpoint, a new query will be sent then to update the link status on both sides */
1171 rpmsgStatus = HAL_ImuSendRpmsgEptQuiryRsp(imuHandle, pImuMsg->PayloadPtr[0], FALSE);
1172 }
1173 }
1174 break;
1175 case IMU_MSG_CONTROL_RPMSG_EPT_QUIRY_RSP:
1176 eptQuiryRspAck = 0;
1177 list_for_each(cur, &imuHandle->eptList)
1178 {
1179 rpmsgHandle = (hal_rpmsg_state_t *)cur;
1180 if (rpmsgHandle->remote_addr == pImuMsg->PayloadPtr[0])
1181 {
1182 if (pImuMsg->PayloadPtr[1] != 0U)
1183 {
1184 eptQuiryRspAck = 1;
1185 rpmsgHandle->eptLinkIsReady = TRUE;
1186 }
1187 else
1188 {
1189 rpmsgHandle->eptLinkIsReady = FALSE;
1190 }
1191 }
1192 }
1193
1194 if (eptQuiryRspAck != 0U)
1195 {
1196 /* Make sure to unblock the task calling HAL_RpmsgInit */
1197 #ifdef __ZEPHYR__
1198 k_event_set(&rpmsgQFlagsRef, RPMSG_EVENT_ENDPOINT_QUERY_RSP << imuHandle->imuLink);
1199 #else
1200 (void)OSA_EventSet((osa_event_handle_t)rpmsgQFlagsRef,
1201 RPMSG_EVENT_ENDPOINT_QUERY_RSP << imuHandle->imuLink);
1202 #endif
1203 }
1204 break;
1205 case IMU_MSG_CONTROL_RPMSG_BUF_FREE:
1206 (void)HAL_RpmsgPutTxBuf(imuHandle, (uint8_t *)pImuMsg->PayloadPtr[0]);
1207 break;
1208 default:
1209 // Do nothing for the commands without header expansion.
1210 break;
1211 }
1212
1213 OSA_EXIT_CRITICAL();
1214 return rpmsgStatus;
1215 }
1216
HAL_ImuReceive(uint8_t imuLink)1217 hal_rpmsg_status_t HAL_ImuReceive(uint8_t imuLink)
1218 {
1219 IMU_Msg_t *pMsg = NULL, localImuMsg;
1220 IMU_Msg_t localImuMsgRx;
1221
1222 hal_imu_handle_t *imuHandle = NULL;
1223 imu_msg_type_t msg_type = IMU_MSG_MAX;
1224 bool isUnlockMsgReqd = FALSE;
1225 hal_rpmsg_state_t *ept;
1226 struct rpmsg_std_msg *rpmsg_msg;
1227 hal_rpmsg_status_t rpmsgStatus = kStatus_HAL_RpmsgSuccess;
1228
1229 assert((uint8_t)kIMU_LinkMax > imuLink);
1230 imuHandle = &imuHandleCh[imuLink];
1231
1232 while (TRUE)
1233 {
1234 if (IMU_RX_FIFO_EMPTY((imu_link_t)imuHandle->imuLink))
1235 {
1236 IMU_ClearPendingInterrupts((imu_link_t)imuHandle->imuLink, IMU_MSG_FIFO_CNTL_MSG_RDY_INT_CLR_MASK);
1237 os_ClearPendingISR(IMULINKID_TO_IRQID((imu_link_t)imuHandle->imuLink));
1238 #ifndef CPU2
1239 *IMU_SLEEP_FLAG_ADDR(imuHandle->imuLink) |= (uint32_t)(1 << 0U);
1240 #endif
1241 break;
1242 }
1243 else
1244 {
1245 #ifndef CPU2
1246 *IMU_SLEEP_FLAG_ADDR(imuHandle->imuLink) &= (uint32_t)(~(1 << 0U));
1247 #endif
1248
1249 /* Message buffer pMsg should be consumed (or copied for later
1250 * processing) in handler before call for next READ_ICC_MESSAGE
1251 * comes here again.
1252 * Otherwise other CPU may use same pMsg for next write,
1253 * when FIFO is almost full
1254 */
1255 pMsg = (IMU_Msg_t *)IMU_RD_MSG(imuHandle->imuLink);
1256 if ((pMsg != NULL) && (IMU_RX_FIFO_LOCKED(imuHandle->imuLink)))
1257 {
1258 isUnlockMsgReqd = TRUE;
1259 }
1260 }
1261
1262 /* release CPU access here because message processing may take time */
1263 if (pMsg != NULL)
1264 {
1265 (void)memcpy((uint8_t *)&localImuMsg, (uint8_t *)pMsg, sizeof(IMU_Msg_t));
1266 pMsg = &localImuMsg;
1267 msg_type = (imu_msg_type_t)pMsg->Hdr.type;
1268
1269 switch (msg_type)
1270 {
1271 case IMU_MSG_CONTROL:
1272 rpmsgStatus = HAL_ImuCtrlHandler(imuHandle, pMsg, pMsg->Hdr.length);
1273 if (imuHandle->imuHandler[IMU_MSG_CONTROL] != NULL)
1274 {
1275 rpmsgStatus = imuHandle->imuHandler[IMU_MSG_CONTROL]((IMU_Msg_t *)pMsg, pMsg->Hdr.length);
1276 }
1277 break;
1278 case IMU_MSG_COMMAND_RESPONSE:
1279 if (imuHandle->imuHandler[IMU_MSG_COMMAND_RESPONSE] != NULL)
1280 {
1281 rpmsgStatus =
1282 imuHandle->imuHandler[IMU_MSG_COMMAND_RESPONSE]((IMU_Msg_t *)pMsg, pMsg->Hdr.length);
1283 }
1284 assert(kStatus_HAL_RpmsgSuccess == rpmsgStatus);
1285 rpmsgStatus = HAL_ImuSendCommandRspAck(imuHandle, (uint8_t *)&pMsg->PayloadPtr[0], 1);
1286 imuHandle->cmd_buffer_available = TRUE;
1287 break;
1288
1289 case IMU_MSG_EVENT:
1290 if (imuHandle->imuHandler[IMU_MSG_EVENT] != NULL)
1291 {
1292 rpmsgStatus = imuHandle->imuHandler[IMU_MSG_EVENT]((IMU_Msg_t *)pMsg, pMsg->Hdr.length);
1293 }
1294 assert(kStatus_HAL_RpmsgSuccess == rpmsgStatus);
1295 rpmsgStatus = HAL_ImuSendEventAck(imuHandle, (uint8_t *)&pMsg->PayloadPtr[0], 1);
1296 break;
1297
1298 case IMU_MSG_RX_DATA:
1299 case IMU_MSG_MULTI_RX_DATA:
1300 (void)memcpy((uint8_t *)&localImuMsgRx, (uint8_t *)pMsg, sizeof(IMU_Msg_t));
1301 if (imuHandle->imuHandler[IMU_MSG_RX_DATA] != NULL)
1302 {
1303 rpmsgStatus = imuHandle->imuHandler[IMU_MSG_RX_DATA]((IMU_Msg_t *)pMsg, pMsg->Hdr.length);
1304 }
1305 pMsg = &localImuMsgRx;
1306 rpmsgStatus = HAL_ImuFreeRxBuf(imuHandle, (uint8_t *)&pMsg->PayloadPtr[0], pMsg->Hdr.length);
1307 break;
1308 case IMU_MSG_RPMSG:
1309 rpmsg_msg = (struct rpmsg_std_msg *)&pMsg->PayloadPtr[0];
1310 ept = (hal_rpmsg_state_t *)HAL_RpmsgGetEndpointFromAddr(imuHandle, rpmsg_msg->hdr.dst);
1311 if (NULL != ept)
1312 {
1313 if (ept->rx.callback != NULL)
1314 {
1315 rpmsgStatus = (hal_rpmsg_status_t)ept->rx.callback(
1316 ept->rx.param, (uint8_t *)rpmsg_msg->data, rpmsg_msg->hdr.len);
1317 }
1318 }
1319 if ((hal_rpmsg_return_status_t)rpmsgStatus == kStatus_HAL_RL_RELEASE)
1320 {
1321 rpmsgStatus = HAL_ImuSendRpmsgFreeBuf(imuHandle, (uint8_t *)&rpmsg_msg->data);
1322 }
1323 break;
1324
1325 default:
1326 // Do nothing for the commands without expansion.
1327 break;
1328 }
1329
1330 assert(kStatus_HAL_RpmsgSuccess == rpmsgStatus);
1331 }
1332 }
1333
1334 if (isUnlockMsgReqd)
1335 {
1336 (void)HAL_ImuSendUnlock(imuHandle);
1337 }
1338
1339 (void)os_InterruptMaskSet(IMULINKID_TO_IRQID((imu_link_t)imuHandle->imuLink));
1340 return (hal_rpmsg_status_t)rpmsgStatus;
1341 }
1342
1343 #if defined(CPU2)
HAL_ImuMain(void * argv)1344 static void HAL_ImuMain(void *argv)
1345 {
1346 uint32_t Events = 0;
1347 uint32_t imuLinkId;
1348
1349 while (TRUE)
1350 {
1351 #if (defined(USE_RTOS) && (USE_RTOS > 0U))
1352 (void)HAL_ImuPutTaskLock();
1353 #endif
1354 (void)OSA_EventWait((osa_event_handle_t)ImuQFlagsRef, IMU_EVENT_TRIGGERS, 0, osaWaitForever_c, &Events);
1355 if (Events == 0U)
1356 {
1357 if (gUseRtos_c == 0U)
1358 {
1359 break;
1360 }
1361 else
1362 {
1363 continue;
1364 }
1365 }
1366 #if (defined(USE_RTOS) && (USE_RTOS > 0U))
1367 (void)HAL_ImuGetTaskLock();
1368 #endif
1369 /*! Check for all IMU links event/ISR has occured
1370 * Only MSG ready events considered
1371 */
1372 for (imuLinkId = 0; imuLinkId < (uint32_t)kIMU_LinkMax; imuLinkId++)
1373 {
1374 if ((Events & (1U << imuLinkId)) != 0U)
1375 {
1376 (void)HAL_ImuReceive((uint8_t)imuLinkId);
1377 }
1378 }
1379 if (gUseRtos_c == 0U)
1380 {
1381 break;
1382 }
1383 }
1384 }
1385 #else
1386
HAL_ImuMainCpu13(void * argv,void * argv2,void * argv3)1387 static void HAL_ImuMainCpu13(void *argv
1388 #ifdef __ZEPHYR__
1389 ,
1390 void *argv2,
1391 void *argv3
1392 #endif
1393 )
1394 {
1395 uint32_t Events = 0;
1396
1397 while (TRUE)
1398 {
1399 #if (defined(USE_RTOS) && (USE_RTOS > 0U))
1400 (void)HAL_ImuPutTaskLock();
1401 #endif
1402
1403 #ifdef __ZEPHYR__
1404 Events = k_event_wait(&ImuQ13FlagsRef, IMU_EVENT_TRIGGERS, 0, K_FOREVER);
1405 k_event_clear(&ImuQ13FlagsRef, (1U << kIMU_LinkCpu1Cpu3));
1406 #else
1407 (void)OSA_EventWait((osa_event_handle_t)ImuQ13FlagsRef, IMU_EVENT_TRIGGERS, 0, osaWaitForever_c, &Events);
1408 #endif
1409
1410 if (Events == 0U)
1411 {
1412 if (gUseRtos_c == 0U)
1413 {
1414 break;
1415 }
1416 else
1417 {
1418 continue;
1419 }
1420 }
1421 #if (defined(USE_RTOS) && (USE_RTOS > 0U))
1422 (void)HAL_ImuGetTaskLock();
1423 #endif
1424 /*! Check for CPU1 to CPU3 IMU links event/ISR has occured
1425 * Only MSG ready events considered
1426 */
1427 (void)HAL_ImuReceive(kIMU_LinkCpu1Cpu3);
1428
1429 if (gUseRtos_c == 0U)
1430 {
1431 break;
1432 }
1433 }
1434 }
1435
HAL_ImuMainCpu23(void * argv,void * argv2,void * argv3)1436 static void HAL_ImuMainCpu23(void *argv
1437 #ifdef __ZEPHYR__
1438 ,
1439 void *argv2,
1440 void *argv3
1441 #endif
1442 )
1443 {
1444 uint32_t Events = 0;
1445
1446 while (TRUE)
1447 {
1448 #if 0
1449 HAL_ImuPutTaskLock();
1450 #endif
1451
1452 #ifdef __ZEPHYR__
1453 Events = k_event_wait(&ImuQ23FlagsRef, IMU_EVENT_TRIGGERS, 0, K_FOREVER);
1454 k_event_clear(&ImuQ23FlagsRef, (1U << kIMU_LinkCpu2Cpu3));
1455 #else
1456 (void)OSA_EventWait((osa_event_handle_t)ImuQ23FlagsRef, IMU_EVENT_TRIGGERS, 0, osaWaitForever_c, &Events);
1457 #endif
1458
1459 if (Events == 0U)
1460 {
1461 if (gUseRtos_c == 0U)
1462 {
1463 break;
1464 }
1465 else
1466 {
1467 continue;
1468 }
1469 }
1470 #if 0
1471 HAL_ImuGetTaskLock();
1472 #endif
1473 /*! Check for CPU2 to CPU3 IMU links event/ISR has occured
1474 * Only MSG ready events considered
1475 */
1476
1477 (void)HAL_ImuReceive(kIMU_LinkCpu2Cpu3);
1478
1479 if (gUseRtos_c == 0U)
1480 {
1481 break;
1482 }
1483 }
1484 }
1485 #endif
1486
HAL_ImuTaskInit(uint8_t link)1487 static void HAL_ImuTaskInit(uint8_t link)
1488 {
1489 #if defined(CPU2)
1490 (void)link;
1491
1492 if (((imu_init_flag & ((1U << (uint8_t)kIMU_LinkMax) - 1U)) == 0U) && imu_task_flag == 0U)
1493 {
1494 (void)OSA_TaskCreate((osa_task_handle_t)ImuTaskHandle, OSA_TASK(HAL_ImuMain), NULL);
1495 (void)OSA_EventCreate((osa_event_handle_t)ImuQFlagsRef, 1U);
1496 imu_task_flag = 1;
1497 }
1498 #else
1499 if (link == kIMU_LinkCpu1Cpu3 && (imu_task_flag & (1U << link)) == 0)
1500 {
1501 #ifdef __ZEPHYR__
1502 ImuTaskCpu13 = k_thread_create(&ImuTaskHandleCpu13, ImuTaskStackCpu13, K_THREAD_STACK_SIZEOF(ImuTaskStackCpu13),
1503 HAL_ImuMainCpu13, NULL, NULL, NULL, IMU_TASK_PRIORITY, 0, K_NO_WAIT);
1504 k_thread_name_set(ImuTaskCpu13, "HAL_ImuMainCpu13");
1505 #else
1506 (void)OSA_TaskCreate((osa_task_handle_t)ImuTaskHandleCpu13, OSA_TASK(HAL_ImuMainCpu13), NULL);
1507 (void)OSA_EventCreate((osa_event_handle_t)ImuQ13FlagsRef, 1U);
1508 #endif
1509 imu_task_flag |= (1U << link);
1510 }
1511 else if (link == kIMU_LinkCpu2Cpu3 && (imu_task_flag & (1U << link)) == 0)
1512 {
1513 #ifdef __ZEPHYR__
1514 ImuTaskCpu23 = k_thread_create(&ImuTaskHandleCpu23, ImuTaskStackCpu23, K_THREAD_STACK_SIZEOF(ImuTaskStackCpu23),
1515 HAL_ImuMainCpu23, NULL, NULL, NULL, IMU_TASK_PRIORITY, 0, K_NO_WAIT);
1516 k_thread_name_set(ImuTaskCpu23, "HAL_ImuMainCpu23");
1517 #else
1518 (void)OSA_TaskCreate((osa_task_handle_t)ImuTaskHandleCpu23, OSA_TASK(HAL_ImuMainCpu23), NULL);
1519 (void)OSA_EventCreate((osa_event_handle_t)ImuQ23FlagsRef, 1U);
1520 #endif
1521 imu_task_flag |= (1U << link);
1522 }
1523 else
1524 {
1525 ; /* No necessary actions. */
1526 }
1527 #endif
1528 }
1529
HAL_ImuTaskDeinit(uint8_t link)1530 static void HAL_ImuTaskDeinit(uint8_t link)
1531 {
1532 #if defined(CPU2)
1533 (void)link;
1534
1535 if (imu_init_flag == 0U && imu_task_flag != 0U)
1536 {
1537 (void)OSA_EventDestroy((osa_event_handle_t)ImuQFlagsRef);
1538 (void)OSA_TaskDestroy(ImuTaskHandle);
1539 imu_task_flag = 0;
1540 }
1541 #else
1542 if (link == kIMU_LinkCpu1Cpu3 && (imu_task_flag & (1U << link)) != 0)
1543 {
1544 #ifndef __ZEPHYR__
1545 (void)OSA_EventDestroy((osa_event_handle_t)ImuQ13FlagsRef);
1546 (void)OSA_TaskDestroy(ImuTaskHandleCpu13);
1547 imu_task_flag &= ~(1U << link);
1548 #endif
1549 }
1550 else if (link == kIMU_LinkCpu2Cpu3 && (imu_task_flag & (1U << link)) != 0)
1551 {
1552 #ifndef __ZEPHYR__
1553 (void)OSA_EventDestroy((osa_event_handle_t)ImuQ23FlagsRef);
1554 (void)OSA_TaskDestroy(ImuTaskHandleCpu23);
1555 imu_task_flag &= ~(1U << link);
1556 #endif
1557 }
1558 else
1559 {
1560 ; /* No necessary actions. */
1561 }
1562 #endif
1563 }
1564
HAL_ImuInit(imu_link_t link)1565 hal_rpmsg_status_t HAL_ImuInit(imu_link_t link)
1566 {
1567 hal_imu_handle_t *imuHandle;
1568 hal_rpmsg_status_t state = kStatus_HAL_RpmsgSuccess;
1569 uint8_t i;
1570 OSA_SR_ALLOC();
1571
1572 assert(kIMU_LinkMax > link);
1573 imuHandle = &imuHandleCh[link];
1574 imuHandle->imuLink = (uint8_t)link;
1575 OSA_ENTER_CRITICAL();
1576
1577 #if defined(IMU_GDMA_ENABLE) && (IMU_GDMA_ENABLE == 1)
1578 if (0U == imu_init_flag)
1579 {
1580 HAL_InitGdma();
1581 }
1582 #endif
1583
1584 /*! IMU and its interrupt are initialized once for each IMU link */
1585 if ((imu_init_flag & (1U << imuHandle->imuLink)) == 0U)
1586 {
1587 HAL_ImuTaskInit(imuHandle->imuLink);
1588
1589 if (IMU_Init(link) != (int)kStatus_HAL_RpmsgSuccess)
1590 {
1591 return kStatus_HAL_RpmsgError;
1592 }
1593 IMU_ClearPendingInterrupts(link, IMU_MSG_FIFO_CNTL_MSG_RDY_INT_CLR_MASK);
1594 os_ClearPendingISR(IMULINKID_TO_IRQID(link));
1595 /* Interrupt must be maskable by FreeRTOS critical section */
1596 NVIC_SetPriority(IMULINKID_TO_IRQID(link), IMU_ISR_PRIORITY);
1597 (void)os_InterruptMaskSet(IMULINKID_TO_IRQID(link));
1598 #if defined(CPU2)
1599 if (kIMU_LinkCpu2Cpu3 == link)
1600 {
1601 for (i = 0; i < RPMSG_TXQ23_BUFSIZE; i++)
1602 {
1603 (void)HAL_RpmsgPutTxBuf(imuHandle, (uint8_t *)rpmsgTxBuf23[i]);
1604 }
1605 }
1606 #else
1607 imuHandle->wlanTxqCtl.writeIndex = 0;
1608 imuHandle->wlanTxqCtl.readIndex = 0;
1609 imuHandle->imuMsgBufIdx = 0;
1610 imuHandle->rpmsgTxqCtl.writeIndex = 0;
1611 imuHandle->rpmsgTxqCtl.readIndex = 0;
1612 if (kIMU_LinkCpu1Cpu3 == link)
1613 {
1614 for (i = 0; i < RPMSG_TXQ13_BUFSIZE; i++)
1615 {
1616 (void)HAL_RpmsgPutTxBuf(imuHandle, (uint8_t *)rpmsgTxBuf13[i]);
1617 }
1618 }
1619 else if (kIMU_LinkCpu2Cpu3 == link)
1620 {
1621 for (i = 0; i < RPMSG_TXQ23_BUFSIZE; i++)
1622 {
1623 (void)HAL_RpmsgPutTxBuf(imuHandle, (uint8_t *)rpmsgTxBuf23[i]);
1624 }
1625 }
1626 else
1627 {
1628 ; /* No necessary actions. */
1629 }
1630 #endif
1631 LIST_init(&imuHandle->eptList);
1632 imu_init_flag |= (1U << imuHandle->imuLink);
1633 }
1634
1635 /*! Could be moved out from rpmsg_init() */
1636 if (imu_init_flag == ((1U << kIMU_LinkMax) - 1U)) /*! All IMU links are initalized */
1637 {
1638 HAL_ImuSetCpuReadyFlag(1U /*! Set CPU1 state */);
1639 }
1640
1641 if ((uint8_t)IMU_UNINITIALIZED == imuHandle->imuSyncState)
1642 {
1643 state = HAL_ImuSendSync(imuHandle);
1644 }
1645
1646 OSA_EXIT_CRITICAL();
1647 (void)state;
1648 return kStatus_HAL_RpmsgSuccess;
1649 }
1650
HAL_ImuDeinit(imu_link_t link,uint32_t flag)1651 hal_rpmsg_status_t HAL_ImuDeinit(imu_link_t link, uint32_t flag)
1652 {
1653 hal_imu_handle_t *imuHandle;
1654 hal_rpmsg_status_t state = kStatus_HAL_RpmsgSuccess;
1655 OSA_SR_ALLOC();
1656
1657 assert(kIMU_LinkMax > link);
1658 imuHandle = &imuHandleCh[link];
1659 OSA_ENTER_CRITICAL();
1660
1661 if ((flag & (1U << 0U)) == 0U)
1662 {
1663 (void)HAL_ImuReturnAllTxBuf(link);
1664 state = HAL_ImuSendShutdown(imuHandle);
1665 if (kStatus_HAL_RpmsgError == state)
1666 {
1667 OSA_EXIT_CRITICAL();
1668 return kStatus_HAL_RpmsgError;
1669 }
1670 }
1671
1672 IMU_ClearPendingInterrupts((imu_link_t)imuHandle->imuLink, IMU_MSG_FIFO_CNTL_MSG_RDY_INT_CLR_MASK);
1673 IMU_ClearPendingInterrupts((imu_link_t)imuHandle->imuLink, IMU_MSG_FIFO_CNTL_SP_AV_INT_CLR_MASK);
1674 (void)os_InterruptMaskClear(IMULINKID_TO_IRQID((imu_link_t)imuHandle->imuLink));
1675 IMU_Deinit((imu_link_t)imuHandle->imuLink);
1676 imuHandle->imuSyncState = (uint8_t)IMU_UNINITIALIZED;
1677 *IMU_MSG_CUR_MAGIC_P(imuHandle->imuLink) = 0;
1678 imu_init_flag &= ~(1U << imuHandle->imuLink);
1679 imuHandle->wlanTxqCtl.writeIndex = 0;
1680 imuHandle->wlanTxqCtl.readIndex = 0;
1681 imuHandle->imuMsgBufIdx = 0;
1682 imuHandle->cmd_buffer = NULL;
1683 imuHandle->cmd_buffer_available = 0;
1684 imuHandle->cmd_response_buffer_available = 0;
1685
1686 if ((flag & (1U << 0U)) == 0U)
1687 {
1688 while (*IMU_MSG_PEER_MAGIC_P((imu_link_t)imuHandle->imuLink) != 0)
1689 {
1690 }
1691 }
1692
1693 if ((flag & (1U << 1U)) == 0U)
1694 {
1695 HAL_ImuTaskDeinit(imuHandle->imuLink);
1696 }
1697
1698 OSA_EXIT_CRITICAL();
1699 return kStatus_HAL_RpmsgSuccess;
1700 }
1701
HAL_RpmsgInit(hal_rpmsg_handle_t handle,hal_rpmsg_config_t * config)1702 hal_rpmsg_status_t HAL_RpmsgInit(hal_rpmsg_handle_t handle, hal_rpmsg_config_t *config)
1703 {
1704 hal_rpmsg_status_t state = kStatus_HAL_RpmsgSuccess;
1705 hal_rpmsg_state_t *rpmsgHandle;
1706 hal_imu_handle_t *imuHandle;
1707 uint32_t Events;
1708 OSA_SR_ALLOC();
1709
1710 assert(HAL_RPMSG_HANDLE_SIZE >= sizeof(hal_rpmsg_state_t));
1711 assert(NULL != handle);
1712 assert(NULL != config);
1713 assert((uint8_t)kIMU_LinkMax > config->imuLink);
1714 rpmsgHandle = (hal_rpmsg_state_t *)handle;
1715
1716 OSA_ENTER_CRITICAL();
1717
1718 if (rpmsg_init_flag == 0U)
1719 {
1720 #ifdef __ZEPHYR__
1721 k_event_init(&rpmsgQFlagsRef);
1722 #else
1723 (void)OSA_EventCreate((osa_event_handle_t)rpmsgQFlagsRef, 1U);
1724 #endif
1725 rpmsg_init_flag = 1U;
1726 }
1727
1728 state = HAL_ImuInit((imu_link_t)config->imuLink);
1729 if (kStatus_HAL_RpmsgError == state)
1730 {
1731 OSA_EXIT_CRITICAL();
1732 return kStatus_HAL_RpmsgError;
1733 }
1734
1735 rpmsgHandle->imuLink = config->imuLink;
1736 rpmsgHandle->local_addr = config->local_addr;
1737 rpmsgHandle->remote_addr = config->remote_addr;
1738 rpmsgHandle->rx.callback = config->callback;
1739 rpmsgHandle->rx.param = config->param;
1740 rpmsgHandle->eptLinkIsReady = FALSE;
1741 LIST_elemInit(&rpmsgHandle->eptLink);
1742
1743 if (NULL == HAL_RpmsgCreateEndpoint(rpmsgHandle))
1744 {
1745 OSA_EXIT_CRITICAL();
1746 return kStatus_HAL_RpmsgError;
1747 }
1748
1749 imuHandle = &imuHandleCh[rpmsgHandle->imuLink];
1750
1751 OSA_EXIT_CRITICAL();
1752
1753 while (kStatus_HAL_RpmsgError == HAL_ImuLinkIsUp(imuHandle->imuLink))
1754 {
1755 #if defined(USE_RTOS) && (USE_RTOS == 1)
1756 OSA_TimeDelay(IMU_LINK_WAIT_DELAY_MS);
1757 #else
1758 (void)HAL_ImuReceive(rpmsgHandle->imuLink);
1759 #endif
1760 }
1761
1762 while (FALSE == rpmsgHandle->eptLinkIsReady)
1763 {
1764 OSA_ENTER_CRITICAL();
1765
1766 state = HAL_ImuSendRpmsgEptQuiry(imuHandle, rpmsgHandle->remote_addr);
1767
1768 OSA_EXIT_CRITICAL();
1769
1770 #if defined(USE_RTOS) && (USE_RTOS == 1U)
1771 #ifdef __ZEPHYR__
1772 Events = k_event_wait(&rpmsgQFlagsRef, RPMSG_EVENT_ENDPOINT_QUERY_RSP << imuHandle->imuLink, 0, K_FOREVER);
1773 k_event_clear(&rpmsgQFlagsRef, RPMSG_EVENT_ENDPOINT_QUERY_RSP << imuHandle->imuLink);
1774 #else
1775 (void)OSA_EventWait((osa_event_handle_t)rpmsgQFlagsRef, RPMSG_EVENT_ENDPOINT_QUERY_RSP << imuHandle->imuLink, 0,
1776 osaWaitForever_c, &Events);
1777 #endif
1778 #else
1779 while (TRUE) /* Wait for RPMSG_EVENT_ENDPOINT_QUERY_RSP */
1780 {
1781 (void)HAL_ImuReceive(rpmsgHandle->imuLink);
1782 (void)OSA_EventWait((osa_event_handle_t)rpmsgQFlagsRef,
1783 RPMSG_EVENT_ENDPOINT_QUERY_RSP << imuHandle->imuLink, 0, osaWaitForever_c, &Events);
1784 if (Events != 0U)
1785 {
1786 break;
1787 }
1788 }
1789 #endif
1790 }
1791
1792 return state;
1793 }
1794
HAL_RpmsgDeinit(hal_rpmsg_handle_t handle)1795 hal_rpmsg_status_t HAL_RpmsgDeinit(hal_rpmsg_handle_t handle)
1796 {
1797 hal_rpmsg_state_t *rpmsgHandle;
1798 hal_rpmsg_status_t state = kStatus_HAL_RpmsgSuccess;
1799 OSA_SR_ALLOC();
1800
1801 assert(NULL != handle);
1802 rpmsgHandle = (hal_rpmsg_state_t *)handle;
1803 OSA_ENTER_CRITICAL();
1804 state = HAL_RpmsgDestroyEndpoint(rpmsgHandle);
1805
1806 OSA_EXIT_CRITICAL();
1807
1808 return state;
1809 }
1810
HAL_RpmsgSend(hal_rpmsg_handle_t handle,uint8_t * data,uint32_t length)1811 hal_rpmsg_status_t HAL_RpmsgSend(hal_rpmsg_handle_t handle, uint8_t *data, uint32_t length)
1812 {
1813 hal_rpmsg_status_t state = kStatus_HAL_RpmsgSuccess;
1814 hal_rpmsg_state_t *rpmsgHandle;
1815 hal_imu_handle_t *imuHandle;
1816 hal_rpmsg_status_t rpmsgStatus = kStatus_HAL_RpmsgSuccess;
1817 OSA_SR_ALLOC();
1818 uint8_t *rpmsg_tx_buf;
1819 struct rpmsg_std_msg localRpmsg;
1820
1821 assert(HAL_RPMSG_HANDLE_SIZE >= sizeof(hal_rpmsg_state_t));
1822 assert(NULL != handle);
1823 assert(NULL != data);
1824
1825 rpmsgHandle = (hal_rpmsg_state_t *)handle;
1826 imuHandle = &imuHandleCh[rpmsgHandle->imuLink];
1827
1828 assert(kStatus_HAL_RpmsgSuccess == HAL_ImuLinkIsUp(imuHandle->imuLink));
1829 assert(rpmsgHandle->eptLinkIsReady == TRUE);
1830
1831 if (rpmsgHandle->imuLink == (uint8_t)kIMU_LinkCpu2Cpu3)
1832 {
1833 assert(RPMSG_TXQ23_BUFLENGTH >= length);
1834 }
1835 else
1836 {
1837 assert(RPMSG_TXQ13_BUFLENGTH >= length);
1838 }
1839
1840 rpmsg_tx_buf = HAL_RpmsgAllocTxBuffer(handle, length);
1841
1842 if (NULL == rpmsg_tx_buf)
1843 {
1844 return kStatus_HAL_RpmsgError;
1845 }
1846 else
1847 {
1848 OSA_ENTER_CRITICAL();
1849
1850 // To be DMAed
1851 (void)HAL_IMU_MEMCPY(rpmsg_tx_buf, data, length);
1852 localRpmsg.hdr.src = rpmsgHandle->local_addr;
1853 localRpmsg.hdr.dst = rpmsgHandle->remote_addr;
1854 localRpmsg.hdr.len = (uint16_t)length;
1855 localRpmsg.hdr.flags = 0;
1856 localRpmsg.data = (uint32_t)rpmsg_tx_buf;
1857
1858 if (kStatus_HAL_RpmsgSuccess == HAL_ImuSendMsgBlocking(imuHandle, (uint8_t)IMU_MSG_RPMSG, 0U,
1859 (uint8_t *)&localRpmsg,
1860 (3U + sizeof(struct rpmsg_std_msg)) >> 2U))
1861 {
1862 seq_num++;
1863 }
1864 else
1865 {
1866 (void)HAL_RpmsgPutTxBuf(imuHandle, rpmsg_tx_buf);
1867 rpmsgStatus = kStatus_HAL_RpmsgError;
1868 }
1869
1870 OSA_EXIT_CRITICAL();
1871 }
1872
1873 (void)state;
1874 return rpmsgStatus;
1875 }
1876
HAL_RpmsgNoCopySend(hal_rpmsg_handle_t handle,uint8_t * data,uint32_t length)1877 hal_rpmsg_status_t HAL_RpmsgNoCopySend(hal_rpmsg_handle_t handle, uint8_t *data, uint32_t length)
1878 {
1879 hal_rpmsg_status_t state = kStatus_HAL_RpmsgSuccess;
1880 hal_rpmsg_state_t *rpmsgHandle;
1881 hal_imu_handle_t *imuHandle;
1882 hal_rpmsg_status_t rpmsgStatus = kStatus_HAL_RpmsgSuccess;
1883 OSA_SR_ALLOC();
1884
1885 struct rpmsg_std_msg localRpmsg;
1886
1887 assert(HAL_RPMSG_HANDLE_SIZE >= sizeof(hal_rpmsg_state_t));
1888 assert(NULL != handle);
1889 assert(NULL != data);
1890
1891 rpmsgHandle = (hal_rpmsg_state_t *)handle;
1892 imuHandle = &imuHandleCh[rpmsgHandle->imuLink];
1893
1894 assert(kStatus_HAL_RpmsgSuccess == HAL_ImuLinkIsUp(imuHandle->imuLink));
1895 assert(rpmsgHandle->eptLinkIsReady == TRUE);
1896
1897 OSA_ENTER_CRITICAL();
1898
1899 localRpmsg.hdr.src = rpmsgHandle->local_addr;
1900 localRpmsg.hdr.dst = rpmsgHandle->remote_addr;
1901 localRpmsg.hdr.len = (uint16_t)length;
1902 localRpmsg.hdr.flags = 0;
1903 localRpmsg.data = (uint32_t)data;
1904
1905 if (kStatus_HAL_RpmsgSuccess == HAL_ImuSendMsgBlocking(imuHandle, (uint8_t)IMU_MSG_RPMSG, 0U,
1906 (uint8_t *)&localRpmsg,
1907 (3U + sizeof(struct rpmsg_std_msg)) >> 2U))
1908 {
1909 seq_num++;
1910 }
1911 else
1912 {
1913 rpmsgStatus = kStatus_HAL_RpmsgError;
1914 }
1915
1916 OSA_EXIT_CRITICAL();
1917 (void)state;
1918 return rpmsgStatus;
1919 }
1920
HAL_ImuInstallCallback(uint8_t imuLink,imu_callback_t callback,uint8_t type)1921 hal_rpmsg_status_t HAL_ImuInstallCallback(uint8_t imuLink, imu_callback_t callback, uint8_t type)
1922 {
1923 hal_imu_handle_t *imuHandle;
1924
1925 assert((uint8_t)kIMU_LinkMax > imuLink);
1926 assert((uint8_t)IMU_MSG_MAX > type);
1927 imuHandle = &imuHandleCh[imuLink];
1928 imuHandle->imuHandler[type] = callback;
1929
1930 return kStatus_HAL_RpmsgSuccess;
1931 }
1932
HAL_ImuInstallIrqCallback(uint8_t imuLink,imu_irq_callback_t callback)1933 hal_rpmsg_status_t HAL_ImuInstallIrqCallback(uint8_t imuLink, imu_irq_callback_t callback)
1934 {
1935 assert((uint8_t)kIMU_LinkMax > imuLink);
1936
1937 imuIrqCallback[imuLink] = callback;
1938
1939 return kStatus_HAL_RpmsgSuccess;
1940 }
1941
HAL_RpmsgInstallRxCallback(hal_rpmsg_handle_t handle,rpmsg_rx_callback_t callback,void * param)1942 hal_rpmsg_status_t HAL_RpmsgInstallRxCallback(hal_rpmsg_handle_t handle, rpmsg_rx_callback_t callback, void *param)
1943 {
1944 hal_rpmsg_state_t *rpmsgHandle;
1945
1946 rpmsgHandle = (hal_rpmsg_state_t *)handle;
1947
1948 rpmsgHandle->rx.callback = callback;
1949 rpmsgHandle->rx.param = param;
1950
1951 return kStatus_HAL_RpmsgSuccess;
1952 }
1953
HAL_RpmsgEnterLowpower(hal_rpmsg_handle_t handle)1954 hal_rpmsg_status_t HAL_RpmsgEnterLowpower(hal_rpmsg_handle_t handle)
1955 {
1956 return kStatus_HAL_RpmsgError;
1957 }
1958
HAL_RpmsgExitLowpower(hal_rpmsg_handle_t handle)1959 hal_rpmsg_status_t HAL_RpmsgExitLowpower(hal_rpmsg_handle_t handle)
1960 {
1961 return kStatus_HAL_RpmsgError;
1962 }
1963
HAL_RpmsgSetEvent(uint32_t Event)1964 void HAL_RpmsgSetEvent(uint32_t Event)
1965 {
1966 #if defined(CPU2)
1967 (void)OSA_EventSet((osa_event_handle_t)ImuQFlagsRef, Event);
1968 #else
1969 if ((Event & (1U << kIMU_LinkCpu1Cpu3)) != 0U)
1970 {
1971 #ifdef __ZEPHYR__
1972 k_event_post(&ImuQ13FlagsRef, Event);
1973 #else
1974 (void)OSA_EventSet((osa_event_handle_t)ImuQ13FlagsRef, Event);
1975 #endif
1976 }
1977 else
1978 {
1979 #ifdef __ZEPHYR__
1980 k_event_post(&ImuQ23FlagsRef, Event);
1981 #else
1982 (void)OSA_EventSet((osa_event_handle_t)ImuQ23FlagsRef, Event);
1983 #endif
1984 }
1985 #endif
1986 }
1987
1988 #if defined(CPU2)
CPU1_TO_CPU2_MSG_RDY_IMU_INT_IRQHandler(void)1989 void CPU1_TO_CPU2_MSG_RDY_IMU_INT_IRQHandler(void)
1990 {
1991 uint32_t irq_num = IMULINKID_TO_IRQID(kIMU_LinkCpu1Cpu2);
1992
1993 /* Mask IMU ICU interrupt */
1994 (void)os_InterruptMaskClear(irq_num);
1995
1996 if (!IMU_RX_FIFO_EMPTY(kIMU_LinkCpu1Cpu2))
1997 {
1998 HAL_RpmsgSetEvent(1U << (uint8_t)kIMU_LinkCpu1Cpu2);
1999 }
2000 else
2001 {
2002 IMU_ClearPendingInterrupts(kIMU_LinkCpu1Cpu2, IMU_MSG_FIFO_CNTL_MSG_RDY_INT_CLR_MASK);
2003 (void)os_InterruptMaskSet(irq_num);
2004 }
2005 }
2006
CPU3_TO_CPU2_MSG_RDY_IMU_INT_IRQHandler(void)2007 void CPU3_TO_CPU2_MSG_RDY_IMU_INT_IRQHandler(void)
2008 {
2009 uint32_t irq_num = IMULINKID_TO_IRQID(kIMU_LinkCpu2Cpu3);
2010
2011 /* Mask IMU ICU interrupt */
2012 (void)os_InterruptMaskClear(irq_num);
2013
2014 if (!IMU_RX_FIFO_EMPTY(kIMU_LinkCpu2Cpu3))
2015 {
2016 HAL_RpmsgSetEvent(1U << (uint8_t)kIMU_LinkCpu2Cpu3);
2017 }
2018 else
2019 {
2020 IMU_ClearPendingInterrupts(kIMU_LinkCpu2Cpu3, IMU_MSG_FIFO_CNTL_MSG_RDY_INT_CLR_MASK);
2021 (void)os_InterruptMaskSet(irq_num);
2022 }
2023 }
2024 #else
2025
WL_MCI_WAKEUP0_DriverIRQHandler(void)2026 void WL_MCI_WAKEUP0_DriverIRQHandler(void)
2027 {
2028 IRQn_Type irq_num;
2029 #if defined(CPU2)
2030 irq_num = IRQ_IMU_CPU32;
2031 #else
2032 irq_num = IRQ_IMU_CPU13;
2033 #endif
2034
2035 /* Mask IMU ICU interrupt */
2036 (void)os_InterruptMaskClear(irq_num);
2037
2038 if (!IMU_RX_FIFO_EMPTY(kIMU_LinkCpu1Cpu3))
2039 {
2040 HAL_RpmsgSetEvent(1U << (uint8_t)kIMU_LinkCpu1Cpu3);
2041 }
2042 else
2043 {
2044 IMU_ClearPendingInterrupts(kIMU_LinkCpu1Cpu3, IMU_MSG_FIFO_CNTL_MSG_RDY_INT_CLR_MASK);
2045 (void)os_InterruptMaskSet(irq_num);
2046 }
2047 }
2048
BLE_MCI_WAKEUP0_DriverIRQHandler(void)2049 void BLE_MCI_WAKEUP0_DriverIRQHandler(void)
2050 {
2051 IRQn_Type irq_num;
2052 #if defined(CPU2)
2053 irq_num = IRQ_IMU_CPU12;
2054 #else
2055 irq_num = IRQ_IMU_CPU23;
2056 #endif
2057
2058 /* Mask IMU ICU interrupt */
2059 (void)os_InterruptMaskClear(irq_num);
2060
2061 if (!IMU_RX_FIFO_EMPTY(kIMU_LinkCpu2Cpu3))
2062 {
2063 HAL_RpmsgSetEvent(1U << (uint8_t)kIMU_LinkCpu2Cpu3);
2064 }
2065 else
2066 {
2067 if (imuIrqCallback[kIMU_LinkCpu2Cpu3] != NULL)
2068 {
2069 imuIrqCallback[kIMU_LinkCpu2Cpu3]();
2070 }
2071
2072 IMU_ClearPendingInterrupts(kIMU_LinkCpu2Cpu3, IMU_MSG_FIFO_CNTL_MSG_RDY_INT_CLR_MASK);
2073 (void)os_InterruptMaskSet(irq_num);
2074 }
2075 }
2076 #endif
2077
HAL_RpmsgAllocTxBuffer(hal_rpmsg_handle_t handle,uint32_t size)2078 void *HAL_RpmsgAllocTxBuffer(hal_rpmsg_handle_t handle, uint32_t size)
2079 {
2080 hal_rpmsg_state_t *rpmsgHandle;
2081 hal_imu_handle_t *imuHandle;
2082 uint32_t retry = RPMSG_ALLOC_RETRY_COUNT;
2083 void *buf = NULL;
2084
2085 rpmsgHandle = (hal_rpmsg_state_t *)handle;
2086
2087 if (rpmsgHandle->imuLink == (uint8_t)kIMU_LinkCpu2Cpu3)
2088 {
2089 assert(RPMSG_TXQ23_BUFLENGTH >= size);
2090 }
2091 else
2092 {
2093 assert(RPMSG_TXQ13_BUFLENGTH >= size);
2094 }
2095
2096 assert(NULL != handle);
2097
2098 imuHandle = &imuHandleCh[rpmsgHandle->imuLink];
2099
2100 buf = HAL_RpmsgGetTxBuf(imuHandle);
2101
2102 while ((buf == NULL) && (retry != 0U))
2103 {
2104 /* Sleep current thread, then try to allocate again */
2105 OSA_TimeDelay(RPMSG_ALLOC_FAILED_DELAY_MS);
2106 buf = HAL_RpmsgGetTxBuf(imuHandle);
2107 retry--;
2108 }
2109
2110 return buf;
2111 }
2112
HAL_RpmsgFreeRxBuffer(hal_rpmsg_handle_t handle,uint8_t * data)2113 hal_rpmsg_status_t HAL_RpmsgFreeRxBuffer(hal_rpmsg_handle_t handle, uint8_t *data)
2114 {
2115 hal_rpmsg_state_t *rpmsgHandle;
2116 hal_imu_handle_t *imuHandle;
2117
2118 assert(NULL != handle);
2119
2120 rpmsgHandle = (hal_rpmsg_state_t *)handle;
2121 imuHandle = &imuHandleCh[rpmsgHandle->imuLink];
2122
2123 return HAL_ImuSendRpmsgFreeBuf(imuHandle, data);
2124 }
2125
HAL_ImuIsTxBufQueueEmpty(uint8_t imuLink)2126 bool HAL_ImuIsTxBufQueueEmpty(uint8_t imuLink)
2127 {
2128 hal_imu_handle_t *imuHandle;
2129 IMU_WLAN_TXQ_CTRL_st *wlanTxqCtl;
2130
2131 assert((uint8_t)kIMU_LinkMax > imuLink);
2132
2133 imuHandle = &imuHandleCh[imuLink];
2134 wlanTxqCtl = &imuHandle->wlanTxqCtl;
2135
2136 return (IS_WLAN_TXBQ_EMPTY(wlanTxqCtl));
2137 }
2138
2139 #if (defined(USE_RTOS) && (USE_RTOS > 0U))
HAL_ImuCreateTaskLock(void)2140 hal_rpmsg_status_t HAL_ImuCreateTaskLock(void)
2141 {
2142 #ifdef __ZEPHYR__
2143 k_mutex_init(&imu_task_lock);
2144 #else
2145 osa_status_t status;
2146
2147 if ((*(uint32_t *)(osa_mutex_handle_t)imu_task_lock) == 0)
2148 {
2149 status = OSA_MutexCreate((osa_mutex_handle_t)imu_task_lock);
2150 if (status == KOSA_StatusError)
2151 {
2152 return kStatus_HAL_RpmsgError;
2153 }
2154 }
2155 #endif
2156 return kStatus_HAL_RpmsgSuccess;
2157 }
2158
HAL_ImuDeleteTaskLock(void)2159 void HAL_ImuDeleteTaskLock(void)
2160 {
2161 #ifndef __ZEPHYR__
2162 if ((*(uint32_t *)(osa_mutex_handle_t)imu_task_lock) != 0)
2163 {
2164 (void)OSA_MutexDestroy((osa_mutex_handle_t)imu_task_lock);
2165 (*(uint32_t *)(osa_mutex_handle_t)imu_task_lock) = 0;
2166 }
2167 #endif
2168 }
2169
HAL_ImuGetTaskLock(void)2170 hal_rpmsg_status_t HAL_ImuGetTaskLock(void)
2171 {
2172 #ifdef __ZEPHYR__
2173 int ret = k_mutex_lock(&imu_task_lock, K_FOREVER);
2174
2175 return (ret == 0) ? kStatus_HAL_RpmsgSuccess : kStatus_HAL_RpmsgError;
2176 #else
2177 osa_status_t status;
2178
2179 if ((*(uint32_t *)(osa_mutex_handle_t)imu_task_lock) == 0)
2180 {
2181 return kStatus_HAL_RpmsgSuccess;
2182 }
2183
2184 status = OSA_MutexLock((osa_mutex_handle_t)imu_task_lock, osaWaitForever_c);
2185 return status == KOSA_StatusSuccess ? kStatus_HAL_RpmsgSuccess : kStatus_HAL_RpmsgError;
2186 #endif
2187 }
2188
HAL_ImuPutTaskLock(void)2189 hal_rpmsg_status_t HAL_ImuPutTaskLock(void)
2190 {
2191 #ifdef __ZEPHYR__
2192 int ret = k_mutex_unlock(&imu_task_lock);
2193
2194 return (ret == 0) ? kStatus_HAL_RpmsgSuccess : kStatus_HAL_RpmsgError;
2195 #else
2196
2197 osa_status_t status;
2198
2199 if ((*(uint32_t *)(osa_mutex_handle_t)imu_task_lock) == 0)
2200 {
2201 return kStatus_HAL_RpmsgSuccess;
2202 }
2203
2204 status = OSA_MutexUnlock((osa_mutex_handle_t)imu_task_lock);
2205 return status == KOSA_StatusSuccess ? kStatus_HAL_RpmsgSuccess : kStatus_HAL_RpmsgError;
2206 #endif
2207 }
2208 #endif
2209
