1 /*
2 * Copyright (c) 2020 Vossloh Cogifer
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #define DT_DRV_COMPAT st_stm32h7_flash_controller
8
9 #include <zephyr/sys/util.h>
10 #include <zephyr/kernel.h>
11 #include <zephyr/device.h>
12 #include <string.h>
13 #include <zephyr/drivers/flash.h>
14 #include <zephyr/init.h>
15 #include <zephyr/sys/barrier.h>
16 #include <soc.h>
17 #include <stm32h7xx_ll_bus.h>
18 #include <stm32h7xx_ll_utils.h>
19
20 #include "flash_stm32.h"
21 #include "stm32_hsem.h"
22
23 #define LOG_DOMAIN flash_stm32h7
24 #define LOG_LEVEL CONFIG_FLASH_LOG_LEVEL
25 #include <zephyr/logging/log.h>
26 LOG_MODULE_REGISTER(LOG_DOMAIN);
27
28 /* Let's wait for double the max erase time to be sure that the operation is
29 * completed.
30 */
31 #define STM32H7_FLASH_TIMEOUT \
32 (2 * DT_PROP(DT_INST(0, st_stm32_nv_flash), max_erase_time))
33
34 #ifdef CONFIG_CPU_CORTEX_M4
35 #error Flash driver on M4 core is not supported yet
36 #endif
37
38 #define REAL_FLASH_SIZE_KB KB(LL_GetFlashSize())
39 #define SECTOR_PER_BANK ((REAL_FLASH_SIZE_KB / FLASH_SECTOR_SIZE) / 2)
40 #if defined(DUAL_BANK)
41 #define STM32H7_SERIES_MAX_FLASH_KB KB(2048)
42 #define BANK2_OFFSET (STM32H7_SERIES_MAX_FLASH_KB / 2)
43 /* When flash is dual bank and flash size is smaller than Max flash size of
44 * the serie, there is a discontinuty between bank1 and bank2.
45 */
46 #define DISCONTINUOUS_BANKS (REAL_FLASH_SIZE_KB < STM32H7_SERIES_MAX_FLASH_KB)
47 #endif
48
49 struct flash_stm32_sector_t {
50 int sector_index;
51 int bank;
52 volatile uint32_t *cr;
53 volatile uint32_t *sr;
54 };
55
56 #if defined(CONFIG_MULTITHREADING) || defined(CONFIG_STM32H7_DUAL_CORE)
57 /*
58 * This is named flash_stm32_sem_take instead of flash_stm32_lock (and
59 * similarly for flash_stm32_sem_give) to avoid confusion with locking
60 * actual flash sectors.
61 */
_flash_stm32_sem_take(const struct device * dev)62 static inline void _flash_stm32_sem_take(const struct device *dev)
63 {
64 k_sem_take(&FLASH_STM32_PRIV(dev)->sem, K_FOREVER);
65 z_stm32_hsem_lock(CFG_HW_FLASH_SEMID, HSEM_LOCK_WAIT_FOREVER);
66 }
67
_flash_stm32_sem_give(const struct device * dev)68 static inline void _flash_stm32_sem_give(const struct device *dev)
69 {
70 z_stm32_hsem_unlock(CFG_HW_FLASH_SEMID);
71 k_sem_give(&FLASH_STM32_PRIV(dev)->sem);
72 }
73
74 #define flash_stm32_sem_init(dev) k_sem_init(&FLASH_STM32_PRIV(dev)->sem, 1, 1)
75 #define flash_stm32_sem_take(dev) _flash_stm32_sem_take(dev)
76 #define flash_stm32_sem_give(dev) _flash_stm32_sem_give(dev)
77 #else
78 #define flash_stm32_sem_init(dev)
79 #define flash_stm32_sem_take(dev)
80 #define flash_stm32_sem_give(dev)
81 #endif
82
flash_stm32_valid_range(const struct device * dev,off_t offset,uint32_t len,bool write)83 bool flash_stm32_valid_range(const struct device *dev, off_t offset,
84 uint32_t len,
85 bool write)
86 {
87 #if defined(DUAL_BANK)
88 if (DISCONTINUOUS_BANKS) {
89 /*
90 * In case of bank1/2 discontinuity, the range should not
91 * start before bank2 and end beyond bank1 at the same time.
92 * Locations beyond bank2 are caught by flash_stm32_range_exists
93 */
94 if ((offset < BANK2_OFFSET)
95 && (offset + len > REAL_FLASH_SIZE_KB / 2)) {
96 LOG_ERR("Range ovelaps flash bank discontinuity");
97 return false;
98 }
99 }
100 #endif
101
102 if (write) {
103 if ((offset % (FLASH_NB_32BITWORD_IN_FLASHWORD * 4)) != 0) {
104 LOG_ERR("Write offset not aligned on flashword length. "
105 "Offset: 0x%lx, flashword length: %d",
106 (unsigned long) offset, FLASH_NB_32BITWORD_IN_FLASHWORD * 4);
107 return false;
108 }
109 }
110 return flash_stm32_range_exists(dev, offset, len);
111 }
112
flash_stm32_check_status(const struct device * dev)113 static int flash_stm32_check_status(const struct device *dev)
114 {
115 FLASH_TypeDef *regs = FLASH_STM32_REGS(dev);
116 /* The hardware corrects single ECC errors and detects double
117 * ECC errors. Corrected data is returned for single ECC
118 * errors, so in this case we just log a warning.
119 */
120 uint32_t const error_bank1 = (FLASH_FLAG_ALL_ERRORS_BANK1
121 & ~FLASH_FLAG_SNECCERR_BANK1);
122 #ifdef DUAL_BANK
123 uint32_t const error_bank2 = (FLASH_FLAG_ALL_ERRORS_BANK2
124 & ~FLASH_FLAG_SNECCERR_BANK2);
125 #endif
126 uint32_t sr;
127
128 /* Read the status flags. */
129 sr = regs->SR1;
130 if (sr & (FLASH_FLAG_SNECCERR_BANK1|FLASH_FLAG_DBECCERR_BANK1)) {
131 uint32_t word = regs->ECC_FA1 & FLASH_ECC_FA_FAIL_ECC_ADDR;
132
133 LOG_WRN("Bank%d ECC error at 0x%08x", 1,
134 word * 4 * FLASH_NB_32BITWORD_IN_FLASHWORD);
135 }
136 /* Clear the flags (including FA1R) */
137 regs->CCR1 = FLASH_FLAG_ALL_BANK1;
138 if (sr & error_bank1) {
139 LOG_ERR("Status Bank%d: 0x%08x", 1, sr);
140 return -EIO;
141 }
142
143 #ifdef DUAL_BANK
144 sr = regs->SR2;
145 if (sr & (FLASH_FLAG_SNECCERR_BANK1|FLASH_FLAG_DBECCERR_BANK1)) {
146 uint32_t word = regs->ECC_FA2 & FLASH_ECC_FA_FAIL_ECC_ADDR;
147
148 LOG_WRN("Bank%d ECC error at 0x%08x", 2,
149 word * 4 * FLASH_NB_32BITWORD_IN_FLASHWORD);
150 }
151 regs->CCR2 = FLASH_FLAG_ALL_BANK2;
152 if (sr & error_bank2) {
153 LOG_ERR("Status Bank%d: 0x%08x", 2, sr);
154 return -EIO;
155 }
156 #endif
157
158 return 0;
159 }
160
161
flash_stm32_wait_flash_idle(const struct device * dev)162 int flash_stm32_wait_flash_idle(const struct device *dev)
163 {
164 int64_t timeout_time = k_uptime_get() + STM32H7_FLASH_TIMEOUT;
165 int rc;
166
167 rc = flash_stm32_check_status(dev);
168 if (rc < 0) {
169 return -EIO;
170 }
171 #ifdef DUAL_BANK
172 while ((FLASH_STM32_REGS(dev)->SR1 & FLASH_SR_QW)
173 || (FLASH_STM32_REGS(dev)->SR2 & FLASH_SR_QW))
174 #else
175 while (FLASH_STM32_REGS(dev)->SR1 & FLASH_SR_QW)
176 #endif
177 {
178 if (k_uptime_get() > timeout_time) {
179 LOG_ERR("Timeout! val: %d", STM32H7_FLASH_TIMEOUT);
180 return -EIO;
181 }
182 }
183
184 return 0;
185 }
186
get_sector(const struct device * dev,off_t offset)187 static struct flash_stm32_sector_t get_sector(const struct device *dev,
188 off_t offset)
189 {
190 struct flash_stm32_sector_t sector;
191 FLASH_TypeDef *regs = FLASH_STM32_REGS(dev);
192
193 #ifdef DUAL_BANK
194 bool bank_swap;
195 /* Check whether bank1/2 are swapped */
196 bank_swap = (READ_BIT(FLASH->OPTCR, FLASH_OPTCR_SWAP_BANK)
197 == FLASH_OPTCR_SWAP_BANK);
198 sector.sector_index = offset / FLASH_SECTOR_SIZE;
199 if ((offset < (REAL_FLASH_SIZE_KB / 2)) && !bank_swap) {
200 sector.bank = 1;
201 sector.cr = ®s->CR1;
202 sector.sr = ®s->SR1;
203 } else if ((offset >= BANK2_OFFSET) && bank_swap) {
204 sector.sector_index -= BANK2_OFFSET / FLASH_SECTOR_SIZE;
205 sector.bank = 1;
206 sector.cr = ®s->CR2;
207 sector.sr = ®s->SR2;
208 } else if ((offset < (REAL_FLASH_SIZE_KB / 2)) && bank_swap) {
209 sector.bank = 2;
210 sector.cr = ®s->CR1;
211 sector.sr = ®s->SR1;
212 } else if ((offset >= BANK2_OFFSET) && !bank_swap) {
213 sector.sector_index -= BANK2_OFFSET / FLASH_SECTOR_SIZE;
214 sector.bank = 2;
215 sector.cr = ®s->CR2;
216 sector.sr = ®s->SR2;
217 } else {
218 sector.sector_index = 0;
219 sector.bank = 0;
220 sector.cr = NULL;
221 sector.sr = NULL;
222 }
223 #else
224 if (offset < REAL_FLASH_SIZE_KB) {
225 sector.sector_index = offset / FLASH_SECTOR_SIZE;
226 sector.bank = 1;
227 sector.cr = ®s->CR1;
228 sector.sr = ®s->SR1;
229 } else {
230 sector.sector_index = 0;
231 sector.bank = 0;
232 sector.cr = NULL;
233 sector.sr = NULL;
234 }
235 #endif
236
237 return sector;
238 }
239
erase_sector(const struct device * dev,int offset)240 static int erase_sector(const struct device *dev, int offset)
241 {
242 int rc;
243 struct flash_stm32_sector_t sector = get_sector(dev, offset);
244
245 if (sector.bank == 0) {
246
247 LOG_ERR("Offset %ld does not exist", (long) offset);
248 return -EINVAL;
249 }
250
251 /* if the control register is locked, do not fail silently */
252 if (*(sector.cr) & FLASH_CR_LOCK) {
253 return -EIO;
254 }
255
256 rc = flash_stm32_wait_flash_idle(dev);
257 if (rc < 0) {
258 return rc;
259 }
260
261 *(sector.cr) &= ~FLASH_CR_SNB;
262 *(sector.cr) |= (FLASH_CR_SER
263 | ((sector.sector_index << FLASH_CR_SNB_Pos) & FLASH_CR_SNB));
264 *(sector.cr) |= FLASH_CR_START;
265 /* flush the register write */
266 barrier_dsync_fence_full();
267
268 rc = flash_stm32_wait_flash_idle(dev);
269 *(sector.cr) &= ~(FLASH_CR_SER | FLASH_CR_SNB);
270
271 return rc;
272 }
273
274
flash_stm32_block_erase_loop(const struct device * dev,unsigned int offset,unsigned int len)275 int flash_stm32_block_erase_loop(const struct device *dev,
276 unsigned int offset,
277 unsigned int len)
278 {
279 unsigned int address = offset;
280 int rc = 0;
281
282 for (; address <= offset + len - 1 ; address += FLASH_SECTOR_SIZE) {
283 rc = erase_sector(dev, address);
284 if (rc < 0) {
285 break;
286 }
287 }
288 return rc;
289 }
290
wait_write_queue(const struct flash_stm32_sector_t * sector)291 static int wait_write_queue(const struct flash_stm32_sector_t *sector)
292 {
293 int64_t timeout_time = k_uptime_get() + 100;
294
295 while (*(sector->sr) & FLASH_SR_QW) {
296 if (k_uptime_get() > timeout_time) {
297 LOG_ERR("Timeout! val: %d", 100);
298 return -EIO;
299 }
300 }
301
302 return 0;
303 }
304
write_ndwords(const struct device * dev,off_t offset,const uint64_t * data,uint8_t n)305 static int write_ndwords(const struct device *dev,
306 off_t offset, const uint64_t *data,
307 uint8_t n)
308 {
309 volatile uint64_t *flash = (uint64_t *)(offset
310 + FLASH_STM32_BASE_ADDRESS);
311 int rc;
312 int i;
313 struct flash_stm32_sector_t sector = get_sector(dev, offset);
314
315 if (sector.bank == 0) {
316 LOG_ERR("Offset %ld does not exist", (long) offset);
317 return -EINVAL;
318 }
319
320 /* if the control register is locked, do not fail silently */
321 if (*(sector.cr) & FLASH_CR_LOCK) {
322 return -EIO;
323 }
324
325 /* Check that no Flash main memory operation is ongoing */
326 rc = flash_stm32_wait_flash_idle(dev);
327 if (rc < 0) {
328 return rc;
329 }
330
331 /* Check if 256 bits location is erased */
332 for (i = 0; i < n; ++i) {
333 if (flash[i] != 0xFFFFFFFFFFFFFFFFUL) {
334 return -EIO;
335 }
336 }
337
338 /* Set the PG bit */
339 *(sector.cr) |= FLASH_CR_PG;
340
341 /* Flush the register write */
342 barrier_dsync_fence_full();
343
344 /* Perform the data write operation at the desired memory address */
345 for (i = 0; i < n; ++i) {
346 /* Source dword may be unaligned, so take extra care when dereferencing it */
347 flash[i] = UNALIGNED_GET(data + i);
348
349 /* Flush the data write */
350 barrier_dsync_fence_full();
351
352 wait_write_queue(§or);
353 }
354
355 /* Wait until the BSY bit is cleared */
356 rc = flash_stm32_wait_flash_idle(dev);
357
358 /* Clear the PG bit */
359 *(sector.cr) &= (~FLASH_CR_PG);
360
361 return rc;
362 }
363
flash_stm32_write_range(const struct device * dev,unsigned int offset,const void * data,unsigned int len)364 int flash_stm32_write_range(const struct device *dev, unsigned int offset,
365 const void *data, unsigned int len)
366 {
367 int rc = 0;
368 int i, j;
369 const uint8_t ndwords = FLASH_NB_32BITWORD_IN_FLASHWORD / 2;
370 const uint8_t nbytes = FLASH_NB_32BITWORD_IN_FLASHWORD * 4;
371 uint8_t unaligned_datas[nbytes];
372
373 for (i = 0; i < len && i + nbytes <= len; i += nbytes, offset += nbytes) {
374 rc = write_ndwords(dev, offset,
375 (const uint64_t *) data + (i >> 3),
376 ndwords);
377 if (rc < 0) {
378 return rc;
379 }
380 }
381
382 /* Handle the remaining bytes if length is not aligned on
383 * FLASH_NB_32BITWORD_IN_FLASHWORD
384 */
385 if (i < len) {
386 memset(unaligned_datas, 0xff, sizeof(unaligned_datas));
387 for (j = 0; j < len - i; ++j) {
388 unaligned_datas[j] = ((uint8_t *)data)[i + j];
389 }
390 rc = write_ndwords(dev, offset,
391 (const uint64_t *)unaligned_datas,
392 ndwords);
393 if (rc < 0) {
394 return rc;
395 }
396 }
397
398 return rc;
399 }
400
flash_stm32h7_write_protection(const struct device * dev,bool enable)401 static int flash_stm32h7_write_protection(const struct device *dev, bool enable)
402 {
403 FLASH_TypeDef *regs = FLASH_STM32_REGS(dev);
404
405 int rc = 0;
406
407 if (enable) {
408 rc = flash_stm32_wait_flash_idle(dev);
409 if (rc) {
410 return rc;
411 }
412 }
413
414 /* Bank 1 */
415 if (enable) {
416 regs->CR1 |= FLASH_CR_LOCK;
417 } else {
418 if (regs->CR1 & FLASH_CR_LOCK) {
419 regs->KEYR1 = FLASH_KEY1;
420 regs->KEYR1 = FLASH_KEY2;
421 }
422 }
423 #ifdef DUAL_BANK
424 /* Bank 2 */
425 if (enable) {
426 regs->CR2 |= FLASH_CR_LOCK;
427 } else {
428 if (regs->CR2 & FLASH_CR_LOCK) {
429 regs->KEYR2 = FLASH_KEY1;
430 regs->KEYR2 = FLASH_KEY2;
431 }
432 }
433 #endif
434
435 if (enable) {
436 LOG_DBG("Enable write protection");
437 } else {
438 LOG_DBG("Disable write protection");
439 }
440
441 return rc;
442 }
443
444 #ifdef CONFIG_CPU_CORTEX_M7
flash_stm32h7_flush_caches(const struct device * dev,off_t offset,size_t len)445 static void flash_stm32h7_flush_caches(const struct device *dev,
446 off_t offset, size_t len)
447 {
448 ARG_UNUSED(dev);
449
450 if (!(SCB->CCR & SCB_CCR_DC_Msk)) {
451 return; /* Cache not enabled */
452 }
453
454 SCB_InvalidateDCache_by_Addr((uint32_t *)(FLASH_STM32_BASE_ADDRESS
455 + offset), len);
456 }
457 #endif /* CONFIG_CPU_CORTEX_M7 */
458
flash_stm32h7_erase(const struct device * dev,off_t offset,size_t len)459 static int flash_stm32h7_erase(const struct device *dev, off_t offset,
460 size_t len)
461 {
462 int rc, rc2;
463
464 #ifdef CONFIG_CPU_CORTEX_M7
465 /* Flush whole sectors */
466 off_t flush_offset = ROUND_DOWN(offset, FLASH_SECTOR_SIZE);
467 size_t flush_len = ROUND_UP(offset + len - 1, FLASH_SECTOR_SIZE)
468 - flush_offset;
469 #endif /* CONFIG_CPU_CORTEX_M7 */
470
471 if (!flash_stm32_valid_range(dev, offset, len, true)) {
472 LOG_ERR("Erase range invalid. Offset: %ld, len: %zu",
473 (long) offset, len);
474 return -EINVAL;
475 }
476
477 if (!len) {
478 return 0;
479 }
480
481 flash_stm32_sem_take(dev);
482
483 LOG_DBG("Erase offset: %ld, len: %zu", (long) offset, len);
484
485 rc = flash_stm32h7_write_protection(dev, false);
486 if (rc) {
487 goto done;
488 }
489
490 rc = flash_stm32_block_erase_loop(dev, offset, len);
491
492 #ifdef CONFIG_CPU_CORTEX_M7
493 /* Flush cache on all sectors affected by the erase */
494 flash_stm32h7_flush_caches(dev, flush_offset, flush_len);
495 #elif CONFIG_CPU_CORTEX_M4
496 if (LL_AHB1_GRP1_IsEnabledClock(LL_AHB1_GRP1_PERIPH_ART)
497 && LL_ART_IsEnabled()) {
498 LOG_ERR("Cortex M4: ART enabled not supported by flash driver");
499 }
500 #endif /* CONFIG_CPU_CORTEX_M7 */
501 done:
502 rc2 = flash_stm32h7_write_protection(dev, true);
503
504 if (!rc) {
505 rc = rc2;
506 }
507
508 flash_stm32_sem_give(dev);
509
510 return rc;
511 }
512
513
flash_stm32h7_write(const struct device * dev,off_t offset,const void * data,size_t len)514 static int flash_stm32h7_write(const struct device *dev, off_t offset,
515 const void *data, size_t len)
516 {
517 int rc;
518
519 if (!flash_stm32_valid_range(dev, offset, len, true)) {
520 LOG_ERR("Write range invalid. Offset: %ld, len: %zu",
521 (long) offset, len);
522 return -EINVAL;
523 }
524
525 if (!len) {
526 return 0;
527 }
528
529 flash_stm32_sem_take(dev);
530
531 LOG_DBG("Write offset: %ld, len: %zu", (long) offset, len);
532
533 rc = flash_stm32h7_write_protection(dev, false);
534 if (!rc) {
535 rc = flash_stm32_write_range(dev, offset, data, len);
536 }
537
538 int rc2 = flash_stm32h7_write_protection(dev, true);
539
540 if (!rc) {
541 rc = rc2;
542 }
543
544 flash_stm32_sem_give(dev);
545
546 return rc;
547 }
548
flash_stm32h7_read(const struct device * dev,off_t offset,void * data,size_t len)549 static int flash_stm32h7_read(const struct device *dev, off_t offset,
550 void *data,
551 size_t len)
552 {
553 if (!flash_stm32_valid_range(dev, offset, len, false)) {
554 LOG_ERR("Read range invalid. Offset: %ld, len: %zu",
555 (long) offset, len);
556 return -EINVAL;
557 }
558
559 if (!len) {
560 return 0;
561 }
562
563 LOG_DBG("Read offset: %ld, len: %zu", (long) offset, len);
564
565 /* During the read we mask bus errors and only allow NMI.
566 *
567 * If the flash has a double ECC error then there is normally
568 * a bus fault, but we want to return an error code instead.
569 */
570 unsigned int irq_lock_key = irq_lock();
571
572 __set_FAULTMASK(1);
573 SCB->CCR |= SCB_CCR_BFHFNMIGN_Msk;
574 barrier_dsync_fence_full();
575 barrier_isync_fence_full();
576
577 memcpy(data, (uint8_t *) FLASH_STM32_BASE_ADDRESS + offset, len);
578
579 __set_FAULTMASK(0);
580 SCB->CCR &= ~SCB_CCR_BFHFNMIGN_Msk;
581 barrier_dsync_fence_full();
582 barrier_isync_fence_full();
583 irq_unlock(irq_lock_key);
584
585 return flash_stm32_check_status(dev);
586 }
587
588
589 static const struct flash_parameters flash_stm32h7_parameters = {
590 .write_block_size = FLASH_STM32_WRITE_BLOCK_SIZE,
591 .erase_value = 0xff,
592 };
593
594 static const struct flash_parameters *
flash_stm32h7_get_parameters(const struct device * dev)595 flash_stm32h7_get_parameters(const struct device *dev)
596 {
597 ARG_UNUSED(dev);
598
599 return &flash_stm32h7_parameters;
600 }
601
602
flash_stm32_page_layout(const struct device * dev,const struct flash_pages_layout ** layout,size_t * layout_size)603 void flash_stm32_page_layout(const struct device *dev,
604 const struct flash_pages_layout **layout,
605 size_t *layout_size)
606 {
607 ARG_UNUSED(dev);
608
609 #if defined(DUAL_BANK)
610 static struct flash_pages_layout stm32h7_flash_layout[3];
611
612 if (DISCONTINUOUS_BANKS) {
613 if (stm32h7_flash_layout[0].pages_count == 0) {
614 /* Bank1 */
615 stm32h7_flash_layout[0].pages_count = SECTOR_PER_BANK;
616 stm32h7_flash_layout[0].pages_size = FLASH_SECTOR_SIZE;
617 /*
618 * Dummy page corresponding to discontinuity
619 * between bank1/2
620 */
621 stm32h7_flash_layout[1].pages_count = 1;
622 stm32h7_flash_layout[1].pages_size = BANK2_OFFSET
623 - (SECTOR_PER_BANK * FLASH_SECTOR_SIZE);
624 /* Bank2 */
625 stm32h7_flash_layout[2].pages_count = SECTOR_PER_BANK;
626 stm32h7_flash_layout[2].pages_size = FLASH_SECTOR_SIZE;
627 }
628 *layout_size = ARRAY_SIZE(stm32h7_flash_layout);
629 } else {
630 if (stm32h7_flash_layout[0].pages_count == 0) {
631 stm32h7_flash_layout[0].pages_count =
632 REAL_FLASH_SIZE_KB / FLASH_SECTOR_SIZE;
633 stm32h7_flash_layout[0].pages_size = FLASH_SECTOR_SIZE;
634 }
635 *layout_size = 1;
636 }
637 #else
638 static struct flash_pages_layout stm32h7_flash_layout[1];
639
640 if (stm32h7_flash_layout[0].pages_count == 0) {
641 stm32h7_flash_layout[0].pages_count =
642 REAL_FLASH_SIZE_KB / FLASH_SECTOR_SIZE;
643 stm32h7_flash_layout[0].pages_size = FLASH_SECTOR_SIZE;
644 }
645 *layout_size = ARRAY_SIZE(stm32h7_flash_layout);
646 #endif
647 *layout = stm32h7_flash_layout;
648 }
649
650 static struct flash_stm32_priv flash_data = {
651 .regs = (FLASH_TypeDef *) DT_INST_REG_ADDR(0),
652 .pclken = { .bus = DT_INST_CLOCKS_CELL(0, bus),
653 .enr = DT_INST_CLOCKS_CELL(0, bits)},
654 };
655
656 static const struct flash_driver_api flash_stm32h7_api = {
657 .erase = flash_stm32h7_erase,
658 .write = flash_stm32h7_write,
659 .read = flash_stm32h7_read,
660 .get_parameters = flash_stm32h7_get_parameters,
661 #ifdef CONFIG_FLASH_PAGE_LAYOUT
662 .page_layout = flash_stm32_page_layout,
663 #endif
664 };
665
stm32h7_flash_init(const struct device * dev)666 static int stm32h7_flash_init(const struct device *dev)
667 {
668 struct flash_stm32_priv *p = FLASH_STM32_PRIV(dev);
669 const struct device *const clk = DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE);
670
671 if (!device_is_ready(clk)) {
672 LOG_ERR("clock control device not ready");
673 return -ENODEV;
674 }
675
676 /* enable clock */
677 if (clock_control_on(clk, (clock_control_subsys_t)&p->pclken) != 0) {
678 LOG_ERR("Failed to enable clock");
679 return -EIO;
680 }
681
682 flash_stm32_sem_init(dev);
683
684 LOG_DBG("Flash initialized. BS: %zu",
685 flash_stm32h7_parameters.write_block_size);
686
687 #if ((CONFIG_FLASH_LOG_LEVEL >= LOG_LEVEL_DBG) && CONFIG_FLASH_PAGE_LAYOUT)
688 const struct flash_pages_layout *layout;
689 size_t layout_size;
690
691 flash_stm32_page_layout(dev, &layout, &layout_size);
692 for (size_t i = 0; i < layout_size; i++) {
693 LOG_DBG("Block %zu: bs: %zu count: %zu", i,
694 layout[i].pages_size, layout[i].pages_count);
695 }
696 #endif
697
698 return flash_stm32h7_write_protection(dev, false);
699 }
700
701
702 DEVICE_DT_INST_DEFINE(0, stm32h7_flash_init, NULL,
703 &flash_data, NULL, POST_KERNEL,
704 CONFIG_FLASH_INIT_PRIORITY, &flash_stm32h7_api);
705
