1 /*
2 * Copyright (c) 2019 Philippe Retornaz <philippe@shapescale.com>
3 * Copyright (c) 2017 Linaro Limited
4 * Copyright (c) 2017 BayLibre, SAS
5 *
6 * SPDX-License-Identifier: Apache-2.0
7 */
8
9 #define LOG_DOMAIN flash_stm32g0
10 #define LOG_LEVEL CONFIG_FLASH_LOG_LEVEL
11 #include <zephyr/logging/log.h>
12 LOG_MODULE_REGISTER(LOG_DOMAIN);
13
14 #include <zephyr/kernel.h>
15 #include <zephyr/device.h>
16 #include <string.h>
17 #include <zephyr/drivers/flash.h>
18 #include <zephyr/init.h>
19 #include <soc.h>
20
21 #include "flash_stm32.h"
22
23
24 /* FLASH_DBANK_SUPPORT is defined in the HAL for all G0Bx and G0C1 SoCs,
25 * while only those with 256KiB and 512KiB Flash have two banks.
26 */
27 #if defined(FLASH_DBANK_SUPPORT) && (CONFIG_FLASH_SIZE > (128))
28 #define STM32G0_DBANK_SUPPORT
29 #endif
30
31 #if defined(STM32G0_DBANK_SUPPORT)
32 #define STM32G0_BANK_COUNT 2
33 #define STM32G0_BANK2_START_PAGE_NR 256
34 #else
35 #define STM32G0_BANK_COUNT 1
36 #endif
37
38 #define STM32G0_FLASH_SIZE (FLASH_SIZE)
39 #define STM32G0_FLASH_PAGE_SIZE (FLASH_PAGE_SIZE)
40 #define STM32G0_PAGES_PER_BANK \
41 ((STM32G0_FLASH_SIZE / STM32G0_FLASH_PAGE_SIZE) / STM32G0_BANK_COUNT)
42
flush_cache(FLASH_TypeDef * regs)43 static inline void flush_cache(FLASH_TypeDef *regs)
44 {
45 if (regs->ACR & FLASH_ACR_ICEN) {
46 regs->ACR &= ~FLASH_ACR_ICEN;
47 /* Datasheet: ICRST: Instruction cache reset :
48 * This bit can be written only when the instruction cache
49 * is disabled
50 */
51 regs->ACR |= FLASH_ACR_ICRST;
52 regs->ACR &= ~FLASH_ACR_ICRST;
53 regs->ACR |= FLASH_ACR_ICEN;
54 }
55 }
56
write_dword(const struct device * dev,off_t offset,uint64_t val)57 static int write_dword(const struct device *dev, off_t offset, uint64_t val)
58 {
59 volatile uint32_t *flash = (uint32_t *)(offset + FLASH_STM32_BASE_ADDRESS);
60 FLASH_TypeDef *regs = FLASH_STM32_REGS(dev);
61 uint32_t tmp;
62 int rc;
63
64 /* if the control register is locked, do not fail silently */
65 if (regs->CR & FLASH_CR_LOCK) {
66 return -EIO;
67 }
68
69 /* Check that no Flash main memory operation is ongoing */
70 rc = flash_stm32_wait_flash_idle(dev);
71 if (rc < 0) {
72 return rc;
73 }
74
75 /* Check if this double word is erased and value isn't 0.
76 *
77 * It is allowed to write only zeros over an already written dword
78 * See 3.3.8 in reference manual.
79 */
80 if ((flash[0] != 0xFFFFFFFFUL ||
81 flash[1] != 0xFFFFFFFFUL) && val != 0UL) {
82 LOG_ERR("Word at offs %ld not erased", (long)offset);
83 return -EIO;
84 }
85
86 /* Set the PG bit */
87 regs->CR |= FLASH_CR_PG;
88
89 /* Flush the register write */
90 tmp = regs->CR;
91
92 /* Perform the data write operation at the desired memory address */
93 flash[0] = (uint32_t)val;
94 flash[1] = (uint32_t)(val >> 32);
95
96 /* Wait until the BSY bit is cleared */
97 rc = flash_stm32_wait_flash_idle(dev);
98
99 /* Clear the PG bit */
100 regs->CR &= (~FLASH_CR_PG);
101
102 return rc;
103 }
104
erase_page(const struct device * dev,unsigned int offset)105 static int erase_page(const struct device *dev, unsigned int offset)
106 {
107 FLASH_TypeDef *regs = FLASH_STM32_REGS(dev);
108 uint32_t tmp;
109 int rc;
110 int page;
111
112 /* if the control register is locked, do not fail silently */
113 if (regs->CR & FLASH_CR_LOCK) {
114 return -EIO;
115 }
116
117 /* Check that no Flash memory operation is ongoing */
118 rc = flash_stm32_wait_flash_idle(dev);
119 if (rc < 0) {
120 return rc;
121 }
122
123 /*
124 * If an erase operation in Flash memory also concerns data
125 * in the instruction cache, the user has to ensure that these data
126 * are rewritten before they are accessed during code execution.
127 */
128 flush_cache(regs);
129
130 tmp = regs->CR;
131 page = offset / STM32G0_FLASH_PAGE_SIZE;
132
133 #if defined(STM32G0_DBANK_SUPPORT)
134 bool swap_enabled = (regs->OPTR & FLASH_OPTR_nSWAP_BANK) == 0;
135
136 /* big page-nr w/o swap or small page-nr w/ swap indicate bank2 */
137 if ((page >= STM32G0_PAGES_PER_BANK) != swap_enabled) {
138 page = (page % STM32G0_PAGES_PER_BANK) + STM32G0_BANK2_START_PAGE_NR;
139 tmp |= FLASH_CR_BKER;
140 LOG_DBG("Erase page %d on bank 2", page);
141 } else {
142 page = page % STM32G0_PAGES_PER_BANK;
143 tmp &= ~FLASH_CR_BKER;
144 LOG_DBG("Erase page %d on bank 1", page);
145 }
146 #endif
147
148 /* Set the PER bit and select the page you wish to erase */
149 tmp |= FLASH_CR_PER;
150 tmp &= ~FLASH_CR_PNB_Msk;
151 tmp |= ((page << FLASH_CR_PNB_Pos) & FLASH_CR_PNB_Msk);
152
153 /* Set the STRT bit and write the reg */
154 tmp |= FLASH_CR_STRT;
155 regs->CR = tmp;
156
157 /* Wait for the BSY bit */
158 rc = flash_stm32_wait_flash_idle(dev);
159
160 regs->CR &= ~FLASH_CR_PER;
161
162 return rc;
163 }
164
flash_stm32_block_erase_loop(const struct device * dev,unsigned int offset,unsigned int len)165 int flash_stm32_block_erase_loop(const struct device *dev,
166 unsigned int offset,
167 unsigned int len)
168 {
169 unsigned int addr = offset;
170 int rc = 0;
171
172 for (; addr <= offset + len - 1 ; addr += STM32G0_FLASH_PAGE_SIZE) {
173 rc = erase_page(dev, addr);
174 if (rc < 0) {
175 break;
176 }
177 }
178
179 return rc;
180 }
181
flash_stm32_write_range(const struct device * dev,unsigned int offset,const void * data,unsigned int len)182 int flash_stm32_write_range(const struct device *dev, unsigned int offset,
183 const void *data, unsigned int len)
184 {
185 int i, rc = 0;
186
187 for (i = 0; i < len; i += 8, offset += 8) {
188 rc = write_dword(dev, offset,
189 UNALIGNED_GET((const uint64_t *) data + (i >> 3)));
190 if (rc < 0) {
191 return rc;
192 }
193 }
194
195 return rc;
196 }
197
198 /*
199 * The address space is always continuous, even though a subset of G0 SoCs has
200 * two flash banks.
201 * Only the "physical" flash page-NRs are not continuous on those SoCs.
202 * As a result the page numbers used in the zephyr flash api differs
203 * from the "physical" flash page number.
204 * The first is equal to the address offset divided by the page size, while
205 * "physical" pages are numbered starting with 0 on bank1 and 256 on bank2.
206 * As a result only a single homogeneous flash page layout needs to be defined.
207 */
flash_stm32_page_layout(const struct device * dev,const struct flash_pages_layout ** layout,size_t * layout_size)208 void flash_stm32_page_layout(const struct device *dev,
209 const struct flash_pages_layout **layout,
210 size_t *layout_size)
211 {
212 static struct flash_pages_layout stm32g0_flash_layout = {
213 .pages_count = 0,
214 .pages_size = 0,
215 };
216
217 ARG_UNUSED(dev);
218
219 if (stm32g0_flash_layout.pages_count == 0) {
220 stm32g0_flash_layout.pages_count =
221 STM32G0_FLASH_SIZE / STM32G0_FLASH_PAGE_SIZE;
222 stm32g0_flash_layout.pages_size = STM32G0_FLASH_PAGE_SIZE;
223 }
224
225 *layout = &stm32g0_flash_layout;
226 *layout_size = 1;
227 }
228
229 /* Override weak function */
flash_stm32_check_configuration(void)230 int flash_stm32_check_configuration(void)
231 {
232 #if defined(STM32G0_DBANK_SUPPORT) && (CONFIG_FLASH_SIZE == 256)
233 /* Single bank mode not supported on dual bank SoCs with 256kiB flash */
234 if ((FLASH->OPTR & FLASH_OPTR_DUAL_BANK) == 0) {
235 LOG_ERR("Single bank configuration not supported by the driver");
236 return -ENOTSUP;
237 }
238 #endif
239 return 0;
240 }
241
