1 /*
2 * Copyright (c) 2021 STMicroelectronics
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #include <zephyr/kernel.h>
8 #include <zephyr/device.h>
9 #include <string.h>
10 #include <zephyr/drivers/flash.h>
11 #include <zephyr/init.h>
12 #include <soc.h>
13
14 #include "flash_stm32.h"
15
flash_stm32_valid_range(const struct device * dev,off_t offset,uint32_t len,bool write)16 bool flash_stm32_valid_range(const struct device *dev, off_t offset,
17 uint32_t len,
18 bool write)
19 {
20 ARG_UNUSED(write);
21
22 return flash_stm32_range_exists(dev, offset, len);
23 }
24
flush_cache(FLASH_TypeDef * regs)25 static inline void flush_cache(FLASH_TypeDef *regs)
26 {
27 /* If Data cache is enabled, disable Data cache, reset Data cache
28 * and then re-enable Data cache.
29 */
30 if (regs->ACR & FLASH_ACR_DCEN) {
31 regs->ACR &= ~FLASH_ACR_DCEN;
32 /* Datasheet: DCRST: Data cache reset
33 * This bit can be written only when the Data cache is disabled
34 */
35 regs->ACR |= FLASH_ACR_DCRST;
36 regs->ACR &= ~FLASH_ACR_DCRST;
37 regs->ACR |= FLASH_ACR_DCEN;
38 }
39
40 /* If Instruction cache is enabled, disable Instruction cache, reset
41 * Instruction cache and then re-enable Instruction cache.
42 */
43 if (regs->ACR & FLASH_ACR_ICEN) {
44 regs->ACR &= ~FLASH_ACR_ICEN;
45 /* Datasheet: ICRST: Instruction cache reset
46 * This bit can be written only when the Instruction cache
47 * is disabled
48 */
49 regs->ACR |= FLASH_ACR_ICRST;
50 regs->ACR &= ~FLASH_ACR_ICRST;
51 regs->ACR |= FLASH_ACR_ICEN;
52 }
53 }
54
write_byte(const struct device * dev,off_t offset,uint8_t val)55 static int write_byte(const struct device *dev, off_t offset, uint8_t val)
56 {
57 FLASH_TypeDef *regs = FLASH_STM32_REGS(dev);
58 uint32_t tmp;
59 int rc;
60
61 /* if the control register is locked, do not fail silently */
62 if (regs->CR & FLASH_CR_LOCK) {
63 return -EIO;
64 }
65
66 /* Check that no Flash main memory operation is ongoing */
67 rc = flash_stm32_wait_flash_idle(dev);
68 if (rc < 0) {
69 return rc;
70 }
71
72 regs->CR &= ~FLASH_CR_PSIZE;
73 regs->CR |= FLASH_PSIZE_BYTE;
74 regs->CR |= FLASH_CR_PG;
75
76 /* flush the register write */
77 tmp = regs->CR;
78
79 *((uint8_t *) offset + FLASH_STM32_BASE_ADDRESS) = val;
80
81 /* Wait until the BSY bit is cleared */
82 rc = flash_stm32_wait_flash_idle(dev);
83
84 /* Clear the PG bit */
85 regs->CR &= (~FLASH_CR_PG);
86
87 return rc;
88 }
89
erase_sector(const struct device * dev,uint32_t sector)90 static int erase_sector(const struct device *dev, uint32_t sector)
91 {
92 FLASH_TypeDef *regs = FLASH_STM32_REGS(dev);
93 uint32_t tmp;
94 int rc;
95
96 /* if the control register is locked, do not fail silently */
97 if (regs->CR & FLASH_CR_LOCK) {
98 return -EIO;
99 }
100
101 /* Check that no Flash memory operation is ongoing */
102 rc = flash_stm32_wait_flash_idle(dev);
103 if (rc < 0) {
104 return rc;
105 }
106
107 regs->CR &= ~FLASH_CR_SNB;
108 regs->CR |= FLASH_CR_SER | (sector << 3);
109 regs->CR |= FLASH_CR_STRT;
110
111 /* flush the register write */
112 tmp = regs->CR;
113
114 /* Wait for the BSY bit */
115 rc = flash_stm32_wait_flash_idle(dev);
116
117 flush_cache(regs);
118
119 regs->CR &= ~(FLASH_CR_SER | FLASH_CR_SNB);
120
121 return rc;
122 }
123
flash_stm32_block_erase_loop(const struct device * dev,unsigned int offset,unsigned int len)124 int flash_stm32_block_erase_loop(const struct device *dev,
125 unsigned int offset,
126 unsigned int len)
127 {
128 struct flash_pages_info info;
129 uint32_t start_sector, end_sector;
130 uint32_t i;
131 int rc = 0;
132
133 rc = flash_get_page_info_by_offs(dev, offset, &info);
134 if (rc) {
135 return rc;
136 }
137 start_sector = info.index;
138 rc = flash_get_page_info_by_offs(dev, offset + len - 1, &info);
139 if (rc) {
140 return rc;
141 }
142 end_sector = info.index;
143
144 for (i = start_sector; i <= end_sector; i++) {
145 rc = erase_sector(dev, i);
146 if (rc < 0) {
147 break;
148 }
149 }
150
151 return rc;
152 }
153
flash_stm32_write_range(const struct device * dev,unsigned int offset,const void * data,unsigned int len)154 int flash_stm32_write_range(const struct device *dev, unsigned int offset,
155 const void *data, unsigned int len)
156 {
157 int i, rc = 0;
158
159 for (i = 0; i < len; i++, offset++) {
160 rc = write_byte(dev, offset, ((const uint8_t *) data)[i]);
161 if (rc < 0) {
162 return rc;
163 }
164 }
165
166 return rc;
167 }
168
169 /*
170 * The flash memory in stm32f2 series has bank 1 only with 12 sectors,
171 * they are split as 4 sectors of 16 Kbytes, 1 sector of 64 Kbytes,
172 * and 7 sectors of 128 Kbytes.
173 */
174 #ifndef FLASH_SECTOR_TOTAL
175 #error "Unknown flash layout"
176 #else /* defined(FLASH_SECTOR_TOTAL) */
177 #if FLASH_SECTOR_TOTAL == 12
178 static const struct flash_pages_layout stm32f2_flash_layout[] = {
179 /*
180 * PM0059, table 10: STM32F207xx
181 */
182 {.pages_count = 4, .pages_size = KB(16)},
183 {.pages_count = 1, .pages_size = KB(64)},
184 {.pages_count = 7, .pages_size = KB(128)},
185 };
186 #else
187 #error "Unknown flash layout"
188 #endif /* FLASH_SECTOR_TOTAL == 12 */
189 #endif/* !defined(FLASH_SECTOR_TOTAL) */
190
flash_stm32_page_layout(const struct device * dev,const struct flash_pages_layout ** layout,size_t * layout_size)191 void flash_stm32_page_layout(const struct device *dev,
192 const struct flash_pages_layout **layout,
193 size_t *layout_size)
194 {
195 ARG_UNUSED(dev);
196
197 *layout = stm32f2_flash_layout;
198 *layout_size = ARRAY_SIZE(stm32f2_flash_layout);
199 }
200
