1 /*
2 * Copyright (c) 2022 STMicroelectronics
3 * Copyright (c) 2022 Georgij Cernysiov
4 *
5 * SPDX-License-Identifier: Apache-2.0
6 */
7
8 #define DT_DRV_COMPAT st_stm32_ospi_nor
9
10 #include <errno.h>
11 #include <zephyr/kernel.h>
12 #include <zephyr/toolchain.h>
13 #include <zephyr/arch/common/ffs.h>
14 #include <zephyr/sys/util.h>
15 #include <soc.h>
16 #include <zephyr/drivers/pinctrl.h>
17 #include <zephyr/drivers/clock_control/stm32_clock_control.h>
18 #include <zephyr/drivers/clock_control.h>
19 #include <zephyr/drivers/flash.h>
20 #include <zephyr/dt-bindings/flash_controller/ospi.h>
21 #include <zephyr/drivers/gpio.h>
22 #include <zephyr/irq.h>
23
24 #include "spi_nor.h"
25 #include "jesd216.h"
26
27 #include "flash_stm32_ospi.h"
28
29 #include <zephyr/logging/log.h>
30 LOG_MODULE_REGISTER(flash_stm32_ospi, CONFIG_FLASH_LOG_LEVEL);
31
32 #define STM32_OSPI_NODE DT_INST_PARENT(0)
33
34 #define DT_OSPI_IO_PORT_PROP_OR(prop, default_value) \
35 COND_CODE_1(DT_NODE_HAS_PROP(STM32_OSPI_NODE, prop), \
36 (_CONCAT(HAL_OSPIM_, DT_STRING_TOKEN(STM32_OSPI_NODE, prop))), \
37 ((default_value)))
38
39 /* Get the base address of the flash from the DTS node */
40 #define STM32_OSPI_BASE_ADDRESS DT_INST_REG_ADDR(0)
41
42 #define STM32_OSPI_RESET_GPIO DT_INST_NODE_HAS_PROP(0, reset_gpios)
43
44 #define STM32_OSPI_DLYB_BYPASSED DT_PROP(STM32_OSPI_NODE, dlyb_bypass)
45
46 #define STM32_OSPI_USE_DMA DT_NODE_HAS_PROP(STM32_OSPI_NODE, dmas)
47
48 #if STM32_OSPI_USE_DMA
49 #include <zephyr/drivers/dma/dma_stm32.h>
50 #include <zephyr/drivers/dma.h>
51 #include <stm32_ll_dma.h>
52 #endif /* STM32_OSPI_USE_DMA */
53
54 #define STM32_OSPI_FIFO_THRESHOLD 4
55
56 #if defined(CONFIG_SOC_SERIES_STM32H5X)
57 /* Valid range is [0, 255] */
58 #define STM32_OSPI_CLOCK_PRESCALER_MIN 0U
59 #define STM32_OSPI_CLOCK_PRESCALER_MAX 255U
60 #define STM32_OSPI_CLOCK_COMPUTE(bus_freq, prescaler) ((bus_freq) / ((prescaler) + 1U))
61 #else
62 /* Valid range is [1, 256] */
63 #define STM32_OSPI_CLOCK_PRESCALER_MIN 1U
64 #define STM32_OSPI_CLOCK_PRESCALER_MAX 256U
65 #define STM32_OSPI_CLOCK_COMPUTE(bus_freq, prescaler) ((bus_freq) / (prescaler))
66 #endif
67
68 /* Max Time value during reset or erase operation */
69 #define STM32_OSPI_RESET_MAX_TIME 100U
70 #define STM32_OSPI_BULK_ERASE_MAX_TIME 460000U
71 #define STM32_OSPI_SECTOR_ERASE_MAX_TIME 1000U
72 #define STM32_OSPI_SUBSECTOR_4K_ERASE_MAX_TIME 400U
73 #define STM32_OSPI_WRITE_REG_MAX_TIME 40U
74
75 /* used as default value for DTS writeoc */
76 #define SPI_NOR_WRITEOC_NONE 0xFF
77
78 #if STM32_OSPI_USE_DMA
79 #if CONFIG_DMA_STM32U5
80 static const uint32_t table_src_size[] = {
81 LL_DMA_SRC_DATAWIDTH_BYTE,
82 LL_DMA_SRC_DATAWIDTH_HALFWORD,
83 LL_DMA_SRC_DATAWIDTH_WORD,
84 };
85
86 static const uint32_t table_dest_size[] = {
87 LL_DMA_DEST_DATAWIDTH_BYTE,
88 LL_DMA_DEST_DATAWIDTH_HALFWORD,
89 LL_DMA_DEST_DATAWIDTH_WORD,
90 };
91
92 /* Lookup table to set dma priority from the DTS */
93 static const uint32_t table_priority[] = {
94 LL_DMA_LOW_PRIORITY_LOW_WEIGHT,
95 LL_DMA_LOW_PRIORITY_MID_WEIGHT,
96 LL_DMA_LOW_PRIORITY_HIGH_WEIGHT,
97 LL_DMA_HIGH_PRIORITY,
98 };
99 #else
100 static const uint32_t table_m_size[] = {
101 LL_DMA_MDATAALIGN_BYTE,
102 LL_DMA_MDATAALIGN_HALFWORD,
103 LL_DMA_MDATAALIGN_WORD,
104 };
105
106 static const uint32_t table_p_size[] = {
107 LL_DMA_PDATAALIGN_BYTE,
108 LL_DMA_PDATAALIGN_HALFWORD,
109 LL_DMA_PDATAALIGN_WORD,
110 };
111
112 /* Lookup table to set dma priority from the DTS */
113 static const uint32_t table_priority[] = {
114 DMA_PRIORITY_LOW,
115 DMA_PRIORITY_MEDIUM,
116 DMA_PRIORITY_HIGH,
117 DMA_PRIORITY_VERY_HIGH,
118 };
119 #endif /* CONFIG_DMA_STM32U5 */
120
121 struct stream {
122 DMA_TypeDef *reg;
123 const struct device *dev;
124 uint32_t channel;
125 struct dma_config cfg;
126 };
127 #endif /* STM32_OSPI_USE_DMA */
128
129 typedef void (*irq_config_func_t)(const struct device *dev);
130
131 struct flash_stm32_ospi_config {
132 OCTOSPI_TypeDef *regs;
133 const struct stm32_pclken pclken; /* clock subsystem */
134 #if DT_CLOCKS_HAS_NAME(STM32_OSPI_NODE, ospi_ker)
135 const struct stm32_pclken pclken_ker; /* clock subsystem */
136 #endif
137 #if DT_CLOCKS_HAS_NAME(STM32_OSPI_NODE, ospi_mgr)
138 const struct stm32_pclken pclken_mgr; /* clock subsystem */
139 #endif
140 irq_config_func_t irq_config;
141 size_t flash_size;
142 uint32_t max_frequency;
143 int data_mode; /* SPI or QSPI or OSPI */
144 int data_rate; /* DTR or STR */
145 const struct pinctrl_dev_config *pcfg;
146 #if STM32_OSPI_RESET_GPIO
147 const struct gpio_dt_spec reset;
148 #endif /* STM32_OSPI_RESET_GPIO */
149 #if DT_NODE_HAS_PROP(DT_INST(0, st_stm32_ospi_nor), sfdp_bfp)
150 uint8_t sfdp_bfp[DT_INST_PROP_LEN(0, sfdp_bfp)];
151 #endif /* sfdp_bfp */
152 };
153
154 struct flash_stm32_ospi_data {
155 OSPI_HandleTypeDef hospi;
156 struct k_sem sem;
157 struct k_sem sync;
158 #if defined(CONFIG_FLASH_PAGE_LAYOUT)
159 struct flash_pages_layout layout;
160 #endif
161 struct jesd216_erase_type erase_types[JESD216_NUM_ERASE_TYPES];
162 /* Number of bytes per page */
163 uint16_t page_size;
164 /* Address width in bytes */
165 uint8_t address_width;
166 /* Read operation dummy cycles */
167 uint8_t read_dummy;
168 uint32_t read_opcode;
169 uint32_t write_opcode;
170 enum jesd216_mode_type read_mode;
171 enum jesd216_dw15_qer_type qer_type;
172 #if defined(CONFIG_FLASH_JESD216_API)
173 /* Table to hold the jedec Read ID given by the octoFlash or the DTS */
174 uint8_t jedec_id[JESD216_READ_ID_LEN];
175 #endif /* CONFIG_FLASH_JESD216_API */
176 int cmd_status;
177 #if STM32_OSPI_USE_DMA
178 struct stream dma;
179 #endif /* STM32_OSPI_USE_DMA */
180 };
181
ospi_lock_thread(const struct device * dev)182 static inline void ospi_lock_thread(const struct device *dev)
183 {
184 struct flash_stm32_ospi_data *dev_data = dev->data;
185
186 k_sem_take(&dev_data->sem, K_FOREVER);
187 }
188
ospi_unlock_thread(const struct device * dev)189 static inline void ospi_unlock_thread(const struct device *dev)
190 {
191 struct flash_stm32_ospi_data *dev_data = dev->data;
192
193 k_sem_give(&dev_data->sem);
194 }
195
ospi_send_cmd(const struct device * dev,OSPI_RegularCmdTypeDef * cmd)196 static int ospi_send_cmd(const struct device *dev, OSPI_RegularCmdTypeDef *cmd)
197 {
198 const struct flash_stm32_ospi_config *dev_cfg = dev->config;
199 struct flash_stm32_ospi_data *dev_data = dev->data;
200 HAL_StatusTypeDef hal_ret;
201
202 LOG_DBG("Instruction 0x%x", cmd->Instruction);
203
204 dev_data->cmd_status = 0;
205
206 hal_ret = HAL_OSPI_Command(&dev_data->hospi, cmd, HAL_OSPI_TIMEOUT_DEFAULT_VALUE);
207 if (hal_ret != HAL_OK) {
208 LOG_ERR("%d: Failed to send OSPI instruction", hal_ret);
209 return -EIO;
210 }
211 LOG_DBG("CCR 0x%x", dev_cfg->regs->CCR);
212
213 return dev_data->cmd_status;
214 }
215
ospi_read_access(const struct device * dev,OSPI_RegularCmdTypeDef * cmd,uint8_t * data,size_t size)216 static int ospi_read_access(const struct device *dev, OSPI_RegularCmdTypeDef *cmd,
217 uint8_t *data, size_t size)
218 {
219 struct flash_stm32_ospi_data *dev_data = dev->data;
220 HAL_StatusTypeDef hal_ret;
221
222 LOG_DBG("Instruction 0x%x", cmd->Instruction);
223
224 cmd->NbData = size;
225
226 dev_data->cmd_status = 0;
227
228 hal_ret = HAL_OSPI_Command(&dev_data->hospi, cmd, HAL_OSPI_TIMEOUT_DEFAULT_VALUE);
229 if (hal_ret != HAL_OK) {
230 LOG_ERR("%d: Failed to send OSPI instruction", hal_ret);
231 return -EIO;
232 }
233
234 #if STM32_OSPI_USE_DMA
235 hal_ret = HAL_OSPI_Receive_DMA(&dev_data->hospi, data);
236 #else
237 hal_ret = HAL_OSPI_Receive_IT(&dev_data->hospi, data);
238 #endif
239 if (hal_ret != HAL_OK) {
240 LOG_ERR("%d: Failed to read data", hal_ret);
241 return -EIO;
242 }
243
244 k_sem_take(&dev_data->sync, K_FOREVER);
245
246 return dev_data->cmd_status;
247 }
248
ospi_write_access(const struct device * dev,OSPI_RegularCmdTypeDef * cmd,const uint8_t * data,size_t size)249 static int ospi_write_access(const struct device *dev, OSPI_RegularCmdTypeDef *cmd,
250 const uint8_t *data, size_t size)
251 {
252 const struct flash_stm32_ospi_config *dev_cfg = dev->config;
253 struct flash_stm32_ospi_data *dev_data = dev->data;
254 HAL_StatusTypeDef hal_ret;
255
256 LOG_DBG("Instruction 0x%x", cmd->Instruction);
257
258 cmd->NbData = size;
259
260 dev_data->cmd_status = 0;
261
262 /* in OPI/STR the 3-byte AddressSize is not supported by the NOR flash */
263 if ((dev_cfg->data_mode == OSPI_OPI_MODE) &&
264 (cmd->AddressSize != HAL_OSPI_ADDRESS_32_BITS)) {
265 LOG_ERR("OSPI wr in OPI/STR mode is for 32bit address only");
266 return -EIO;
267 }
268
269 hal_ret = HAL_OSPI_Command(&dev_data->hospi, cmd, HAL_OSPI_TIMEOUT_DEFAULT_VALUE);
270 if (hal_ret != HAL_OK) {
271 LOG_ERR("%d: Failed to send OSPI instruction", hal_ret);
272 return -EIO;
273 }
274
275 #if STM32_OSPI_USE_DMA
276 hal_ret = HAL_OSPI_Transmit_DMA(&dev_data->hospi, (uint8_t *)data);
277 #else
278 hal_ret = HAL_OSPI_Transmit_IT(&dev_data->hospi, (uint8_t *)data);
279 #endif
280
281 if (hal_ret != HAL_OK) {
282 LOG_ERR("%d: Failed to write data", hal_ret);
283 return -EIO;
284 }
285
286 k_sem_take(&dev_data->sync, K_FOREVER);
287
288 return dev_data->cmd_status;
289 }
290
291 /*
292 * Gives a OSPI_RegularCmdTypeDef with all parameters set
293 * except Instruction, Address, DummyCycles, NbData
294 */
ospi_prepare_cmd(uint8_t transfer_mode,uint8_t transfer_rate)295 static OSPI_RegularCmdTypeDef ospi_prepare_cmd(uint8_t transfer_mode, uint8_t transfer_rate)
296 {
297 OSPI_RegularCmdTypeDef cmd_tmp = {
298 .OperationType = HAL_OSPI_OPTYPE_COMMON_CFG,
299 .FlashId = HAL_OSPI_FLASH_ID_1,
300 .InstructionSize = ((transfer_mode == OSPI_OPI_MODE)
301 ? HAL_OSPI_INSTRUCTION_16_BITS
302 : HAL_OSPI_INSTRUCTION_8_BITS),
303 .InstructionDtrMode = ((transfer_rate == OSPI_DTR_TRANSFER)
304 ? HAL_OSPI_INSTRUCTION_DTR_ENABLE
305 : HAL_OSPI_INSTRUCTION_DTR_DISABLE),
306 .AddressDtrMode = ((transfer_rate == OSPI_DTR_TRANSFER)
307 ? HAL_OSPI_ADDRESS_DTR_ENABLE
308 : HAL_OSPI_ADDRESS_DTR_DISABLE),
309 /* AddressSize must be set to 32bits for init and mem config phase */
310 .AddressSize = HAL_OSPI_ADDRESS_32_BITS,
311 .AlternateBytesMode = HAL_OSPI_ALTERNATE_BYTES_NONE,
312 .DataDtrMode = ((transfer_rate == OSPI_DTR_TRANSFER)
313 ? HAL_OSPI_DATA_DTR_ENABLE
314 : HAL_OSPI_DATA_DTR_DISABLE),
315 .DQSMode = (transfer_rate == OSPI_DTR_TRANSFER)
316 ? HAL_OSPI_DQS_ENABLE
317 : HAL_OSPI_DQS_DISABLE,
318 .SIOOMode = HAL_OSPI_SIOO_INST_EVERY_CMD,
319 };
320
321 switch (transfer_mode) {
322 case OSPI_OPI_MODE: {
323 cmd_tmp.InstructionMode = HAL_OSPI_INSTRUCTION_8_LINES;
324 cmd_tmp.AddressMode = HAL_OSPI_ADDRESS_8_LINES;
325 cmd_tmp.DataMode = HAL_OSPI_DATA_8_LINES;
326 break;
327 }
328 case OSPI_QUAD_MODE: {
329 cmd_tmp.InstructionMode = HAL_OSPI_INSTRUCTION_4_LINES;
330 cmd_tmp.AddressMode = HAL_OSPI_ADDRESS_4_LINES;
331 cmd_tmp.DataMode = HAL_OSPI_DATA_4_LINES;
332 break;
333 }
334 case OSPI_DUAL_MODE: {
335 cmd_tmp.InstructionMode = HAL_OSPI_INSTRUCTION_2_LINES;
336 cmd_tmp.AddressMode = HAL_OSPI_ADDRESS_2_LINES;
337 cmd_tmp.DataMode = HAL_OSPI_DATA_2_LINES;
338 break;
339 }
340 default: {
341 cmd_tmp.InstructionMode = HAL_OSPI_INSTRUCTION_1_LINE;
342 cmd_tmp.AddressMode = HAL_OSPI_ADDRESS_1_LINE;
343 cmd_tmp.DataMode = HAL_OSPI_DATA_1_LINE;
344 break;
345 }
346 }
347
348 return cmd_tmp;
349 }
350
stm32_ospi_hal_address_size(const struct device * dev)351 static uint32_t stm32_ospi_hal_address_size(const struct device *dev)
352 {
353 struct flash_stm32_ospi_data *dev_data = dev->data;
354
355 if (dev_data->address_width == 4U) {
356 return HAL_OSPI_ADDRESS_32_BITS;
357 }
358
359 return HAL_OSPI_ADDRESS_24_BITS;
360 }
361
362 #if defined(CONFIG_FLASH_JESD216_API)
363 /*
364 * Read the JEDEC ID data from the octoFlash at init or DTS
365 * and store in the jedec_id Table of the flash_stm32_ospi_data
366 */
stm32_ospi_read_jedec_id(const struct device * dev)367 static int stm32_ospi_read_jedec_id(const struct device *dev)
368 {
369 struct flash_stm32_ospi_data *dev_data = dev->data;
370
371 #if DT_NODE_HAS_PROP(DT_INST(0, st_stm32_ospi_nor), jedec_id)
372 /* If DTS has the jedec_id property, check its length */
373 if (DT_INST_PROP_LEN(0, jedec_id) != JESD216_READ_ID_LEN) {
374 LOG_ERR("Read ID length is wrong (%d)", DT_INST_PROP_LEN(0, jedec_id));
375 return -EIO;
376 }
377
378 /* The dev_data->jedec_id if filled from the DTS property */
379 #else
380 /* This is a SPI/STR command to issue to the octoFlash device */
381 OSPI_RegularCmdTypeDef cmd = ospi_prepare_cmd(OSPI_SPI_MODE, OSPI_STR_TRANSFER);
382
383 cmd.Instruction = JESD216_CMD_READ_ID;
384 cmd.AddressSize = stm32_ospi_hal_address_size(dev);
385 cmd.AddressMode = HAL_OSPI_ADDRESS_NONE;
386 cmd.NbData = JESD216_READ_ID_LEN; /* 3 bytes in the READ ID */
387
388 HAL_StatusTypeDef hal_ret;
389
390 hal_ret = HAL_OSPI_Command(&dev_data->hospi, &cmd,
391 HAL_OSPI_TIMEOUT_DEFAULT_VALUE);
392
393 if (hal_ret != HAL_OK) {
394 LOG_ERR("%d: Failed to send OSPI instruction", hal_ret);
395 return -EIO;
396 }
397
398 /* Place the received data directly into the jedec Table */
399 hal_ret = HAL_OSPI_Receive(&dev_data->hospi, dev_data->jedec_id,
400 HAL_OSPI_TIMEOUT_DEFAULT_VALUE);
401 if (hal_ret != HAL_OK) {
402 LOG_ERR("%d: Failed to read data", hal_ret);
403 return -EIO;
404 }
405 #endif /* jedec_id */
406 LOG_DBG("Jedec ID = [%02x %02x %02x]",
407 dev_data->jedec_id[0], dev_data->jedec_id[1], dev_data->jedec_id[2]);
408
409 dev_data->cmd_status = 0;
410
411 return 0;
412 }
413
414 /*
415 * Read Serial Flash ID :
416 * just gives the values received by the octoFlash or from the DTS
417 */
ospi_read_jedec_id(const struct device * dev,uint8_t * id)418 static int ospi_read_jedec_id(const struct device *dev, uint8_t *id)
419 {
420 struct flash_stm32_ospi_data *dev_data = dev->data;
421
422 /* Take jedec Id values from the table (issued from the octoFlash) */
423 memcpy(id, dev_data->jedec_id, JESD216_READ_ID_LEN);
424
425 LOG_INF("Manuf ID = %02x Memory Type = %02x Memory Density = %02x",
426 id[0], id[1], id[2]);
427
428 return 0;
429 }
430 #endif /* CONFIG_FLASH_JESD216_API */
431
432 #if !DT_NODE_HAS_PROP(DT_INST(0, st_stm32_ospi_nor), sfdp_bfp)
433 /*
434 * Read Serial Flash Discovery Parameter from the octoFlash at init :
435 * perform a read access over SPI bus for SDFP (DataMode is already set)
436 */
stm32_ospi_read_sfdp(const struct device * dev,off_t addr,void * data,size_t size)437 static int stm32_ospi_read_sfdp(const struct device *dev, off_t addr,
438 void *data,
439 size_t size)
440 {
441 const struct flash_stm32_ospi_config *dev_cfg = dev->config;
442 struct flash_stm32_ospi_data *dev_data = dev->data;
443
444 OSPI_RegularCmdTypeDef cmd = ospi_prepare_cmd(dev_cfg->data_mode,
445 dev_cfg->data_rate);
446 if (dev_cfg->data_mode == OSPI_OPI_MODE) {
447 cmd.Instruction = JESD216_OCMD_READ_SFDP;
448 cmd.DummyCycles = 20U;
449 cmd.AddressSize = HAL_OSPI_ADDRESS_32_BITS;
450 } else {
451 cmd.Instruction = JESD216_CMD_READ_SFDP;
452 cmd.InstructionMode = HAL_OSPI_INSTRUCTION_1_LINE;
453 cmd.DataMode = HAL_OSPI_DATA_1_LINE;
454 cmd.AddressMode = HAL_OSPI_ADDRESS_1_LINE;
455 cmd.DummyCycles = 8U;
456 cmd.AddressSize = HAL_OSPI_ADDRESS_24_BITS;
457 }
458 cmd.Address = addr;
459 cmd.NbData = size;
460
461 HAL_StatusTypeDef hal_ret;
462
463 hal_ret = HAL_OSPI_Command(&dev_data->hospi, &cmd, HAL_OSPI_TIMEOUT_DEFAULT_VALUE);
464 if (hal_ret != HAL_OK) {
465 LOG_ERR("%d: Failed to send OSPI instruction", hal_ret);
466 return -EIO;
467 }
468
469 hal_ret = HAL_OSPI_Receive(&dev_data->hospi, (uint8_t *)data,
470 HAL_OSPI_TIMEOUT_DEFAULT_VALUE);
471 if (hal_ret != HAL_OK) {
472 LOG_ERR("%d: Failed to read data", hal_ret);
473 return -EIO;
474 }
475
476 dev_data->cmd_status = 0;
477
478 return 0;
479 }
480 #endif /* ! sfdp_bfp */
481
482 /*
483 * Read Serial Flash Discovery Parameter :
484 * perform a read access over SPI bus for SDFP (DataMode is already set)
485 * or get it from the sdfp table (in the DTS)
486 */
ospi_read_sfdp(const struct device * dev,off_t addr,void * data,size_t size)487 static int ospi_read_sfdp(const struct device *dev, off_t addr, void *data,
488 size_t size)
489 {
490 #if DT_NODE_HAS_PROP(DT_INST(0, st_stm32_ospi_nor), sfdp_bfp)
491 /* There is a sfdp-bfp property in the deviceTree : do not read the flash */
492 const struct flash_stm32_ospi_config *dev_cfg = dev->config;
493
494 LOG_INF("Read SFDP from DTS property");
495 /* If DTS has the sdfp table property, check its length */
496 if (size > DT_INST_PROP_LEN(0, sfdp_bfp)) {
497 LOG_ERR("SDFP bdfp length is wrong (%d)", DT_INST_PROP_LEN(0, sfdp_bfp));
498 return -EIO;
499 }
500 /* The dev_cfg->sfdp_bfp if filled from the DTS property */
501 memcpy(data, dev_cfg->sfdp_bfp + addr, size);
502
503 return 0;
504 #else
505 LOG_INF("Read SFDP from octoFlash");
506 /* Get the SFDP from the octoFlash (no sfdp-bfp table in the DeviceTree) */
507 if (stm32_ospi_read_sfdp(dev, addr, data, size) == 0) {
508 /* If valid, then ignore any table from the DTS */
509 return 0;
510 }
511 LOG_INF("Error reading SFDP from octoFlash and none in the DTS");
512 return -EINVAL;
513 #endif /* sfdp_bfp */
514 }
515
ospi_address_is_valid(const struct device * dev,off_t addr,size_t size)516 static bool ospi_address_is_valid(const struct device *dev, off_t addr,
517 size_t size)
518 {
519 const struct flash_stm32_ospi_config *dev_cfg = dev->config;
520 size_t flash_size = dev_cfg->flash_size;
521
522 return (addr >= 0) && ((uint64_t)addr + (uint64_t)size <= flash_size);
523 }
524
525 /*
526 * This function Polls the WEL (write enable latch) bit to become to 0
527 * When the Chip Erase Cycle is completed, the Write Enable Latch (WEL) bit is cleared.
528 * in nor_mode SPI/OPI OSPI_SPI_MODE or OSPI_OPI_MODE
529 * and nor_rate transfer STR/DTR OSPI_STR_TRANSFER or OSPI_DTR_TRANSFER
530 */
stm32_ospi_mem_erased(OSPI_HandleTypeDef * hospi,uint8_t nor_mode,uint8_t nor_rate)531 static int stm32_ospi_mem_erased(OSPI_HandleTypeDef *hospi, uint8_t nor_mode, uint8_t nor_rate)
532 {
533 OSPI_AutoPollingTypeDef s_config = {0};
534 OSPI_RegularCmdTypeDef s_command = ospi_prepare_cmd(nor_mode, nor_rate);
535
536 /* Configure automatic polling mode command to wait for memory ready */
537 if (nor_mode == OSPI_OPI_MODE) {
538 s_command.Instruction = SPI_NOR_OCMD_RDSR;
539 s_command.DummyCycles = (nor_rate == OSPI_DTR_TRANSFER)
540 ? SPI_NOR_DUMMY_REG_OCTAL_DTR
541 : SPI_NOR_DUMMY_REG_OCTAL;
542 } else {
543 s_command.Instruction = SPI_NOR_CMD_RDSR;
544 /* force 1-line InstructionMode for any non-OSPI transfer */
545 s_command.InstructionMode = HAL_OSPI_INSTRUCTION_1_LINE;
546 s_command.AddressMode = HAL_OSPI_ADDRESS_NONE;
547 /* force 1-line DataMode for any non-OSPI transfer */
548 s_command.DataMode = HAL_OSPI_DATA_1_LINE;
549 s_command.DummyCycles = 0;
550 }
551 s_command.NbData = ((nor_rate == OSPI_DTR_TRANSFER) ? 2U : 1U);
552 s_command.Address = 0U;
553
554 /* Set the mask to 0x02 to mask all Status REG bits except WEL */
555 /* Set the match to 0x00 to check if the WEL bit is Reset */
556 s_config.Match = SPI_NOR_WEL_MATCH;
557 s_config.Mask = SPI_NOR_WEL_MASK; /* Write Enable Latch */
558
559 s_config.MatchMode = HAL_OSPI_MATCH_MODE_AND;
560 s_config.Interval = SPI_NOR_AUTO_POLLING_INTERVAL;
561 s_config.AutomaticStop = HAL_OSPI_AUTOMATIC_STOP_ENABLE;
562
563 if (HAL_OSPI_Command(hospi, &s_command, HAL_OSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) {
564 LOG_ERR("OSPI AutoPoll command (WEL) failed");
565 return -EIO;
566 }
567
568 /* Start Automatic-Polling mode to wait until the memory is totally erased */
569 if (HAL_OSPI_AutoPolling(hospi, &s_config, STM32_OSPI_BULK_ERASE_MAX_TIME) != HAL_OK) {
570 LOG_ERR("OSPI AutoPoll (WEL) failed");
571 return -EIO;
572 }
573
574 return 0;
575 }
576
577 /*
578 * This function Polls the WIP(Write In Progress) bit to become to 0
579 * in nor_mode SPI/OPI OSPI_SPI_MODE or OSPI_OPI_MODE
580 * and nor_rate transfer STR/DTR OSPI_STR_TRANSFER or OSPI_DTR_TRANSFER
581 */
stm32_ospi_mem_ready(OSPI_HandleTypeDef * hospi,uint8_t nor_mode,uint8_t nor_rate)582 static int stm32_ospi_mem_ready(OSPI_HandleTypeDef *hospi, uint8_t nor_mode, uint8_t nor_rate)
583 {
584 OSPI_AutoPollingTypeDef s_config = {0};
585 OSPI_RegularCmdTypeDef s_command = ospi_prepare_cmd(nor_mode, nor_rate);
586
587 /* Configure automatic polling mode command to wait for memory ready */
588 if (nor_mode == OSPI_OPI_MODE) {
589 s_command.Instruction = SPI_NOR_OCMD_RDSR;
590 s_command.DummyCycles = (nor_rate == OSPI_DTR_TRANSFER)
591 ? SPI_NOR_DUMMY_REG_OCTAL_DTR
592 : SPI_NOR_DUMMY_REG_OCTAL;
593 } else {
594 s_command.Instruction = SPI_NOR_CMD_RDSR;
595 /* force 1-line InstructionMode for any non-OSPI transfer */
596 s_command.InstructionMode = HAL_OSPI_INSTRUCTION_1_LINE;
597 s_command.AddressMode = HAL_OSPI_ADDRESS_NONE;
598 /* force 1-line DataMode for any non-OSPI transfer */
599 s_command.DataMode = HAL_OSPI_DATA_1_LINE;
600 s_command.DummyCycles = 0;
601 }
602 s_command.NbData = ((nor_rate == OSPI_DTR_TRANSFER) ? 2U : 1U);
603 s_command.Address = 0U;
604
605 /* Set the mask to 0x01 to mask all Status REG bits except WIP */
606 /* Set the match to 0x00 to check if the WIP bit is Reset */
607 s_config.Match = SPI_NOR_MEM_RDY_MATCH;
608 s_config.Mask = SPI_NOR_MEM_RDY_MASK; /* Write in progress */
609 s_config.MatchMode = HAL_OSPI_MATCH_MODE_AND;
610 s_config.Interval = SPI_NOR_AUTO_POLLING_INTERVAL;
611 s_config.AutomaticStop = HAL_OSPI_AUTOMATIC_STOP_ENABLE;
612
613 if (HAL_OSPI_Command(hospi, &s_command, HAL_OSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) {
614 LOG_ERR("OSPI AutoPoll command failed");
615 return -EIO;
616 }
617
618 /* Start Automatic-Polling mode to wait until the memory is ready WIP=0 */
619 if (HAL_OSPI_AutoPolling(hospi, &s_config, HAL_OSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) {
620 LOG_ERR("OSPI AutoPoll failed");
621 return -EIO;
622 }
623
624 return 0;
625 }
626
627 /* Enables writing to the memory sending a Write Enable and wait it is effective */
stm32_ospi_write_enable(OSPI_HandleTypeDef * hospi,uint8_t nor_mode,uint8_t nor_rate)628 static int stm32_ospi_write_enable(OSPI_HandleTypeDef *hospi, uint8_t nor_mode, uint8_t nor_rate)
629 {
630 OSPI_AutoPollingTypeDef s_config = {0};
631 OSPI_RegularCmdTypeDef s_command = ospi_prepare_cmd(nor_mode, nor_rate);
632
633 /* Initialize the write enable command */
634 if (nor_mode == OSPI_OPI_MODE) {
635 s_command.Instruction = SPI_NOR_OCMD_WREN;
636 } else {
637 s_command.Instruction = SPI_NOR_CMD_WREN;
638 /* force 1-line InstructionMode for any non-OSPI transfer */
639 s_command.InstructionMode = HAL_OSPI_INSTRUCTION_1_LINE;
640 }
641 s_command.AddressMode = HAL_OSPI_ADDRESS_NONE;
642 s_command.DataMode = HAL_OSPI_DATA_NONE;
643 s_command.DummyCycles = 0U;
644
645 if (HAL_OSPI_Command(hospi, &s_command, HAL_OSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) {
646 LOG_ERR("OSPI flash write enable cmd failed");
647 return -EIO;
648 }
649
650 /* New command to Configure automatic polling mode to wait for write enabling */
651 if (nor_mode == OSPI_OPI_MODE) {
652 s_command.Instruction = SPI_NOR_OCMD_RDSR;
653 s_command.AddressMode = HAL_OSPI_ADDRESS_8_LINES;
654 s_command.DataMode = HAL_OSPI_DATA_8_LINES;
655 s_command.DummyCycles = (nor_rate == OSPI_DTR_TRANSFER)
656 ? SPI_NOR_DUMMY_REG_OCTAL_DTR
657 : SPI_NOR_DUMMY_REG_OCTAL;
658 } else {
659 s_command.Instruction = SPI_NOR_CMD_RDSR;
660 /* force 1-line DataMode for any non-OSPI transfer */
661 s_command.InstructionMode = HAL_OSPI_INSTRUCTION_1_LINE;
662 s_command.AddressMode = HAL_OSPI_ADDRESS_1_LINE;
663 s_command.DataMode = HAL_OSPI_DATA_1_LINE;
664 s_command.DummyCycles = 0;
665
666 /* DummyCycles remains 0 */
667 }
668 s_command.NbData = (nor_rate == OSPI_DTR_TRANSFER) ? 2U : 1U;
669 s_command.Address = 0U;
670
671 if (HAL_OSPI_Command(hospi, &s_command, HAL_OSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) {
672 LOG_ERR("OSPI config auto polling cmd failed");
673 return -EIO;
674 }
675
676 s_config.Match = SPI_NOR_WREN_MATCH;
677 s_config.Mask = SPI_NOR_WREN_MASK;
678 s_config.MatchMode = HAL_OSPI_MATCH_MODE_AND;
679 s_config.Interval = SPI_NOR_AUTO_POLLING_INTERVAL;
680 s_config.AutomaticStop = HAL_OSPI_AUTOMATIC_STOP_ENABLE;
681
682 if (HAL_OSPI_AutoPolling(hospi, &s_config, HAL_OSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) {
683 LOG_ERR("OSPI config auto polling failed");
684 return -EIO;
685 }
686
687 return 0;
688 }
689
690 /* Write Flash configuration register 2 with new dummy cycles */
stm32_ospi_write_cfg2reg_dummy(OSPI_HandleTypeDef * hospi,uint8_t nor_mode,uint8_t nor_rate)691 static int stm32_ospi_write_cfg2reg_dummy(OSPI_HandleTypeDef *hospi,
692 uint8_t nor_mode, uint8_t nor_rate)
693 {
694 uint8_t transmit_data = SPI_NOR_CR2_DUMMY_CYCLES_66MHZ;
695 OSPI_RegularCmdTypeDef s_command = ospi_prepare_cmd(nor_mode, nor_rate);
696
697 /* Initialize the writing of configuration register 2 */
698 s_command.Instruction = (nor_mode == OSPI_SPI_MODE)
699 ? SPI_NOR_CMD_WR_CFGREG2
700 : SPI_NOR_OCMD_WR_CFGREG2;
701 s_command.Address = SPI_NOR_REG2_ADDR3;
702 s_command.DummyCycles = 0U;
703 s_command.NbData = (nor_mode == OSPI_SPI_MODE) ? 1U
704 : ((nor_rate == OSPI_DTR_TRANSFER) ? 2U : 1U);
705
706 if (HAL_OSPI_Command(hospi, &s_command,
707 HAL_OSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) {
708 LOG_ERR("OSPI transmit ");
709 return -EIO;
710 }
711
712 if (HAL_OSPI_Transmit(hospi, &transmit_data,
713 HAL_OSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) {
714 LOG_ERR("OSPI transmit ");
715 return -EIO;
716 }
717
718 return 0;
719 }
720
721 /* Write Flash configuration register 2 with new single or octal SPI protocol */
stm32_ospi_write_cfg2reg_io(OSPI_HandleTypeDef * hospi,uint8_t nor_mode,uint8_t nor_rate,uint8_t op_enable)722 static int stm32_ospi_write_cfg2reg_io(OSPI_HandleTypeDef *hospi,
723 uint8_t nor_mode, uint8_t nor_rate, uint8_t op_enable)
724 {
725 OSPI_RegularCmdTypeDef s_command = ospi_prepare_cmd(nor_mode, nor_rate);
726
727 /* Initialize the writing of configuration register 2 */
728 s_command.Instruction = (nor_mode == OSPI_SPI_MODE)
729 ? SPI_NOR_CMD_WR_CFGREG2
730 : SPI_NOR_OCMD_WR_CFGREG2;
731 s_command.Address = SPI_NOR_REG2_ADDR1;
732 s_command.DummyCycles = 0U;
733 s_command.NbData = (nor_mode == OSPI_SPI_MODE) ? 1U
734 : ((nor_rate == OSPI_DTR_TRANSFER) ? 2U : 1U);
735
736 if (HAL_OSPI_Command(hospi, &s_command,
737 HAL_OSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) {
738 LOG_ERR("Write Flash configuration reg2 failed");
739 return -EIO;
740 }
741
742 if (HAL_OSPI_Transmit(hospi, &op_enable,
743 HAL_OSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) {
744 LOG_ERR("Write Flash configuration reg2 failed");
745 return -EIO;
746 }
747
748 return 0;
749 }
750
751 /* Read Flash configuration register 2 with new single or octal SPI protocol */
stm32_ospi_read_cfg2reg(OSPI_HandleTypeDef * hospi,uint8_t nor_mode,uint8_t nor_rate,uint8_t * value)752 static int stm32_ospi_read_cfg2reg(OSPI_HandleTypeDef *hospi,
753 uint8_t nor_mode, uint8_t nor_rate, uint8_t *value)
754 {
755 OSPI_RegularCmdTypeDef s_command = ospi_prepare_cmd(nor_mode, nor_rate);
756
757 /* Initialize the writing of configuration register 2 */
758 s_command.Instruction = (nor_mode == OSPI_SPI_MODE)
759 ? SPI_NOR_CMD_RD_CFGREG2
760 : SPI_NOR_OCMD_RD_CFGREG2;
761 s_command.Address = SPI_NOR_REG2_ADDR1;
762 s_command.DummyCycles = (nor_mode == OSPI_SPI_MODE)
763 ? 0U
764 : ((nor_rate == OSPI_DTR_TRANSFER)
765 ? SPI_NOR_DUMMY_REG_OCTAL_DTR
766 : SPI_NOR_DUMMY_REG_OCTAL);
767 s_command.NbData = (nor_rate == OSPI_DTR_TRANSFER) ? 2U : 1U;
768
769 if (HAL_OSPI_Command(hospi, &s_command, HAL_OSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) {
770 LOG_ERR("Write Flash configuration reg2 failed");
771 return -EIO;
772 }
773
774 if (HAL_OSPI_Receive(hospi, value, HAL_OSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) {
775 LOG_ERR("Write Flash configuration reg2 failed");
776 return -EIO;
777 }
778
779 return 0;
780 }
781
782 /* Set the NOR Flash to desired Interface mode : SPI/OSPI and STR/DTR according to the DTS */
stm32_ospi_config_mem(const struct device * dev)783 static int stm32_ospi_config_mem(const struct device *dev)
784 {
785 const struct flash_stm32_ospi_config *dev_cfg = dev->config;
786 struct flash_stm32_ospi_data *dev_data = dev->data;
787 uint8_t reg[2];
788
789 /* Going to set the SPI mode and STR transfer rate : done */
790 if ((dev_cfg->data_mode != OSPI_OPI_MODE)
791 && (dev_cfg->data_rate == OSPI_STR_TRANSFER)) {
792 LOG_INF("OSPI flash config is SPI|DUAL|QUAD / STR");
793 return 0;
794 }
795
796 /* Going to set the OPI mode (STR or DTR transfer rate) */
797 LOG_DBG("OSPI configuring OctoSPI mode");
798
799 if (stm32_ospi_write_enable(&dev_data->hospi,
800 OSPI_SPI_MODE, OSPI_STR_TRANSFER) != 0) {
801 LOG_ERR("OSPI write Enable failed");
802 return -EIO;
803 }
804
805 /* Write Configuration register 2 (with new dummy cycles) */
806 if (stm32_ospi_write_cfg2reg_dummy(&dev_data->hospi,
807 OSPI_SPI_MODE, OSPI_STR_TRANSFER) != 0) {
808 LOG_ERR("OSPI write CFGR2 failed");
809 return -EIO;
810 }
811 if (stm32_ospi_mem_ready(&dev_data->hospi,
812 OSPI_SPI_MODE, OSPI_STR_TRANSFER) != 0) {
813 LOG_ERR("OSPI autopolling failed");
814 return -EIO;
815 }
816 if (stm32_ospi_write_enable(&dev_data->hospi,
817 OSPI_SPI_MODE, OSPI_STR_TRANSFER) != 0) {
818 LOG_ERR("OSPI write Enable 2 failed");
819 return -EIO;
820 }
821
822 /* Write Configuration register 2 (with Octal I/O SPI protocol : choose STR or DTR) */
823 uint8_t mode_enable = ((dev_cfg->data_rate == OSPI_DTR_TRANSFER)
824 ? SPI_NOR_CR2_DTR_OPI_EN
825 : SPI_NOR_CR2_STR_OPI_EN);
826 if (stm32_ospi_write_cfg2reg_io(&dev_data->hospi,
827 OSPI_SPI_MODE, OSPI_STR_TRANSFER, mode_enable) != 0) {
828 LOG_ERR("OSPI write CFGR2 failed");
829 return -EIO;
830 }
831
832 /* Wait that the configuration is effective and check that memory is ready */
833 k_busy_wait(STM32_OSPI_WRITE_REG_MAX_TIME * USEC_PER_MSEC);
834
835 /* Reconfigure the memory type of the peripheral */
836 dev_data->hospi.Init.MemoryType = HAL_OSPI_MEMTYPE_MACRONIX;
837 dev_data->hospi.Init.DelayHoldQuarterCycle = HAL_OSPI_DHQC_ENABLE;
838 if (HAL_OSPI_Init(&dev_data->hospi) != HAL_OK) {
839 LOG_ERR("OSPI mem type MACRONIX failed");
840 return -EIO;
841 }
842
843 if (dev_cfg->data_rate == OSPI_STR_TRANSFER) {
844 if (stm32_ospi_mem_ready(&dev_data->hospi,
845 OSPI_OPI_MODE, OSPI_STR_TRANSFER) != 0) {
846 /* Check Flash busy ? */
847 LOG_ERR("OSPI flash busy failed");
848 return -EIO;
849 }
850
851 if (stm32_ospi_read_cfg2reg(&dev_data->hospi,
852 OSPI_OPI_MODE, OSPI_STR_TRANSFER, reg) != 0) {
853 /* Check the configuration has been correctly done on SPI_NOR_REG2_ADDR1 */
854 LOG_ERR("OSPI flash config read failed");
855 return -EIO;
856 }
857
858 LOG_INF("OSPI flash config is OPI / STR");
859 }
860
861 if (dev_cfg->data_rate == OSPI_DTR_TRANSFER) {
862 if (stm32_ospi_mem_ready(&dev_data->hospi,
863 OSPI_OPI_MODE, OSPI_DTR_TRANSFER) != 0) {
864 /* Check Flash busy ? */
865 LOG_ERR("OSPI flash busy failed");
866 return -EIO;
867 }
868
869 LOG_INF("OSPI flash config is OPI / DTR");
870 }
871
872 return 0;
873 }
874
875 /* gpio or send the different reset command to the NOR flash in SPI/OSPI and STR/DTR */
stm32_ospi_mem_reset(const struct device * dev)876 static int stm32_ospi_mem_reset(const struct device *dev)
877 {
878 struct flash_stm32_ospi_data *dev_data = dev->data;
879
880 #if STM32_OSPI_RESET_GPIO
881 /* Generate RESETn pulse for the flash memory */
882 gpio_pin_configure_dt(&dev_cfg->reset, GPIO_OUTPUT_ACTIVE);
883 k_msleep(DT_INST_PROP(0, reset_gpios_duration));
884 gpio_pin_set_dt(&dev_cfg->reset, 0);
885 #else
886
887 /* Reset command sent sucessively for each mode SPI/OPS & STR/DTR */
888 OSPI_RegularCmdTypeDef s_command = {
889 .OperationType = HAL_OSPI_OPTYPE_COMMON_CFG,
890 .FlashId = HAL_OSPI_FLASH_ID_1,
891 .AddressMode = HAL_OSPI_ADDRESS_NONE,
892 .InstructionMode = HAL_OSPI_INSTRUCTION_1_LINE,
893 .InstructionDtrMode = HAL_OSPI_INSTRUCTION_DTR_DISABLE,
894 .Instruction = SPI_NOR_CMD_RESET_EN,
895 .InstructionSize = HAL_OSPI_INSTRUCTION_8_BITS,
896 .AlternateBytesMode = HAL_OSPI_ALTERNATE_BYTES_NONE,
897 .DataMode = HAL_OSPI_DATA_NONE,
898 .DummyCycles = 0U,
899 .DQSMode = HAL_OSPI_DQS_DISABLE,
900 .SIOOMode = HAL_OSPI_SIOO_INST_EVERY_CMD,
901 };
902
903 /* Reset enable in SPI mode and STR transfer mode */
904 if (HAL_OSPI_Command(&dev_data->hospi,
905 &s_command, HAL_OSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) {
906 LOG_ERR("OSPI reset enable (SPI/STR) failed");
907 return -EIO;
908 }
909
910 /* Reset memory in SPI mode and STR transfer mode */
911 s_command.Instruction = SPI_NOR_CMD_RESET_MEM;
912 if (HAL_OSPI_Command(&dev_data->hospi,
913 &s_command, HAL_OSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) {
914 LOG_ERR("OSPI reset memory (SPI/STR) failed");
915 return -EIO;
916 }
917
918 /* Reset enable in OPI mode and STR transfer mode */
919 s_command.InstructionMode = HAL_OSPI_INSTRUCTION_8_LINES;
920 s_command.InstructionDtrMode = HAL_OSPI_INSTRUCTION_DTR_DISABLE;
921 s_command.Instruction = SPI_NOR_OCMD_RESET_EN;
922 s_command.InstructionSize = HAL_OSPI_INSTRUCTION_16_BITS;
923 if (HAL_OSPI_Command(&dev_data->hospi,
924 &s_command, HAL_OSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) {
925 LOG_ERR("OSPI reset enable (OPI/STR) failed");
926 return -EIO;
927 }
928
929 /* Reset memory in OPI mode and STR transfer mode */
930 s_command.Instruction = SPI_NOR_OCMD_RESET_MEM;
931 if (HAL_OSPI_Command(&dev_data->hospi,
932 &s_command, HAL_OSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) {
933 LOG_ERR("OSPI reset memory (OPI/STR) failed");
934 return -EIO;
935 }
936
937 /* Reset enable in OPI mode and DTR transfer mode */
938 s_command.InstructionDtrMode = HAL_OSPI_INSTRUCTION_DTR_ENABLE;
939 s_command.Instruction = SPI_NOR_OCMD_RESET_EN;
940 if (HAL_OSPI_Command(&dev_data->hospi,
941 &s_command, HAL_OSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) {
942 LOG_ERR("OSPI reset enable (OPI/DTR) failed");
943 return -EIO;
944 }
945
946 /* Reset memory in OPI mode and DTR transfer mode */
947 s_command.Instruction = SPI_NOR_OCMD_RESET_MEM;
948 if (HAL_OSPI_Command(&dev_data->hospi,
949 &s_command, HAL_OSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) {
950 LOG_ERR("OSPI reset memory (OPI/DTR) failed");
951 return -EIO;
952 }
953
954 #endif
955 /* Wait after SWreset CMD, in case SWReset occurred during erase operation */
956 k_busy_wait(STM32_OSPI_RESET_MAX_TIME * USEC_PER_MSEC);
957
958 return 0;
959 }
960
961 /*
962 * Function to erase the flash : chip or sector with possible OSPI/SPI and STR/DTR
963 * to erase the complete chip (using dedicated command) :
964 * set size >= flash size
965 * set addr = 0
966 */
flash_stm32_ospi_erase(const struct device * dev,off_t addr,size_t size)967 static int flash_stm32_ospi_erase(const struct device *dev, off_t addr,
968 size_t size)
969 {
970 const struct flash_stm32_ospi_config *dev_cfg = dev->config;
971 struct flash_stm32_ospi_data *dev_data = dev->data;
972 int ret = 0;
973
974 /* Ignore zero size erase */
975 if (size == 0) {
976 return 0;
977 }
978
979 /* Maximise erase size : means the complete chip */
980 if (size > dev_cfg->flash_size) {
981 size = dev_cfg->flash_size;
982 }
983
984 if (!ospi_address_is_valid(dev, addr, size)) {
985 LOG_ERR("Error: address or size exceeds expected values: "
986 "addr 0x%lx, size %zu", (long)addr, size);
987 return -EINVAL;
988 }
989
990 if (((size % SPI_NOR_SECTOR_SIZE) != 0) && (size < dev_cfg->flash_size)) {
991 LOG_ERR("Error: wrong sector size 0x%x", size);
992 return -ENOTSUP;
993 }
994
995 OSPI_RegularCmdTypeDef cmd_erase = {
996 .OperationType = HAL_OSPI_OPTYPE_COMMON_CFG,
997 .FlashId = HAL_OSPI_FLASH_ID_1,
998 .AlternateBytesMode = HAL_OSPI_ALTERNATE_BYTES_NONE,
999 .DataMode = HAL_OSPI_DATA_NONE,
1000 .DummyCycles = 0U,
1001 .DQSMode = HAL_OSPI_DQS_DISABLE,
1002 .SIOOMode = HAL_OSPI_SIOO_INST_EVERY_CMD,
1003 };
1004
1005 ospi_lock_thread(dev);
1006
1007 if (stm32_ospi_mem_ready(&dev_data->hospi,
1008 dev_cfg->data_mode, dev_cfg->data_rate) != 0) {
1009 ospi_unlock_thread(dev);
1010 LOG_ERR("Erase failed : flash busy");
1011 return -EBUSY;
1012 }
1013
1014 cmd_erase.InstructionMode = (dev_cfg->data_mode == OSPI_OPI_MODE)
1015 ? HAL_OSPI_INSTRUCTION_8_LINES
1016 : HAL_OSPI_INSTRUCTION_1_LINE;
1017 cmd_erase.InstructionDtrMode = (dev_cfg->data_rate == OSPI_DTR_TRANSFER)
1018 ? HAL_OSPI_INSTRUCTION_DTR_ENABLE
1019 : HAL_OSPI_INSTRUCTION_DTR_DISABLE;
1020 cmd_erase.InstructionSize = (dev_cfg->data_mode == OSPI_OPI_MODE)
1021 ? HAL_OSPI_INSTRUCTION_16_BITS
1022 : HAL_OSPI_INSTRUCTION_8_BITS;
1023
1024 while ((size > 0) && (ret == 0)) {
1025
1026 ret = stm32_ospi_write_enable(&dev_data->hospi,
1027 dev_cfg->data_mode, dev_cfg->data_rate);
1028 if (ret != 0) {
1029 LOG_ERR("Erase failed : write enable");
1030 break;
1031 }
1032
1033 if (size == dev_cfg->flash_size) {
1034 /* Chip erase */
1035 LOG_DBG("Chip Erase");
1036
1037 cmd_erase.Address = 0;
1038 cmd_erase.Instruction = (dev_cfg->data_mode == OSPI_OPI_MODE)
1039 ? SPI_NOR_OCMD_BULKE
1040 : SPI_NOR_CMD_BULKE;
1041 cmd_erase.AddressMode = HAL_OSPI_ADDRESS_NONE;
1042 /* Full chip erase (Bulk) command */
1043 ospi_send_cmd(dev, &cmd_erase);
1044
1045 size -= dev_cfg->flash_size;
1046 /* Chip (Bulk) erase started, wait until WEL becomes 0 */
1047 ret = stm32_ospi_mem_erased(&dev_data->hospi,
1048 dev_cfg->data_mode, dev_cfg->data_rate);
1049 if (ret != 0) {
1050 LOG_ERR("Chip Erase failed");
1051 break;
1052 }
1053 } else {
1054 /* Sector or Block erase depending on the size */
1055 LOG_INF("Sector/Block Erase");
1056
1057 cmd_erase.AddressMode =
1058 (dev_cfg->data_mode == OSPI_OPI_MODE)
1059 ? HAL_OSPI_ADDRESS_8_LINES
1060 : HAL_OSPI_ADDRESS_1_LINE;
1061 cmd_erase.AddressDtrMode =
1062 (dev_cfg->data_rate == OSPI_DTR_TRANSFER)
1063 ? HAL_OSPI_ADDRESS_DTR_ENABLE
1064 : HAL_OSPI_ADDRESS_DTR_DISABLE;
1065 cmd_erase.AddressSize = stm32_ospi_hal_address_size(dev);
1066 cmd_erase.Address = addr;
1067
1068 const struct jesd216_erase_type *erase_types =
1069 dev_data->erase_types;
1070 const struct jesd216_erase_type *bet = NULL;
1071
1072 for (uint8_t ei = 0;
1073 ei < JESD216_NUM_ERASE_TYPES; ++ei) {
1074 const struct jesd216_erase_type *etp =
1075 &erase_types[ei];
1076
1077 if ((etp->exp != 0)
1078 && SPI_NOR_IS_ALIGNED(addr, etp->exp)
1079 && (size >= BIT(etp->exp))
1080 && ((bet == NULL)
1081 || (etp->exp > bet->exp))) {
1082 bet = etp;
1083 cmd_erase.Instruction = bet->cmd;
1084 } else if (bet == NULL) {
1085 /* Use the default sector erase cmd */
1086 if (dev_cfg->data_mode == OSPI_OPI_MODE) {
1087 cmd_erase.Instruction = SPI_NOR_OCMD_SE;
1088 } else {
1089 cmd_erase.Instruction =
1090 (stm32_ospi_hal_address_size(dev) ==
1091 HAL_OSPI_ADDRESS_32_BITS)
1092 ? SPI_NOR_CMD_SE_4B
1093 : SPI_NOR_CMD_SE;
1094 }
1095 /* Avoid using wrong erase type,
1096 * if zero entries are found in erase_types
1097 */
1098 bet = NULL;
1099 }
1100 }
1101 LOG_INF("Sector/Block Erase addr 0x%x, asize 0x%x amode 0x%x instr 0x%x",
1102 cmd_erase.Address, cmd_erase.AddressSize,
1103 cmd_erase.AddressMode, cmd_erase.Instruction);
1104
1105 ospi_send_cmd(dev, &cmd_erase);
1106
1107 if (bet != NULL) {
1108 addr += BIT(bet->exp);
1109 size -= BIT(bet->exp);
1110 } else {
1111 addr += SPI_NOR_SECTOR_SIZE;
1112 size -= SPI_NOR_SECTOR_SIZE;
1113 }
1114
1115 ret = stm32_ospi_mem_ready(&dev_data->hospi,
1116 dev_cfg->data_mode, dev_cfg->data_rate);
1117 }
1118
1119 }
1120
1121 ospi_unlock_thread(dev);
1122
1123 return ret;
1124 }
1125
1126 /* Function to read the flash with possible OSPI/SPI and STR/DTR */
flash_stm32_ospi_read(const struct device * dev,off_t addr,void * data,size_t size)1127 static int flash_stm32_ospi_read(const struct device *dev, off_t addr,
1128 void *data, size_t size)
1129 {
1130 const struct flash_stm32_ospi_config *dev_cfg = dev->config;
1131 struct flash_stm32_ospi_data *dev_data = dev->data;
1132 int ret;
1133
1134 if (!ospi_address_is_valid(dev, addr, size)) {
1135 LOG_ERR("Error: address or size exceeds expected values: "
1136 "addr 0x%lx, size %zu", (long)addr, size);
1137 return -EINVAL;
1138 }
1139
1140 /* Ignore zero size read */
1141 if (size == 0) {
1142 return 0;
1143 }
1144
1145 OSPI_RegularCmdTypeDef cmd = ospi_prepare_cmd(dev_cfg->data_mode, dev_cfg->data_rate);
1146
1147 if (dev_cfg->data_mode != OSPI_OPI_MODE) {
1148 switch (dev_data->read_mode) {
1149 case JESD216_MODE_112: {
1150 cmd.InstructionMode = HAL_OSPI_INSTRUCTION_1_LINE;
1151 cmd.AddressMode = HAL_OSPI_ADDRESS_1_LINE;
1152 cmd.DataMode = HAL_OSPI_DATA_2_LINES;
1153 break;
1154 }
1155 case JESD216_MODE_122: {
1156 cmd.InstructionMode = HAL_OSPI_INSTRUCTION_1_LINE;
1157 cmd.AddressMode = HAL_OSPI_ADDRESS_2_LINES;
1158 cmd.DataMode = HAL_OSPI_DATA_2_LINES;
1159 break;
1160 }
1161 case JESD216_MODE_114: {
1162 cmd.InstructionMode = HAL_OSPI_INSTRUCTION_1_LINE;
1163 cmd.AddressMode = HAL_OSPI_ADDRESS_1_LINE;
1164 cmd.DataMode = HAL_OSPI_DATA_4_LINES;
1165 break;
1166 }
1167 case JESD216_MODE_144: {
1168 cmd.InstructionMode = HAL_OSPI_INSTRUCTION_1_LINE;
1169 cmd.AddressMode = HAL_OSPI_ADDRESS_4_LINES;
1170 cmd.DataMode = HAL_OSPI_DATA_4_LINES;
1171 break;
1172 }
1173 default:
1174 /* use the mode from ospi_prepare_cmd */
1175 break;
1176 }
1177 }
1178
1179 /* Instruction and DummyCycles are set below */
1180 cmd.Address = addr; /* AddressSize is 32bits in OPSI mode */
1181 cmd.AddressSize = stm32_ospi_hal_address_size(dev);
1182 /* DataSize is set by the read cmd */
1183
1184 /* Configure other parameters */
1185 if (dev_cfg->data_rate == OSPI_DTR_TRANSFER) {
1186 /* DTR transfer rate (==> Octal mode) */
1187 cmd.Instruction = SPI_NOR_OCMD_DTR_RD;
1188 cmd.DummyCycles = SPI_NOR_DUMMY_RD_OCTAL_DTR;
1189 } else {
1190 /* STR transfer rate */
1191 if (dev_cfg->data_mode == OSPI_OPI_MODE) {
1192 /* OPI and STR */
1193 cmd.Instruction = SPI_NOR_OCMD_RD;
1194 cmd.DummyCycles = SPI_NOR_DUMMY_RD_OCTAL;
1195 } else {
1196 /* use SFDP:BFP read instruction */
1197 cmd.Instruction = dev_data->read_opcode;
1198 cmd.DummyCycles = dev_data->read_dummy;
1199 /* in SPI and STR : expecting SPI_NOR_CMD_READ_FAST_4B */
1200 }
1201 }
1202
1203 LOG_DBG("OSPI: read %zu data", size);
1204 ospi_lock_thread(dev);
1205
1206 ret = ospi_read_access(dev, &cmd, data, size);
1207
1208 ospi_unlock_thread(dev);
1209
1210 return ret;
1211 }
1212
1213 /* Function to write the flash (page program) : with possible OSPI/SPI and STR/DTR */
flash_stm32_ospi_write(const struct device * dev,off_t addr,const void * data,size_t size)1214 static int flash_stm32_ospi_write(const struct device *dev, off_t addr,
1215 const void *data, size_t size)
1216 {
1217 const struct flash_stm32_ospi_config *dev_cfg = dev->config;
1218 struct flash_stm32_ospi_data *dev_data = dev->data;
1219 size_t to_write;
1220 int ret = 0;
1221
1222 if (!ospi_address_is_valid(dev, addr, size)) {
1223 LOG_ERR("Error: address or size exceeds expected values: "
1224 "addr 0x%lx, size %zu", (long)addr, size);
1225 return -EINVAL;
1226 }
1227
1228 /* Ignore zero size write */
1229 if (size == 0) {
1230 return 0;
1231 }
1232
1233 /* page program for STR or DTR mode */
1234 OSPI_RegularCmdTypeDef cmd_pp = ospi_prepare_cmd(dev_cfg->data_mode, dev_cfg->data_rate);
1235
1236 /* using 32bits address also in SPI/STR mode */
1237 cmd_pp.Instruction = dev_data->write_opcode;
1238
1239 if (dev_cfg->data_mode != OSPI_OPI_MODE) {
1240 switch (cmd_pp.Instruction) {
1241 case SPI_NOR_CMD_PP_4B:
1242 __fallthrough;
1243 case SPI_NOR_CMD_PP: {
1244 cmd_pp.InstructionMode = HAL_OSPI_INSTRUCTION_1_LINE;
1245 cmd_pp.AddressMode = HAL_OSPI_ADDRESS_1_LINE;
1246 cmd_pp.DataMode = HAL_OSPI_DATA_1_LINE;
1247 break;
1248 }
1249 case SPI_NOR_CMD_PP_1_1_4_4B:
1250 __fallthrough;
1251 case SPI_NOR_CMD_PP_1_1_4: {
1252 cmd_pp.InstructionMode = HAL_OSPI_INSTRUCTION_1_LINE;
1253 cmd_pp.AddressMode = HAL_OSPI_ADDRESS_1_LINE;
1254 cmd_pp.DataMode = HAL_OSPI_DATA_4_LINES;
1255 break;
1256 }
1257 case SPI_NOR_CMD_PP_1_4_4_4B:
1258 __fallthrough;
1259 case SPI_NOR_CMD_PP_1_4_4: {
1260 cmd_pp.InstructionMode = HAL_OSPI_INSTRUCTION_1_LINE;
1261 cmd_pp.AddressMode = HAL_OSPI_ADDRESS_4_LINES;
1262 cmd_pp.DataMode = HAL_OSPI_DATA_4_LINES;
1263 break;
1264 }
1265 default:
1266 /* use the mode from ospi_prepare_cmd */
1267 break;
1268 }
1269 }
1270
1271 cmd_pp.Address = addr;
1272 cmd_pp.AddressSize = stm32_ospi_hal_address_size(dev);
1273 cmd_pp.DummyCycles = 0U;
1274
1275 LOG_DBG("OSPI: write %zu data", size);
1276 ospi_lock_thread(dev);
1277
1278 ret = stm32_ospi_mem_ready(&dev_data->hospi,
1279 dev_cfg->data_mode, dev_cfg->data_rate);
1280 if (ret != 0) {
1281 ospi_unlock_thread(dev);
1282 LOG_ERR("OSPI: write not ready");
1283 return -EIO;
1284 }
1285
1286 while ((size > 0) && (ret == 0)) {
1287 to_write = size;
1288 ret = stm32_ospi_write_enable(&dev_data->hospi,
1289 dev_cfg->data_mode, dev_cfg->data_rate);
1290 if (ret != 0) {
1291 LOG_ERR("OSPI: write not enabled");
1292 break;
1293 }
1294 /* Don't write more than a page. */
1295 if (to_write >= SPI_NOR_PAGE_SIZE) {
1296 to_write = SPI_NOR_PAGE_SIZE;
1297 }
1298
1299 /* Don't write across a page boundary */
1300 if (((addr + to_write - 1U) / SPI_NOR_PAGE_SIZE)
1301 != (addr / SPI_NOR_PAGE_SIZE)) {
1302 to_write = SPI_NOR_PAGE_SIZE -
1303 (addr % SPI_NOR_PAGE_SIZE);
1304 }
1305 cmd_pp.Address = addr;
1306
1307 ret = ospi_write_access(dev, &cmd_pp, data, to_write);
1308 if (ret != 0) {
1309 LOG_ERR("OSPI: write not access");
1310 break;
1311 }
1312
1313 size -= to_write;
1314 data = (const uint8_t *)data + to_write;
1315 addr += to_write;
1316
1317 /* Configure automatic polling mode to wait for end of program */
1318 ret = stm32_ospi_mem_ready(&dev_data->hospi,
1319 dev_cfg->data_mode, dev_cfg->data_rate);
1320 if (ret != 0) {
1321 LOG_ERR("OSPI: write PP not ready");
1322 break;
1323 }
1324 }
1325
1326 ospi_unlock_thread(dev);
1327
1328 return ret;
1329 }
1330
1331 static const struct flash_parameters flash_stm32_ospi_parameters = {
1332 .write_block_size = 1,
1333 .erase_value = 0xff
1334 };
1335
1336 static const struct flash_parameters *
flash_stm32_ospi_get_parameters(const struct device * dev)1337 flash_stm32_ospi_get_parameters(const struct device *dev)
1338 {
1339 ARG_UNUSED(dev);
1340
1341 return &flash_stm32_ospi_parameters;
1342 }
1343
flash_stm32_ospi_isr(const struct device * dev)1344 static void flash_stm32_ospi_isr(const struct device *dev)
1345 {
1346 struct flash_stm32_ospi_data *dev_data = dev->data;
1347
1348 HAL_OSPI_IRQHandler(&dev_data->hospi);
1349 }
1350
1351 #if !defined(CONFIG_SOC_SERIES_STM32H7X)
1352 /* weak function required for HAL compilation */
HAL_DMA_Abort_IT(DMA_HandleTypeDef * hdma)1353 __weak HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma)
1354 {
1355 return HAL_OK;
1356 }
1357
1358 /* weak function required for HAL compilation */
HAL_DMA_Abort(DMA_HandleTypeDef * hdma)1359 __weak HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
1360 {
1361 return HAL_OK;
1362 }
1363 #endif /* !CONFIG_SOC_SERIES_STM32H7X */
1364
1365 /* This function is executed in the interrupt context */
1366 #if STM32_OSPI_USE_DMA
ospi_dma_callback(const struct device * dev,void * arg,uint32_t channel,int status)1367 static void ospi_dma_callback(const struct device *dev, void *arg,
1368 uint32_t channel, int status)
1369 {
1370 DMA_HandleTypeDef *hdma = arg;
1371
1372 ARG_UNUSED(dev);
1373
1374 if (status < 0) {
1375 LOG_ERR("DMA callback error with channel %d.", channel);
1376 }
1377
1378 HAL_DMA_IRQHandler(hdma);
1379 }
1380 #endif
1381
1382 /*
1383 * Transfer Error callback.
1384 */
HAL_OSPI_ErrorCallback(OSPI_HandleTypeDef * hospi)1385 void HAL_OSPI_ErrorCallback(OSPI_HandleTypeDef *hospi)
1386 {
1387 struct flash_stm32_ospi_data *dev_data =
1388 CONTAINER_OF(hospi, struct flash_stm32_ospi_data, hospi);
1389
1390 LOG_DBG("Error cb");
1391
1392 dev_data->cmd_status = -EIO;
1393
1394 k_sem_give(&dev_data->sync);
1395 }
1396
1397 /*
1398 * Command completed callback.
1399 */
HAL_OSPI_CmdCpltCallback(OSPI_HandleTypeDef * hospi)1400 void HAL_OSPI_CmdCpltCallback(OSPI_HandleTypeDef *hospi)
1401 {
1402 struct flash_stm32_ospi_data *dev_data =
1403 CONTAINER_OF(hospi, struct flash_stm32_ospi_data, hospi);
1404
1405 LOG_DBG("Cmd Cplt cb");
1406
1407 k_sem_give(&dev_data->sync);
1408 }
1409
1410 /*
1411 * Rx Transfer completed callback.
1412 */
HAL_OSPI_RxCpltCallback(OSPI_HandleTypeDef * hospi)1413 void HAL_OSPI_RxCpltCallback(OSPI_HandleTypeDef *hospi)
1414 {
1415 struct flash_stm32_ospi_data *dev_data =
1416 CONTAINER_OF(hospi, struct flash_stm32_ospi_data, hospi);
1417
1418 LOG_DBG("Rx Cplt cb");
1419
1420 k_sem_give(&dev_data->sync);
1421 }
1422
1423 /*
1424 * Tx Transfer completed callback.
1425 */
HAL_OSPI_TxCpltCallback(OSPI_HandleTypeDef * hospi)1426 void HAL_OSPI_TxCpltCallback(OSPI_HandleTypeDef *hospi)
1427 {
1428 struct flash_stm32_ospi_data *dev_data =
1429 CONTAINER_OF(hospi, struct flash_stm32_ospi_data, hospi);
1430
1431 LOG_DBG("Tx Cplt cb");
1432
1433 k_sem_give(&dev_data->sync);
1434 }
1435
1436 /*
1437 * Status Match callback.
1438 */
HAL_OSPI_StatusMatchCallback(OSPI_HandleTypeDef * hospi)1439 void HAL_OSPI_StatusMatchCallback(OSPI_HandleTypeDef *hospi)
1440 {
1441 struct flash_stm32_ospi_data *dev_data =
1442 CONTAINER_OF(hospi, struct flash_stm32_ospi_data, hospi);
1443
1444 LOG_DBG("Status Match cb");
1445
1446 k_sem_give(&dev_data->sync);
1447 }
1448
1449 /*
1450 * Timeout callback.
1451 */
HAL_OSPI_TimeOutCallback(OSPI_HandleTypeDef * hospi)1452 void HAL_OSPI_TimeOutCallback(OSPI_HandleTypeDef *hospi)
1453 {
1454 struct flash_stm32_ospi_data *dev_data =
1455 CONTAINER_OF(hospi, struct flash_stm32_ospi_data, hospi);
1456
1457 LOG_DBG("Timeout cb");
1458
1459 dev_data->cmd_status = -EIO;
1460
1461 k_sem_give(&dev_data->sync);
1462 }
1463
1464 #if defined(CONFIG_FLASH_PAGE_LAYOUT)
flash_stm32_ospi_pages_layout(const struct device * dev,const struct flash_pages_layout ** layout,size_t * layout_size)1465 static void flash_stm32_ospi_pages_layout(const struct device *dev,
1466 const struct flash_pages_layout **layout,
1467 size_t *layout_size)
1468 {
1469 struct flash_stm32_ospi_data *dev_data = dev->data;
1470
1471 *layout = &dev_data->layout;
1472 *layout_size = 1;
1473 }
1474 #endif
1475
1476 static const struct flash_driver_api flash_stm32_ospi_driver_api = {
1477 .read = flash_stm32_ospi_read,
1478 .write = flash_stm32_ospi_write,
1479 .erase = flash_stm32_ospi_erase,
1480 .get_parameters = flash_stm32_ospi_get_parameters,
1481 #if defined(CONFIG_FLASH_PAGE_LAYOUT)
1482 .page_layout = flash_stm32_ospi_pages_layout,
1483 #endif
1484 #if defined(CONFIG_FLASH_JESD216_API)
1485 .sfdp_read = ospi_read_sfdp,
1486 .read_jedec_id = ospi_read_jedec_id,
1487 #endif /* CONFIG_FLASH_JESD216_API */
1488 };
1489
1490 #if defined(CONFIG_FLASH_PAGE_LAYOUT)
setup_pages_layout(const struct device * dev)1491 static int setup_pages_layout(const struct device *dev)
1492 {
1493 const struct flash_stm32_ospi_config *dev_cfg = dev->config;
1494 struct flash_stm32_ospi_data *data = dev->data;
1495 const size_t flash_size = dev_cfg->flash_size;
1496 uint32_t layout_page_size = data->page_size;
1497 uint8_t value = 0;
1498 int rv = 0;
1499
1500 /* Find the smallest erase size. */
1501 for (size_t i = 0; i < ARRAY_SIZE(data->erase_types); ++i) {
1502 const struct jesd216_erase_type *etp = &data->erase_types[i];
1503
1504 if ((etp->cmd != 0)
1505 && ((value == 0) || (etp->exp < value))) {
1506 value = etp->exp;
1507 }
1508 }
1509
1510 uint32_t erase_size = BIT(value);
1511
1512 if (erase_size == 0) {
1513 erase_size = SPI_NOR_SECTOR_SIZE;
1514 }
1515
1516 /* We need layout page size to be compatible with erase size */
1517 if ((layout_page_size % erase_size) != 0) {
1518 LOG_DBG("layout page %u not compatible with erase size %u",
1519 layout_page_size, erase_size);
1520 LOG_DBG("erase size will be used as layout page size");
1521 layout_page_size = erase_size;
1522 }
1523
1524 /* Warn but accept layout page sizes that leave inaccessible
1525 * space.
1526 */
1527 if ((flash_size % layout_page_size) != 0) {
1528 LOG_DBG("layout page %u wastes space with device size %zu",
1529 layout_page_size, flash_size);
1530 }
1531
1532 data->layout.pages_size = layout_page_size;
1533 data->layout.pages_count = flash_size / layout_page_size;
1534 LOG_DBG("layout %u x %u By pages", data->layout.pages_count,
1535 data->layout.pages_size);
1536
1537 return rv;
1538 }
1539 #endif /* CONFIG_FLASH_PAGE_LAYOUT */
1540
stm32_ospi_read_status_register(const struct device * dev,uint8_t reg_num,uint8_t * reg)1541 static int stm32_ospi_read_status_register(const struct device *dev, uint8_t reg_num, uint8_t *reg)
1542 {
1543 OSPI_RegularCmdTypeDef s_command = {
1544 .InstructionMode = HAL_OSPI_INSTRUCTION_1_LINE,
1545 .DataMode = HAL_OSPI_DATA_1_LINE,
1546 };
1547
1548 switch (reg_num) {
1549 case 1U:
1550 s_command.Instruction = SPI_NOR_CMD_RDSR;
1551 break;
1552 case 2U:
1553 s_command.Instruction = SPI_NOR_CMD_RDSR2;
1554 break;
1555 case 3U:
1556 s_command.Instruction = SPI_NOR_CMD_RDSR3;
1557 break;
1558 default:
1559 return -EINVAL;
1560 }
1561
1562 return ospi_read_access(dev, &s_command, reg, sizeof(*reg));
1563 }
1564
stm32_ospi_write_status_register(const struct device * dev,uint8_t reg_num,uint8_t reg)1565 static int stm32_ospi_write_status_register(const struct device *dev, uint8_t reg_num, uint8_t reg)
1566 {
1567 struct flash_stm32_ospi_data *data = dev->data;
1568 OSPI_RegularCmdTypeDef s_command = {
1569 .Instruction = SPI_NOR_CMD_WRSR,
1570 .InstructionMode = HAL_OSPI_INSTRUCTION_1_LINE,
1571 .DataMode = HAL_OSPI_DATA_1_LINE
1572 };
1573 size_t size;
1574 uint8_t regs[4] = { 0 };
1575 uint8_t *regs_p;
1576 int ret;
1577
1578 if (reg_num == 1U) {
1579 size = 1U;
1580 regs[0] = reg;
1581 regs_p = ®s[0];
1582 /* 1 byte write clears SR2, write SR2 as well */
1583 if (data->qer_type == JESD216_DW15_QER_S2B1v1) {
1584 ret = stm32_ospi_read_status_register(dev, 2, ®s[1]);
1585 if (ret < 0) {
1586 return ret;
1587 }
1588 size = 2U;
1589 }
1590 } else if (reg_num == 2U) {
1591 s_command.Instruction = SPI_NOR_CMD_WRSR2;
1592 size = 1U;
1593 regs[1] = reg;
1594 regs_p = ®s[1];
1595 /* if SR2 write needs SR1 */
1596 if ((data->qer_type == JESD216_DW15_QER_VAL_S2B1v1) ||
1597 (data->qer_type == JESD216_DW15_QER_VAL_S2B1v4) ||
1598 (data->qer_type == JESD216_DW15_QER_VAL_S2B1v5)) {
1599 ret = stm32_ospi_read_status_register(dev, 1, ®s[0]);
1600 if (ret < 0) {
1601 return ret;
1602 }
1603 s_command.Instruction = SPI_NOR_CMD_WRSR;
1604 size = 2U;
1605 regs_p = ®s[0];
1606 }
1607 } else if (reg_num == 3U) {
1608 s_command.Instruction = SPI_NOR_CMD_WRSR3;
1609 size = 1U;
1610 regs[2] = reg;
1611 regs_p = ®s[2];
1612 } else {
1613 return -EINVAL;
1614 }
1615
1616 return ospi_write_access(dev, &s_command, regs_p, size);
1617 }
1618
stm32_ospi_enable_qe(const struct device * dev)1619 static int stm32_ospi_enable_qe(const struct device *dev)
1620 {
1621 struct flash_stm32_ospi_data *data = dev->data;
1622 uint8_t qe_reg_num;
1623 uint8_t qe_bit;
1624 uint8_t reg;
1625 int ret;
1626
1627 switch (data->qer_type) {
1628 case JESD216_DW15_QER_NONE:
1629 /* no QE bit, device detects reads based on opcode */
1630 return 0;
1631 case JESD216_DW15_QER_S1B6:
1632 qe_reg_num = 1U;
1633 qe_bit = BIT(6U);
1634 break;
1635 case JESD216_DW15_QER_S2B7:
1636 qe_reg_num = 2U;
1637 qe_bit = BIT(7U);
1638 break;
1639 case JESD216_DW15_QER_S2B1v1:
1640 __fallthrough;
1641 case JESD216_DW15_QER_S2B1v4:
1642 __fallthrough;
1643 case JESD216_DW15_QER_S2B1v5:
1644 __fallthrough;
1645 case JESD216_DW15_QER_S2B1v6:
1646 qe_reg_num = 2U;
1647 qe_bit = BIT(1U);
1648 break;
1649 default:
1650 return -ENOTSUP;
1651 }
1652
1653 ret = stm32_ospi_read_status_register(dev, qe_reg_num, ®);
1654 if (ret < 0) {
1655 return ret;
1656 }
1657
1658 /* exit early if QE bit is already set */
1659 if ((reg & qe_bit) != 0U) {
1660 return 0;
1661 }
1662
1663 ret = stm32_ospi_write_enable(&data->hospi, OSPI_SPI_MODE, OSPI_STR_TRANSFER);
1664 if (ret < 0) {
1665 return ret;
1666 }
1667
1668 reg |= qe_bit;
1669
1670 ret = stm32_ospi_write_status_register(dev, qe_reg_num, reg);
1671 if (ret < 0) {
1672 return ret;
1673 }
1674
1675 ret = stm32_ospi_mem_ready(&data->hospi, OSPI_SPI_MODE, OSPI_STR_TRANSFER);
1676 if (ret < 0) {
1677 return ret;
1678 }
1679
1680 /* validate that QE bit is set */
1681 ret = stm32_ospi_read_status_register(dev, qe_reg_num, ®);
1682 if (ret < 0) {
1683 return ret;
1684 }
1685
1686 if ((reg & qe_bit) == 0U) {
1687 LOG_ERR("Status Register %u [0x%02x] not set", qe_reg_num, reg);
1688 ret = -EIO;
1689 }
1690
1691 return ret;
1692 }
1693
spi_nor_process_bfp_addrbytes(const struct device * dev,const uint8_t jesd216_bfp_addrbytes)1694 static void spi_nor_process_bfp_addrbytes(const struct device *dev,
1695 const uint8_t jesd216_bfp_addrbytes)
1696 {
1697 struct flash_stm32_ospi_data *data = dev->data;
1698
1699 if ((jesd216_bfp_addrbytes == JESD216_SFDP_BFP_DW1_ADDRBYTES_VAL_4B) ||
1700 (jesd216_bfp_addrbytes == JESD216_SFDP_BFP_DW1_ADDRBYTES_VAL_3B4B)) {
1701 data->address_width = 4U;
1702 } else {
1703 data->address_width = 3U;
1704 }
1705 }
1706
spi_nor_convert_read_to_4b(const uint8_t opcode)1707 static inline uint8_t spi_nor_convert_read_to_4b(const uint8_t opcode)
1708 {
1709 switch (opcode) {
1710 case SPI_NOR_CMD_READ:
1711 return SPI_NOR_CMD_READ_4B;
1712 case SPI_NOR_CMD_DREAD:
1713 return SPI_NOR_CMD_DREAD_4B;
1714 case SPI_NOR_CMD_2READ:
1715 return SPI_NOR_CMD_2READ_4B;
1716 case SPI_NOR_CMD_QREAD:
1717 return SPI_NOR_CMD_QREAD_4B;
1718 case SPI_NOR_CMD_4READ:
1719 return SPI_NOR_CMD_4READ_4B;
1720 default:
1721 /* use provided */
1722 return opcode;
1723 }
1724 }
1725
spi_nor_convert_write_to_4b(const uint8_t opcode)1726 static inline uint8_t spi_nor_convert_write_to_4b(const uint8_t opcode)
1727 {
1728 switch (opcode) {
1729 case SPI_NOR_CMD_PP:
1730 return SPI_NOR_CMD_PP_4B;
1731 case SPI_NOR_CMD_PP_1_1_4:
1732 return SPI_NOR_CMD_PP_1_1_4_4B;
1733 case SPI_NOR_CMD_PP_1_4_4:
1734 return SPI_NOR_CMD_PP_1_4_4_4B;
1735 default:
1736 /* use provided */
1737 return opcode;
1738 }
1739 }
1740
spi_nor_process_bfp(const struct device * dev,const struct jesd216_param_header * php,const struct jesd216_bfp * bfp)1741 static int spi_nor_process_bfp(const struct device *dev,
1742 const struct jesd216_param_header *php,
1743 const struct jesd216_bfp *bfp)
1744 {
1745 const struct flash_stm32_ospi_config *dev_cfg = dev->config;
1746 struct flash_stm32_ospi_data *data = dev->data;
1747 /* must be kept in data mode order, ignore 1-1-1 (always supported) */
1748 const enum jesd216_mode_type supported_read_modes[] = { JESD216_MODE_112, JESD216_MODE_122,
1749 JESD216_MODE_114,
1750 JESD216_MODE_144 };
1751 size_t supported_read_modes_max_idx;
1752 struct jesd216_erase_type *etp = data->erase_types;
1753 size_t idx;
1754 const size_t flash_size = jesd216_bfp_density(bfp) / 8U;
1755 struct jesd216_instr read_instr = { 0 };
1756 struct jesd216_bfp_dw15 dw15;
1757
1758 if (flash_size != dev_cfg->flash_size) {
1759 LOG_DBG("Unexpected flash size: %u", flash_size);
1760 }
1761
1762 LOG_DBG("%s: %u MiBy flash", dev->name, (uint32_t)(flash_size >> 20));
1763
1764 /* Copy over the erase types, preserving their order. (The
1765 * Sector Map Parameter table references them by index.)
1766 */
1767 memset(data->erase_types, 0, sizeof(data->erase_types));
1768 for (idx = 1U; idx <= ARRAY_SIZE(data->erase_types); ++idx) {
1769 if (jesd216_bfp_erase(bfp, idx, etp) == 0) {
1770 LOG_DBG("Erase %u with %02x",
1771 (uint32_t)BIT(etp->exp), etp->cmd);
1772 }
1773 ++etp;
1774 }
1775
1776 spi_nor_process_bfp_addrbytes(dev, jesd216_bfp_addrbytes(bfp));
1777 LOG_DBG("Address width: %u Bytes", data->address_width);
1778
1779 /* use PP opcode based on configured data mode if nothing is set in DTS */
1780 if (data->write_opcode == SPI_NOR_WRITEOC_NONE) {
1781 switch (dev_cfg->data_mode) {
1782 case OSPI_OPI_MODE:
1783 data->write_opcode = SPI_NOR_OCMD_PAGE_PRG;
1784 break;
1785 case OSPI_QUAD_MODE:
1786 data->write_opcode = SPI_NOR_CMD_PP_1_4_4;
1787 break;
1788 case OSPI_DUAL_MODE:
1789 data->write_opcode = SPI_NOR_CMD_PP_1_1_2;
1790 break;
1791 default:
1792 data->write_opcode = SPI_NOR_CMD_PP;
1793 break;
1794 }
1795 }
1796
1797 if (dev_cfg->data_mode != OSPI_OPI_MODE) {
1798 /* determine supported read modes, begin from the slowest */
1799 data->read_mode = JESD216_MODE_111;
1800 data->read_opcode = SPI_NOR_CMD_READ;
1801 data->read_dummy = 0U;
1802
1803 if (dev_cfg->data_mode != OSPI_SPI_MODE) {
1804 if (dev_cfg->data_mode == OSPI_DUAL_MODE) {
1805 /* the index of JESD216_MODE_114 in supported_read_modes */
1806 supported_read_modes_max_idx = 2U;
1807 } else {
1808 supported_read_modes_max_idx = ARRAY_SIZE(supported_read_modes);
1809 }
1810
1811 for (idx = 0U; idx < supported_read_modes_max_idx; ++idx) {
1812 if (jesd216_bfp_read_support(php, bfp, supported_read_modes[idx],
1813 &read_instr) < 0) {
1814 /* not supported */
1815 continue;
1816 }
1817
1818 LOG_DBG("Supports read mode: %d, instr: 0x%X",
1819 supported_read_modes[idx], read_instr.instr);
1820 data->read_mode = supported_read_modes[idx];
1821 data->read_opcode = read_instr.instr;
1822 data->read_dummy =
1823 (read_instr.wait_states + read_instr.mode_clocks);
1824 }
1825 }
1826
1827 /* convert 3-Byte opcodes to 4-Byte (if required) */
1828 if (IS_ENABLED(DT_INST_PROP(0, four_byte_opcodes))) {
1829 if (data->address_width != 4U) {
1830 LOG_DBG("4-Byte opcodes require 4-Byte address width");
1831 return -ENOTSUP;
1832 }
1833 data->read_opcode = spi_nor_convert_read_to_4b(data->read_opcode);
1834 data->write_opcode = spi_nor_convert_write_to_4b(data->write_opcode);
1835 }
1836
1837 /* enable quad mode (if required) */
1838 if (dev_cfg->data_mode == OSPI_QUAD_MODE) {
1839 if (jesd216_bfp_decode_dw15(php, bfp, &dw15) < 0) {
1840 /* will use QER from DTS or default (refer to device data) */
1841 LOG_WRN("Unable to decode QE requirement [DW15]");
1842 } else {
1843 /* bypass DTS QER value */
1844 data->qer_type = dw15.qer;
1845 }
1846
1847 LOG_DBG("QE requirement mode: %x", data->qer_type);
1848
1849 if (stm32_ospi_enable_qe(dev) < 0) {
1850 LOG_ERR("Failed to enable QUAD mode");
1851 return -EIO;
1852 }
1853
1854 LOG_DBG("QUAD mode enabled");
1855 }
1856 }
1857
1858 data->page_size = jesd216_bfp_page_size(php, bfp);
1859
1860 LOG_DBG("Page size %u bytes", data->page_size);
1861 LOG_DBG("Flash size %zu bytes", flash_size);
1862 LOG_DBG("Using read mode: %d, instr: 0x%X, dummy cycles: %u",
1863 data->read_mode, data->read_opcode, data->read_dummy);
1864 LOG_DBG("Using write instr: 0x%X", data->write_opcode);
1865
1866 return 0;
1867 }
1868
flash_stm32_ospi_init(const struct device * dev)1869 static int flash_stm32_ospi_init(const struct device *dev)
1870 {
1871 const struct flash_stm32_ospi_config *dev_cfg = dev->config;
1872 struct flash_stm32_ospi_data *dev_data = dev->data;
1873 uint32_t ahb_clock_freq;
1874 uint32_t prescaler = STM32_OSPI_CLOCK_PRESCALER_MIN;
1875 int ret;
1876
1877 /* The SPI/DTR is not a valid config of data_mode/data_rate according to the DTS */
1878 if ((dev_cfg->data_mode != OSPI_OPI_MODE)
1879 && (dev_cfg->data_rate == OSPI_DTR_TRANSFER)) {
1880 /* already the right config, continue */
1881 LOG_ERR("OSPI mode SPI|DUAL|QUAD/DTR is not valid");
1882 return -ENOTSUP;
1883 }
1884
1885 /* Signals configuration */
1886 ret = pinctrl_apply_state(dev_cfg->pcfg, PINCTRL_STATE_DEFAULT);
1887 if (ret < 0) {
1888 LOG_ERR("OSPI pinctrl setup failed (%d)", ret);
1889 return ret;
1890 }
1891
1892 if (!device_is_ready(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE))) {
1893 LOG_ERR("clock control device not ready");
1894 return -ENODEV;
1895 }
1896
1897 #if STM32_OSPI_USE_DMA
1898 /*
1899 * DMA configuration
1900 * Due to use of OSPI HAL API in current driver,
1901 * both HAL and Zephyr DMA drivers should be configured.
1902 * The required configuration for Zephyr DMA driver should only provide
1903 * the minimum information to inform the DMA slot will be in used and
1904 * how to route callbacks.
1905 */
1906 struct dma_config dma_cfg = dev_data->dma.cfg;
1907 static DMA_HandleTypeDef hdma;
1908
1909 if (!device_is_ready(dev_data->dma.dev)) {
1910 LOG_ERR("%s device not ready", dev_data->dma.dev->name);
1911 return -ENODEV;
1912 }
1913
1914 /* Proceed to the minimum Zephyr DMA driver init */
1915 dma_cfg.user_data = &hdma;
1916 /* HACK: This field is used to inform driver that it is overridden */
1917 dma_cfg.linked_channel = STM32_DMA_HAL_OVERRIDE;
1918 /* Because of the STREAM OFFSET, the DMA channel given here is from 1 - 8 */
1919 ret = dma_config(dev_data->dma.dev,
1920 (dev_data->dma.channel + STM32_DMA_STREAM_OFFSET), &dma_cfg);
1921 if (ret != 0) {
1922 LOG_ERR("Failed to configure DMA channel %d",
1923 dev_data->dma.channel + STM32_DMA_STREAM_OFFSET);
1924 return ret;
1925 }
1926
1927 /* Proceed to the HAL DMA driver init */
1928 if (dma_cfg.source_data_size != dma_cfg.dest_data_size) {
1929 LOG_ERR("Source and destination data sizes not aligned");
1930 return -EINVAL;
1931 }
1932
1933 int index = find_lsb_set(dma_cfg.source_data_size) - 1;
1934
1935 #if CONFIG_DMA_STM32U5
1936 /* Fill the structure for dma init */
1937 hdma.Init.BlkHWRequest = DMA_BREQ_SINGLE_BURST;
1938 hdma.Init.SrcInc = DMA_SINC_FIXED;
1939 hdma.Init.DestInc = DMA_DINC_INCREMENTED;
1940 hdma.Init.SrcDataWidth = table_src_size[index];
1941 hdma.Init.DestDataWidth = table_dest_size[index];
1942 hdma.Init.SrcBurstLength = 4;
1943 hdma.Init.DestBurstLength = 4;
1944 hdma.Init.TransferAllocatedPort = DMA_SRC_ALLOCATED_PORT0 | DMA_DEST_ALLOCATED_PORT1;
1945 hdma.Init.TransferEventMode = DMA_TCEM_BLOCK_TRANSFER;
1946 #else
1947 hdma.Init.PeriphDataAlignment = table_p_size[index];
1948 hdma.Init.MemDataAlignment = table_m_size[index];
1949 hdma.Init.PeriphInc = DMA_PINC_DISABLE;
1950 hdma.Init.MemInc = DMA_MINC_ENABLE;
1951 #endif /* CONFIG_DMA_STM32U5 */
1952 hdma.Init.Mode = DMA_NORMAL;
1953 hdma.Init.Priority = table_priority[dma_cfg.channel_priority];
1954 hdma.Init.Direction = DMA_PERIPH_TO_MEMORY;
1955 #ifdef CONFIG_DMA_STM32_V1
1956 /* TODO: Not tested in this configuration */
1957 hdma.Init.Channel = dma_cfg.dma_slot;
1958 hdma.Instance = __LL_DMA_GET_STREAM_INSTANCE(dev_data->dma.reg,
1959 dev_data->dma.channel);
1960 #else
1961 hdma.Init.Request = dma_cfg.dma_slot;
1962 #if CONFIG_DMA_STM32U5
1963 hdma.Instance = LL_DMA_GET_CHANNEL_INSTANCE(dev_data->dma.reg,
1964 dev_data->dma.channel);
1965 #elif defined(CONFIG_DMAMUX_STM32)
1966 /*
1967 * HAL expects a valid DMA channel (not DMAMUX).
1968 * The channel is from 0 to 7 because of the STM32_DMA_STREAM_OFFSET in the dma_stm32 driver
1969 */
1970 hdma.Instance = __LL_DMA_GET_CHANNEL_INSTANCE(dev_data->dma.reg,
1971 dev_data->dma.channel);
1972 #else
1973 hdma.Instance = __LL_DMA_GET_CHANNEL_INSTANCE(dev_data->dma.reg,
1974 dev_data->dma.channel-1);
1975 #endif /* CONFIG_DMA_STM32U5 */
1976 #endif /* CONFIG_DMA_STM32_V1 */
1977
1978 /* Initialize DMA HAL */
1979 __HAL_LINKDMA(&dev_data->hospi, hdma, hdma);
1980 if (HAL_DMA_Init(&hdma) != HAL_OK) {
1981 LOG_ERR("OSPI DMA Init failed");
1982 return -EIO;
1983 }
1984 LOG_INF("OSPI with DMA transfer");
1985
1986 #endif /* STM32_OSPI_USE_DMA */
1987
1988 /* Clock configuration */
1989 if (clock_control_on(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE),
1990 (clock_control_subsys_t) &dev_cfg->pclken) != 0) {
1991 LOG_ERR("Could not enable OSPI clock");
1992 return -EIO;
1993 }
1994 /* Alternate clock config for peripheral if any */
1995 #if DT_CLOCKS_HAS_NAME(STM32_OSPI_NODE, ospi_ker)
1996 if (clock_control_configure(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE),
1997 (clock_control_subsys_t) &dev_cfg->pclken_ker,
1998 NULL) != 0) {
1999 LOG_ERR("Could not select OSPI domain clock");
2000 return -EIO;
2001 }
2002 if (clock_control_get_rate(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE),
2003 (clock_control_subsys_t) &dev_cfg->pclken_ker,
2004 &ahb_clock_freq) < 0) {
2005 LOG_ERR("Failed call clock_control_get_rate(pclken_ker)");
2006 return -EIO;
2007 }
2008 #else
2009 if (clock_control_get_rate(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE),
2010 (clock_control_subsys_t) &dev_cfg->pclken,
2011 &ahb_clock_freq) < 0) {
2012 LOG_ERR("Failed call clock_control_get_rate(pclken)");
2013 return -EIO;
2014 }
2015 #endif
2016 #if DT_CLOCKS_HAS_NAME(STM32_OSPI_NODE, ospi_mgr)
2017 if (clock_control_on(DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE),
2018 (clock_control_subsys_t) &dev_cfg->pclken_mgr) != 0) {
2019 LOG_ERR("Could not enable OSPI Manager clock");
2020 return -EIO;
2021 }
2022 #endif
2023
2024 for (; prescaler <= STM32_OSPI_CLOCK_PRESCALER_MAX; prescaler++) {
2025 uint32_t clk = STM32_OSPI_CLOCK_COMPUTE(ahb_clock_freq, prescaler);
2026
2027 if (clk <= dev_cfg->max_frequency) {
2028 break;
2029 }
2030 }
2031 __ASSERT_NO_MSG(prescaler >= STM32_OSPI_CLOCK_PRESCALER_MIN &&
2032 prescaler <= STM32_OSPI_CLOCK_PRESCALER_MAX);
2033
2034 /* Initialize OSPI HAL structure completely */
2035 dev_data->hospi.Init.FifoThreshold = 4;
2036 dev_data->hospi.Init.ClockPrescaler = prescaler;
2037 #if defined(CONFIG_SOC_SERIES_STM32H5X)
2038 /* The stm32h5xx_hal_xspi does not reduce DEVSIZE before writing the DCR1 */
2039 dev_data->hospi.Init.DeviceSize = find_lsb_set(dev_cfg->flash_size) - 2;
2040 #else
2041 /* Give a bit position from 0 to 31 to the HAL init for the DCR1 reg */
2042 dev_data->hospi.Init.DeviceSize = find_lsb_set(dev_cfg->flash_size) - 1;
2043 #endif /* CONFIG_SOC_SERIES_STM32U5X */
2044 dev_data->hospi.Init.DualQuad = HAL_OSPI_DUALQUAD_DISABLE;
2045 dev_data->hospi.Init.ChipSelectHighTime = 2;
2046 dev_data->hospi.Init.FreeRunningClock = HAL_OSPI_FREERUNCLK_DISABLE;
2047 dev_data->hospi.Init.ClockMode = HAL_OSPI_CLOCK_MODE_0;
2048 #if defined(OCTOSPI_DCR2_WRAPSIZE)
2049 dev_data->hospi.Init.WrapSize = HAL_OSPI_WRAP_NOT_SUPPORTED;
2050 #endif /* OCTOSPI_DCR2_WRAPSIZE */
2051 /* STR mode else Macronix for DTR mode */
2052 if (dev_cfg->data_rate == OSPI_DTR_TRANSFER) {
2053 dev_data->hospi.Init.MemoryType = HAL_OSPI_MEMTYPE_MACRONIX;
2054 dev_data->hospi.Init.DelayHoldQuarterCycle = HAL_OSPI_DHQC_ENABLE;
2055 } else {
2056 dev_data->hospi.Init.MemoryType = HAL_OSPI_MEMTYPE_MICRON;
2057 dev_data->hospi.Init.DelayHoldQuarterCycle = HAL_OSPI_DHQC_DISABLE;
2058 }
2059 dev_data->hospi.Init.ChipSelectBoundary = 0;
2060 #if STM32_OSPI_DLYB_BYPASSED
2061 dev_data->hospi.Init.DelayBlockBypass = HAL_OSPI_DELAY_BLOCK_BYPASSED;
2062 #else
2063 dev_data->hospi.Init.DelayBlockBypass = HAL_OSPI_DELAY_BLOCK_USED;
2064 #endif /* STM32_OSPI_DLYB_BYPASSED */
2065 #if defined(OCTOSPI_DCR4_REFRESH)
2066 dev_data->hospi.Init.Refresh = 0;
2067 #endif /* OCTOSPI_DCR4_REFRESH */
2068
2069 if (HAL_OSPI_Init(&dev_data->hospi) != HAL_OK) {
2070 LOG_ERR("OSPI Init failed");
2071 return -EIO;
2072 }
2073
2074 LOG_DBG("OSPI Init'd");
2075
2076 #if defined(OCTOSPIM)
2077 /* OCTOSPI I/O manager init Function */
2078 OSPIM_CfgTypeDef ospi_mgr_cfg = {0};
2079
2080 if (dev_data->hospi.Instance == OCTOSPI1) {
2081 ospi_mgr_cfg.ClkPort = 1;
2082 ospi_mgr_cfg.DQSPort = 1;
2083 ospi_mgr_cfg.NCSPort = 1;
2084 ospi_mgr_cfg.IOLowPort = DT_OSPI_IO_PORT_PROP_OR(io_low_port,
2085 HAL_OSPIM_IOPORT_1_LOW);
2086 ospi_mgr_cfg.IOHighPort = DT_OSPI_IO_PORT_PROP_OR(io_high_port,
2087 HAL_OSPIM_IOPORT_1_HIGH);
2088 } else if (dev_data->hospi.Instance == OCTOSPI2) {
2089 ospi_mgr_cfg.ClkPort = 2;
2090 ospi_mgr_cfg.DQSPort = 2;
2091 ospi_mgr_cfg.NCSPort = 2;
2092 ospi_mgr_cfg.IOLowPort = DT_OSPI_IO_PORT_PROP_OR(io_low_port,
2093 HAL_OSPIM_IOPORT_2_LOW);
2094 ospi_mgr_cfg.IOHighPort = DT_OSPI_IO_PORT_PROP_OR(io_high_port,
2095 HAL_OSPIM_IOPORT_2_HIGH);
2096 }
2097 #if defined(OCTOSPIM_CR_MUXEN)
2098 ospi_mgr_cfg.Req2AckTime = 1;
2099 #endif /* OCTOSPIM_CR_MUXEN */
2100 if (HAL_OSPIM_Config(&dev_data->hospi, &ospi_mgr_cfg,
2101 HAL_OSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) {
2102 LOG_ERR("OSPI M config failed");
2103 return -EIO;
2104 }
2105 #if defined(CONFIG_SOC_SERIES_STM32U5X)
2106 /* OCTOSPI2 delay block init Function */
2107 HAL_OSPI_DLYB_CfgTypeDef ospi_delay_block_cfg = {0};
2108
2109 ospi_delay_block_cfg.Units = 56;
2110 ospi_delay_block_cfg.PhaseSel = 2;
2111 if (HAL_OSPI_DLYB_SetConfig(&dev_data->hospi, &ospi_delay_block_cfg) != HAL_OK) {
2112 LOG_ERR("OSPI DelayBlock failed");
2113 return -EIO;
2114 }
2115 #endif /* CONFIG_SOC_SERIES_STM32U5X */
2116
2117 #endif /* OCTOSPIM */
2118
2119 #if defined(CONFIG_SOC_SERIES_STM32H5X)
2120 /* OCTOSPI1 delay block init Function */
2121 HAL_XSPI_DLYB_CfgTypeDef xspi_delay_block_cfg = {0};
2122
2123 (void)HAL_XSPI_DLYB_GetClockPeriod(&dev_data->hospi, &xspi_delay_block_cfg);
2124 /* with DTR, set the PhaseSel/4 (empiric value from stm32Cube) */
2125 xspi_delay_block_cfg.PhaseSel /= 4;
2126
2127 if (HAL_XSPI_DLYB_SetConfig(&dev_data->hospi, &xspi_delay_block_cfg) != HAL_OK) {
2128 LOG_ERR("XSPI DelayBlock failed");
2129 return -EIO;
2130 }
2131
2132 LOG_DBG("Delay Block Init");
2133
2134 #endif /* CONFIG_SOC_SERIES_STM32H5X */
2135
2136 /* Reset NOR flash memory : still with the SPI/STR config for the NOR */
2137 if (stm32_ospi_mem_reset(dev) != 0) {
2138 LOG_ERR("OSPI reset failed");
2139 return -EIO;
2140 }
2141
2142 LOG_DBG("Reset Mem (SPI/STR)");
2143
2144 /* Check if memory is ready in the SPI/STR mode */
2145 if (stm32_ospi_mem_ready(&dev_data->hospi,
2146 OSPI_SPI_MODE, OSPI_STR_TRANSFER) != 0) {
2147 LOG_ERR("OSPI memory not ready");
2148 return -EIO;
2149 }
2150
2151 LOG_DBG("Mem Ready (SPI/STR)");
2152
2153 #if defined(CONFIG_FLASH_JESD216_API)
2154 /* Process with the RDID (jedec read ID) instruction at init and fill jedec_id Table */
2155 ret = stm32_ospi_read_jedec_id(dev);
2156 if (ret != 0) {
2157 LOG_ERR("Read ID failed: %d", ret);
2158 return ret;
2159 }
2160 #endif /* CONFIG_FLASH_JESD216_API */
2161
2162 if (stm32_ospi_config_mem(dev) != 0) {
2163 LOG_ERR("OSPI mode not config'd (%u rate %u)",
2164 dev_cfg->data_mode, dev_cfg->data_rate);
2165 return -EIO;
2166 }
2167
2168 /* Initialize semaphores */
2169 k_sem_init(&dev_data->sem, 1, 1);
2170 k_sem_init(&dev_data->sync, 0, 1);
2171
2172 /* Run IRQ init */
2173 dev_cfg->irq_config(dev);
2174
2175 /* Send the instruction to read the SFDP */
2176 const uint8_t decl_nph = 2;
2177 union {
2178 /* We only process BFP so use one parameter block */
2179 uint8_t raw[JESD216_SFDP_SIZE(decl_nph)];
2180 struct jesd216_sfdp_header sfdp;
2181 } u;
2182 const struct jesd216_sfdp_header *hp = &u.sfdp;
2183
2184 ret = ospi_read_sfdp(dev, 0, u.raw, sizeof(u.raw));
2185 if (ret != 0) {
2186 LOG_ERR("SFDP read failed: %d", ret);
2187 return ret;
2188 }
2189
2190 uint32_t magic = jesd216_sfdp_magic(hp);
2191
2192 if (magic != JESD216_SFDP_MAGIC) {
2193 LOG_ERR("SFDP magic %08x invalid", magic);
2194 return -EINVAL;
2195 }
2196
2197 LOG_DBG("%s: SFDP v %u.%u AP %x with %u PH", dev->name,
2198 hp->rev_major, hp->rev_minor, hp->access, 1 + hp->nph);
2199
2200 const struct jesd216_param_header *php = hp->phdr;
2201 const struct jesd216_param_header *phpe = php +
2202 MIN(decl_nph, 1 + hp->nph);
2203
2204 while (php != phpe) {
2205 uint16_t id = jesd216_param_id(php);
2206
2207 LOG_DBG("PH%u: %04x rev %u.%u: %u DW @ %x",
2208 (php - hp->phdr), id, php->rev_major, php->rev_minor,
2209 php->len_dw, jesd216_param_addr(php));
2210
2211 if (id == JESD216_SFDP_PARAM_ID_BFP) {
2212 union {
2213 uint32_t dw[20];
2214 struct jesd216_bfp bfp;
2215 } u2;
2216 const struct jesd216_bfp *bfp = &u2.bfp;
2217
2218 ret = ospi_read_sfdp(dev, jesd216_param_addr(php),
2219 (uint8_t *)u2.dw,
2220 MIN(sizeof(uint32_t) * php->len_dw, sizeof(u2.dw)));
2221 if (ret == 0) {
2222 ret = spi_nor_process_bfp(dev, php, bfp);
2223 }
2224
2225 if (ret != 0) {
2226 LOG_ERR("SFDP BFP failed: %d", ret);
2227 break;
2228 }
2229 }
2230 ++php;
2231 }
2232
2233 #if defined(CONFIG_FLASH_PAGE_LAYOUT)
2234 ret = setup_pages_layout(dev);
2235 if (ret != 0) {
2236 LOG_ERR("layout setup failed: %d", ret);
2237 return -ENODEV;
2238 }
2239 #endif /* CONFIG_FLASH_PAGE_LAYOUT */
2240
2241 LOG_INF("NOR octo-flash at 0x%lx (0x%x bytes)",
2242 (long)(STM32_OSPI_BASE_ADDRESS),
2243 dev_cfg->flash_size);
2244
2245 return 0;
2246 }
2247
2248 #if STM32_OSPI_USE_DMA
2249 #define DMA_CHANNEL_CONFIG(node, dir) \
2250 DT_DMAS_CELL_BY_NAME(node, dir, channel_config)
2251
2252 #define OSPI_DMA_CHANNEL_INIT(node, dir) \
2253 .dev = DEVICE_DT_GET(DT_DMAS_CTLR(node)), \
2254 .channel = DT_DMAS_CELL_BY_NAME(node, dir, channel), \
2255 .reg = (DMA_TypeDef *)DT_REG_ADDR( \
2256 DT_PHANDLE_BY_NAME(node, dmas, dir)),\
2257 .cfg = { \
2258 .dma_slot = DT_DMAS_CELL_BY_NAME(node, dir, slot), \
2259 .source_data_size = STM32_DMA_CONFIG_PERIPHERAL_DATA_SIZE( \
2260 DMA_CHANNEL_CONFIG(node, dir)), \
2261 .dest_data_size = STM32_DMA_CONFIG_MEMORY_DATA_SIZE( \
2262 DMA_CHANNEL_CONFIG(node, dir)), \
2263 .channel_priority = STM32_DMA_CONFIG_PRIORITY( \
2264 DMA_CHANNEL_CONFIG(node, dir)), \
2265 .dma_callback = ospi_dma_callback, \
2266 }, \
2267
2268 #define OSPI_DMA_CHANNEL(node, dir) \
2269 .dma = { \
2270 COND_CODE_1(DT_DMAS_HAS_NAME(node, dir), \
2271 (OSPI_DMA_CHANNEL_INIT(node, dir)), \
2272 (NULL)) \
2273 },
2274
2275 #else
2276 #define OSPI_DMA_CHANNEL(node, dir)
2277 #endif /* CONFIG_USE_STM32_HAL_DMA */
2278
2279 #define OSPI_FLASH_MODULE(drv_id, flash_id) \
2280 (DT_DRV_INST(drv_id), ospi_nor_flash_##flash_id)
2281
2282 #define DT_WRITEOC_PROP_OR(inst, default_value) \
2283 COND_CODE_1(DT_INST_NODE_HAS_PROP(inst, writeoc), \
2284 (_CONCAT(SPI_NOR_CMD_, DT_STRING_TOKEN(DT_DRV_INST(inst), writeoc))), \
2285 ((default_value)))
2286
2287 #define DT_QER_PROP_OR(inst, default_value) \
2288 COND_CODE_1(DT_INST_NODE_HAS_PROP(inst, quad_enable_requirements), \
2289 (_CONCAT(JESD216_DW15_QER_VAL_, \
2290 DT_STRING_TOKEN(DT_DRV_INST(inst), quad_enable_requirements))), \
2291 ((default_value)))
2292
2293 static void flash_stm32_ospi_irq_config_func(const struct device *dev);
2294
2295 PINCTRL_DT_DEFINE(STM32_OSPI_NODE);
2296
2297 static const struct flash_stm32_ospi_config flash_stm32_ospi_cfg = {
2298 .regs = (OCTOSPI_TypeDef *)DT_REG_ADDR(STM32_OSPI_NODE),
2299 .pclken = {.bus = DT_CLOCKS_CELL_BY_NAME(STM32_OSPI_NODE, ospix, bus),
2300 .enr = DT_CLOCKS_CELL_BY_NAME(STM32_OSPI_NODE, ospix, bits)},
2301 #if DT_CLOCKS_HAS_NAME(STM32_OSPI_NODE, ospi_ker)
2302 .pclken_ker = {.bus = DT_CLOCKS_CELL_BY_NAME(STM32_OSPI_NODE, ospi_ker, bus),
2303 .enr = DT_CLOCKS_CELL_BY_NAME(STM32_OSPI_NODE, ospi_ker, bits)},
2304 #endif
2305 #if DT_CLOCKS_HAS_NAME(STM32_OSPI_NODE, ospi_mgr)
2306 .pclken_mgr = {.bus = DT_CLOCKS_CELL_BY_NAME(STM32_OSPI_NODE, ospi_mgr, bus),
2307 .enr = DT_CLOCKS_CELL_BY_NAME(STM32_OSPI_NODE, ospi_mgr, bits)},
2308 #endif
2309 .irq_config = flash_stm32_ospi_irq_config_func,
2310 .flash_size = DT_INST_REG_ADDR_BY_IDX(0, 1),
2311 .max_frequency = DT_INST_PROP(0, ospi_max_frequency),
2312 .data_mode = DT_INST_PROP(0, spi_bus_width), /* SPI or OPI */
2313 .data_rate = DT_INST_PROP(0, data_rate), /* DTR or STR */
2314 .pcfg = PINCTRL_DT_DEV_CONFIG_GET(STM32_OSPI_NODE),
2315 #if STM32_OSPI_RESET_GPIO
2316 .reset = GPIO_DT_SPEC_INST_GET(0, reset_gpios),
2317 #endif /* STM32_OSPI_RESET_GPIO */
2318 #if DT_NODE_HAS_PROP(DT_INST(0, st_stm32_ospi_nor), sfdp_bfp)
2319 .sfdp_bfp = DT_INST_PROP(0, sfdp_bfp),
2320 #endif /* sfdp_bfp */
2321 };
2322
2323 static struct flash_stm32_ospi_data flash_stm32_ospi_dev_data = {
2324 .hospi = {
2325 .Instance = (OCTOSPI_TypeDef *)DT_REG_ADDR(STM32_OSPI_NODE),
2326 .Init = {
2327 .FifoThreshold = STM32_OSPI_FIFO_THRESHOLD,
2328 .SampleShifting = (DT_PROP(STM32_OSPI_NODE, ssht_enable)
2329 ? HAL_OSPI_SAMPLE_SHIFTING_HALFCYCLE
2330 : HAL_OSPI_SAMPLE_SHIFTING_NONE),
2331 .ChipSelectHighTime = 1,
2332 .ClockMode = HAL_OSPI_CLOCK_MODE_0,
2333 },
2334 },
2335 .qer_type = DT_QER_PROP_OR(0, JESD216_DW15_QER_VAL_S1B6),
2336 .write_opcode = DT_WRITEOC_PROP_OR(0, SPI_NOR_WRITEOC_NONE),
2337 .page_size = SPI_NOR_PAGE_SIZE, /* by default, to be updated by sfdp */
2338 #if DT_NODE_HAS_PROP(DT_INST(0, st_stm32_ospi_nor), jedec_id)
2339 .jedec_id = DT_INST_PROP(0, jedec_id),
2340 #endif /* jedec_id */
2341 OSPI_DMA_CHANNEL(STM32_OSPI_NODE, tx_rx)
2342 };
2343
2344 DEVICE_DT_INST_DEFINE(0, &flash_stm32_ospi_init, NULL,
2345 &flash_stm32_ospi_dev_data, &flash_stm32_ospi_cfg,
2346 POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
2347 &flash_stm32_ospi_driver_api);
2348
flash_stm32_ospi_irq_config_func(const struct device * dev)2349 static void flash_stm32_ospi_irq_config_func(const struct device *dev)
2350 {
2351 IRQ_CONNECT(DT_IRQN(STM32_OSPI_NODE), DT_IRQ(STM32_OSPI_NODE, priority),
2352 flash_stm32_ospi_isr, DEVICE_DT_INST_GET(0), 0);
2353 irq_enable(DT_IRQN(STM32_OSPI_NODE));
2354 }
2355
