1 /*
2 * Copyright 2023 NXP
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #define DT_DRV_COMPAT nxp_s32_qspi_nor
8
9 #include <zephyr/logging/log.h>
10 LOG_MODULE_REGISTER(nxp_s32_qspi_nor, CONFIG_FLASH_LOG_LEVEL);
11
12 #include <zephyr/kernel.h>
13 #include <zephyr/drivers/flash.h>
14 #include <zephyr/sys/util.h>
15
16 #include <Qspi_Ip.h>
17
18 #include "spi_nor.h"
19 #include "jesd216.h"
20
21 #include "memc_nxp_s32_qspi.h"
22
23 #define QSPI_INST_NODE_HAS_PROP_EQ_AND_OR(n, prop, val) \
24 COND_CODE_1(DT_INST_NODE_HAS_PROP(n, prop), \
25 (IS_EQ(DT_INST_ENUM_IDX(n, prop), val)), \
26 (0)) ||
27
28 #define QSPI_ANY_INST_HAS_PROP_EQ(prop, val) \
29 (DT_INST_FOREACH_STATUS_OKAY_VARGS(QSPI_INST_NODE_HAS_PROP_EQ_AND_OR, prop, val) 0)
30
31 #define QSPI_INST_NODE_NOT_HAS_PROP_AND_OR(n, prop) \
32 !DT_INST_NODE_HAS_PROP(n, prop) ||
33
34 #define QSPI_ANY_INST_HAS_PROP_STATUS_NOT_OKAY(prop) \
35 (DT_INST_FOREACH_STATUS_OKAY_VARGS(QSPI_INST_NODE_NOT_HAS_PROP_AND_OR, prop) 0)
36
37 #define QSPI_QER_TYPE(n) \
38 _CONCAT(JESD216_DW15_QER_VAL_, \
39 DT_INST_STRING_TOKEN_OR(n, quad_enable_requirements, S1B6))
40
41 #define QSPI_HAS_QUAD_MODE(n) \
42 (QSPI_INST_NODE_HAS_PROP_EQ_AND_OR(n, readoc, 3) \
43 QSPI_INST_NODE_HAS_PROP_EQ_AND_OR(n, readoc, 4) \
44 QSPI_INST_NODE_HAS_PROP_EQ_AND_OR(n, writeoc, 2) \
45 QSPI_INST_NODE_HAS_PROP_EQ_AND_OR(n, writeoc, 3) \
46 0)
47
48 #define QSPI_WRITE_SEQ(n) \
49 COND_CODE_1(DT_INST_NODE_HAS_PROP(n, writeoc), \
50 (_CONCAT(QSPI_SEQ_PP_, DT_INST_STRING_UPPER_TOKEN(n, writeoc))),\
51 (QSPI_SEQ_PP_1_1_1))
52
53 #define QSPI_READ_SEQ(n) \
54 COND_CODE_1(DT_INST_NODE_HAS_PROP(n, readoc), \
55 (_CONCAT(QSPI_SEQ_READ_, DT_INST_STRING_UPPER_TOKEN(n, readoc))),\
56 (QSPI_SEQ_READ_1_1_1))
57
58 #define QSPI_ERASE_VALUE 0xff
59 #define QSPI_WRITE_BLOCK_SIZE 1U
60
61 #define QSPI_IS_ALIGNED(addr, bits) (((addr) & BIT_MASK(bits)) == 0)
62
63 #define QSPI_LUT_ENTRY_SIZE (FEATURE_QSPI_LUT_SEQUENCE_SIZE * 2)
64 #define QSPI_LUT_IDX(n) (n * QSPI_LUT_ENTRY_SIZE)
65
66 #if defined(CONFIG_FLASH_NXP_S32_QSPI_NOR_SFDP_RUNTIME)
67 /* Size of LUT */
68 #define QSPI_SFDP_LUT_SIZE 130U
69 /* Size of init operations */
70 #define QSPI_SFDP_INIT_OP_SIZE 8U
71 #if defined(CONFIG_FLASH_JESD216_API)
72 /* Size of all LUT sequences for JESD216 operations */
73 #define QSPI_JESD216_SEQ_SIZE 8U
74 #endif /* CONFIG_FLASH_JESD216_API */
75 #endif /* CONFIG_FLASH_NXP_S32_QSPI_NOR_SFDP_RUNTIME */
76
77 struct nxp_s32_qspi_config {
78 const struct device *controller;
79 struct flash_parameters flash_parameters;
80 #if defined(CONFIG_FLASH_PAGE_LAYOUT)
81 struct flash_pages_layout layout;
82 #endif
83 #if !defined(CONFIG_FLASH_NXP_S32_QSPI_NOR_SFDP_RUNTIME)
84 const Qspi_Ip_MemoryConfigType memory_cfg;
85 enum jesd216_dw15_qer_type qer_type;
86 bool quad_mode;
87 #endif
88 };
89
90 struct nxp_s32_qspi_data {
91 uint8_t instance;
92 Qspi_Ip_MemoryConnectionType memory_conn_cfg;
93 uint8_t read_sfdp_lut_idx;
94 #if defined(CONFIG_FLASH_NXP_S32_QSPI_NOR_SFDP_RUNTIME)
95 Qspi_Ip_MemoryConfigType memory_cfg;
96 Qspi_Ip_InstrOpType lut_ops[QSPI_SFDP_LUT_SIZE];
97 Qspi_Ip_InitOperationType init_ops[QSPI_SFDP_INIT_OP_SIZE];
98 #endif
99 #if defined(CONFIG_MULTITHREADING)
100 struct k_sem sem;
101 #endif
102 };
103
104 enum {
105 QSPI_SEQ_RDSR,
106 QSPI_SEQ_RDSR2,
107 QSPI_SEQ_WRSR,
108 QSPI_SEQ_WRSR2,
109 QSPI_SEQ_WREN,
110 QSPI_SEQ_RESET,
111 QSPI_SEQ_SE,
112 #if DT_ANY_INST_HAS_PROP_STATUS_OKAY(has_32k_erase)
113 QSPI_SEQ_BE_32K,
114 #endif
115 QSPI_SEQ_BE,
116 QSPI_SEQ_CE,
117 QSPI_SEQ_READ_SFDP,
118 QSPI_SEQ_RDID,
119 #if QSPI_ANY_INST_HAS_PROP_EQ(readoc, 0) || QSPI_ANY_INST_HAS_PROP_STATUS_NOT_OKAY(readoc)
120 QSPI_SEQ_READ_1_1_1,
121 #endif
122 #if QSPI_ANY_INST_HAS_PROP_EQ(readoc, 1)
123 QSPI_SEQ_READ_1_1_2,
124 #endif
125 #if QSPI_ANY_INST_HAS_PROP_EQ(readoc, 2)
126 QSPI_SEQ_READ_1_2_2,
127 #endif
128 #if QSPI_ANY_INST_HAS_PROP_EQ(readoc, 3)
129 QSPI_SEQ_READ_1_1_4,
130 #endif
131 #if QSPI_ANY_INST_HAS_PROP_EQ(readoc, 4)
132 QSPI_SEQ_READ_1_4_4,
133 #endif
134 #if QSPI_ANY_INST_HAS_PROP_EQ(writeoc, 0) || QSPI_ANY_INST_HAS_PROP_STATUS_NOT_OKAY(writeoc)
135 QSPI_SEQ_PP_1_1_1,
136 #endif
137 #if QSPI_ANY_INST_HAS_PROP_EQ(writeoc, 1)
138 QSPI_SEQ_PP_1_1_2,
139 #endif
140 #if QSPI_ANY_INST_HAS_PROP_EQ(writeoc, 2)
141 QSPI_SEQ_PP_1_1_4,
142 #endif
143 #if QSPI_ANY_INST_HAS_PROP_EQ(writeoc, 3)
144 QSPI_SEQ_PP_1_4_4,
145 #endif
146 };
147
148 #if !defined(CONFIG_FLASH_NXP_S32_QSPI_NOR_SFDP_RUNTIME)
149 static const Qspi_Ip_InstrOpType nxp_s32_qspi_lut[][QSPI_LUT_ENTRY_SIZE] = {
150 [QSPI_SEQ_RDSR] = {
151 QSPI_LUT_OP(QSPI_IP_LUT_INSTR_CMD, QSPI_IP_LUT_PADS_1, SPI_NOR_CMD_RDSR),
152 QSPI_LUT_OP(QSPI_IP_LUT_INSTR_READ, QSPI_IP_LUT_PADS_1, 1U),
153 QSPI_LUT_OP(QSPI_IP_LUT_INSTR_STOP, QSPI_IP_LUT_SEQ_END, QSPI_IP_LUT_SEQ_END),
154 },
155
156 [QSPI_SEQ_RDSR2] = {
157 QSPI_LUT_OP(QSPI_IP_LUT_INSTR_CMD, QSPI_IP_LUT_PADS_1, SPI_NOR_CMD_RDSR2),
158 QSPI_LUT_OP(QSPI_IP_LUT_INSTR_READ, QSPI_IP_LUT_PADS_1, 1U),
159 QSPI_LUT_OP(QSPI_IP_LUT_INSTR_STOP, QSPI_IP_LUT_SEQ_END, QSPI_IP_LUT_SEQ_END),
160 },
161
162 [QSPI_SEQ_WRSR] = {
163 QSPI_LUT_OP(QSPI_IP_LUT_INSTR_CMD, QSPI_IP_LUT_PADS_1, SPI_NOR_CMD_WRSR),
164 QSPI_LUT_OP(QSPI_IP_LUT_INSTR_WRITE, QSPI_IP_LUT_PADS_1, 1U),
165 QSPI_LUT_OP(QSPI_IP_LUT_INSTR_STOP, QSPI_IP_LUT_SEQ_END, QSPI_IP_LUT_SEQ_END),
166 },
167
168 [QSPI_SEQ_WRSR2] = {
169 QSPI_LUT_OP(QSPI_IP_LUT_INSTR_CMD, QSPI_IP_LUT_PADS_1, SPI_NOR_CMD_WRSR2),
170 QSPI_LUT_OP(QSPI_IP_LUT_INSTR_WRITE, QSPI_IP_LUT_PADS_1, 1U),
171 QSPI_LUT_OP(QSPI_IP_LUT_INSTR_STOP, QSPI_IP_LUT_SEQ_END, QSPI_IP_LUT_SEQ_END),
172 },
173
174 [QSPI_SEQ_WREN] = {
175 QSPI_LUT_OP(QSPI_IP_LUT_INSTR_CMD, QSPI_IP_LUT_PADS_1, SPI_NOR_CMD_WREN),
176 QSPI_LUT_OP(QSPI_IP_LUT_INSTR_STOP, QSPI_IP_LUT_SEQ_END, QSPI_IP_LUT_SEQ_END),
177 },
178
179 [QSPI_SEQ_RESET] = {
180 QSPI_LUT_OP(QSPI_IP_LUT_INSTR_CMD, QSPI_IP_LUT_PADS_1, SPI_NOR_CMD_RESET_EN),
181 QSPI_LUT_OP(QSPI_IP_LUT_INSTR_STOP, QSPI_IP_LUT_PADS_1, 0U),
182 QSPI_LUT_OP(QSPI_IP_LUT_INSTR_CMD, QSPI_IP_LUT_PADS_1, SPI_NOR_CMD_RESET_MEM),
183 QSPI_LUT_OP(QSPI_IP_LUT_INSTR_STOP, QSPI_IP_LUT_PADS_1, 0U),
184 },
185
186 [QSPI_SEQ_SE] = {
187 QSPI_LUT_OP(QSPI_IP_LUT_INSTR_CMD, QSPI_IP_LUT_PADS_1, SPI_NOR_CMD_SE),
188 QSPI_LUT_OP(QSPI_IP_LUT_INSTR_ADDR, QSPI_IP_LUT_PADS_1, 24U),
189 QSPI_LUT_OP(QSPI_IP_LUT_INSTR_STOP, QSPI_IP_LUT_SEQ_END, QSPI_IP_LUT_SEQ_END),
190 },
191
192 #if DT_ANY_INST_HAS_PROP_STATUS_OKAY(has_32k_erase)
193 [QSPI_SEQ_BE_32K] = {
194 QSPI_LUT_OP(QSPI_IP_LUT_INSTR_CMD, QSPI_IP_LUT_PADS_1, SPI_NOR_CMD_BE_32K),
195 QSPI_LUT_OP(QSPI_IP_LUT_INSTR_ADDR, QSPI_IP_LUT_PADS_1, 24U),
196 QSPI_LUT_OP(QSPI_IP_LUT_INSTR_STOP, QSPI_IP_LUT_SEQ_END, QSPI_IP_LUT_SEQ_END),
197 },
198 #endif
199
200 [QSPI_SEQ_BE] = {
201 QSPI_LUT_OP(QSPI_IP_LUT_INSTR_CMD, QSPI_IP_LUT_PADS_1, SPI_NOR_CMD_BE),
202 QSPI_LUT_OP(QSPI_IP_LUT_INSTR_ADDR, QSPI_IP_LUT_PADS_1, 24U),
203 QSPI_LUT_OP(QSPI_IP_LUT_INSTR_STOP, QSPI_IP_LUT_SEQ_END, QSPI_IP_LUT_SEQ_END),
204 },
205
206 [QSPI_SEQ_CE] = {
207 QSPI_LUT_OP(QSPI_IP_LUT_INSTR_CMD, QSPI_IP_LUT_PADS_1, SPI_NOR_CMD_CE),
208 QSPI_LUT_OP(QSPI_IP_LUT_INSTR_STOP, QSPI_IP_LUT_SEQ_END, QSPI_IP_LUT_SEQ_END),
209 },
210
211 [QSPI_SEQ_READ_SFDP] = {
212 QSPI_LUT_OP(QSPI_IP_LUT_INSTR_CMD, QSPI_IP_LUT_PADS_1, JESD216_CMD_READ_SFDP),
213 QSPI_LUT_OP(QSPI_IP_LUT_INSTR_ADDR, QSPI_IP_LUT_PADS_1, 24U),
214 QSPI_LUT_OP(QSPI_IP_LUT_INSTR_DUMMY, QSPI_IP_LUT_PADS_1, 8U),
215 QSPI_LUT_OP(QSPI_IP_LUT_INSTR_READ, QSPI_IP_LUT_PADS_1, 16U),
216 QSPI_LUT_OP(QSPI_IP_LUT_INSTR_STOP, QSPI_IP_LUT_SEQ_END, QSPI_IP_LUT_SEQ_END),
217 },
218
219 [QSPI_SEQ_RDID] = {
220 QSPI_LUT_OP(QSPI_IP_LUT_INSTR_CMD, QSPI_IP_LUT_PADS_1, JESD216_CMD_READ_ID),
221 QSPI_LUT_OP(QSPI_IP_LUT_INSTR_READ, QSPI_IP_LUT_PADS_1, JESD216_READ_ID_LEN),
222 QSPI_LUT_OP(QSPI_IP_LUT_INSTR_STOP, QSPI_IP_LUT_SEQ_END, QSPI_IP_LUT_SEQ_END),
223 },
224
225 #if QSPI_ANY_INST_HAS_PROP_EQ(readoc, 0) || QSPI_ANY_INST_HAS_PROP_STATUS_NOT_OKAY(readoc)
226 [QSPI_SEQ_READ_1_1_1] = {
227 QSPI_LUT_OP(QSPI_IP_LUT_INSTR_CMD, QSPI_IP_LUT_PADS_1, SPI_NOR_CMD_READ_FAST),
228 QSPI_LUT_OP(QSPI_IP_LUT_INSTR_ADDR, QSPI_IP_LUT_PADS_1, 24U),
229 QSPI_LUT_OP(QSPI_IP_LUT_INSTR_DUMMY, QSPI_IP_LUT_PADS_1, 8U),
230 QSPI_LUT_OP(QSPI_IP_LUT_INSTR_READ, QSPI_IP_LUT_PADS_1, 8U),
231 QSPI_LUT_OP(QSPI_IP_LUT_INSTR_STOP, QSPI_IP_LUT_SEQ_END, QSPI_IP_LUT_SEQ_END),
232 },
233 #endif
234
235 #if QSPI_ANY_INST_HAS_PROP_EQ(readoc, 1)
236 [QSPI_SEQ_READ_1_1_2] = {
237 QSPI_LUT_OP(QSPI_IP_LUT_INSTR_CMD, QSPI_IP_LUT_PADS_1, SPI_NOR_CMD_DREAD),
238 QSPI_LUT_OP(QSPI_IP_LUT_INSTR_ADDR, QSPI_IP_LUT_PADS_1, 24U),
239 QSPI_LUT_OP(QSPI_IP_LUT_INSTR_DUMMY, QSPI_IP_LUT_PADS_1, 8U),
240 QSPI_LUT_OP(QSPI_IP_LUT_INSTR_READ, QSPI_IP_LUT_PADS_2, 8U),
241 QSPI_LUT_OP(QSPI_IP_LUT_INSTR_STOP, QSPI_IP_LUT_SEQ_END, QSPI_IP_LUT_SEQ_END),
242 },
243 #endif
244
245 #if QSPI_ANY_INST_HAS_PROP_EQ(readoc, 2)
246 [QSPI_SEQ_READ_1_2_2] = {
247 QSPI_LUT_OP(QSPI_IP_LUT_INSTR_CMD, QSPI_IP_LUT_PADS_1, SPI_NOR_CMD_2READ),
248 QSPI_LUT_OP(QSPI_IP_LUT_INSTR_ADDR, QSPI_IP_LUT_PADS_2, 24U),
249 QSPI_LUT_OP(QSPI_IP_LUT_INSTR_DUMMY, QSPI_IP_LUT_PADS_2, 4U),
250 QSPI_LUT_OP(QSPI_IP_LUT_INSTR_READ, QSPI_IP_LUT_PADS_2, 8U),
251 QSPI_LUT_OP(QSPI_IP_LUT_INSTR_STOP, QSPI_IP_LUT_SEQ_END, QSPI_IP_LUT_SEQ_END),
252 },
253 #endif
254
255 #if QSPI_ANY_INST_HAS_PROP_EQ(readoc, 3)
256 [QSPI_SEQ_READ_1_1_4] = {
257 QSPI_LUT_OP(QSPI_IP_LUT_INSTR_CMD, QSPI_IP_LUT_PADS_1, SPI_NOR_CMD_QREAD),
258 QSPI_LUT_OP(QSPI_IP_LUT_INSTR_ADDR, QSPI_IP_LUT_PADS_1, 24U),
259 QSPI_LUT_OP(QSPI_IP_LUT_INSTR_DUMMY, QSPI_IP_LUT_PADS_1, 8U),
260 QSPI_LUT_OP(QSPI_IP_LUT_INSTR_READ, QSPI_IP_LUT_PADS_4, 8U),
261 QSPI_LUT_OP(QSPI_IP_LUT_INSTR_STOP, QSPI_IP_LUT_SEQ_END, QSPI_IP_LUT_SEQ_END),
262 },
263 #endif
264
265 #if QSPI_ANY_INST_HAS_PROP_EQ(readoc, 4)
266 [QSPI_SEQ_READ_1_4_4] = {
267 QSPI_LUT_OP(QSPI_IP_LUT_INSTR_CMD, QSPI_IP_LUT_PADS_1, SPI_NOR_CMD_4READ),
268 QSPI_LUT_OP(QSPI_IP_LUT_INSTR_ADDR, QSPI_IP_LUT_PADS_4, 24U),
269 QSPI_LUT_OP(QSPI_IP_LUT_INSTR_MODE, QSPI_IP_LUT_PADS_4, 0U),
270 QSPI_LUT_OP(QSPI_IP_LUT_INSTR_DUMMY, QSPI_IP_LUT_PADS_4, 4U),
271 QSPI_LUT_OP(QSPI_IP_LUT_INSTR_READ, QSPI_IP_LUT_PADS_4, 8U),
272 QSPI_LUT_OP(QSPI_IP_LUT_INSTR_STOP, QSPI_IP_LUT_SEQ_END, QSPI_IP_LUT_SEQ_END),
273 },
274 #endif
275
276 #if QSPI_ANY_INST_HAS_PROP_EQ(writeoc, 0) || QSPI_ANY_INST_HAS_PROP_STATUS_NOT_OKAY(writeoc)
277 [QSPI_SEQ_PP_1_1_1] = {
278 QSPI_LUT_OP(QSPI_IP_LUT_INSTR_CMD, QSPI_IP_LUT_PADS_1, SPI_NOR_CMD_PP),
279 QSPI_LUT_OP(QSPI_IP_LUT_INSTR_ADDR, QSPI_IP_LUT_PADS_1, 24U),
280 QSPI_LUT_OP(QSPI_IP_LUT_INSTR_WRITE, QSPI_IP_LUT_PADS_1, 8U),
281 QSPI_LUT_OP(QSPI_IP_LUT_INSTR_STOP, QSPI_IP_LUT_SEQ_END, QSPI_IP_LUT_SEQ_END),
282 },
283 #endif
284
285 #if QSPI_ANY_INST_HAS_PROP_EQ(writeoc, 1)
286 [QSPI_SEQ_PP_1_1_2] = {
287 QSPI_LUT_OP(QSPI_IP_LUT_INSTR_CMD, QSPI_IP_LUT_PADS_1, SPI_NOR_CMD_PP_1_1_2),
288 QSPI_LUT_OP(QSPI_IP_LUT_INSTR_ADDR, QSPI_IP_LUT_PADS_1, 24U),
289 QSPI_LUT_OP(QSPI_IP_LUT_INSTR_WRITE, QSPI_IP_LUT_PADS_2, 8U),
290 QSPI_LUT_OP(QSPI_IP_LUT_INSTR_STOP, QSPI_IP_LUT_SEQ_END, QSPI_IP_LUT_SEQ_END),
291 },
292 #endif
293
294 #if QSPI_ANY_INST_HAS_PROP_EQ(writeoc, 2)
295 [QSPI_SEQ_PP_1_1_4] = {
296 QSPI_LUT_OP(QSPI_IP_LUT_INSTR_CMD, QSPI_IP_LUT_PADS_1, SPI_NOR_CMD_PP_1_1_4),
297 QSPI_LUT_OP(QSPI_IP_LUT_INSTR_ADDR, QSPI_IP_LUT_PADS_1, 24U),
298 QSPI_LUT_OP(QSPI_IP_LUT_INSTR_WRITE, QSPI_IP_LUT_PADS_4, 8U),
299 QSPI_LUT_OP(QSPI_IP_LUT_INSTR_STOP, QSPI_IP_LUT_SEQ_END, QSPI_IP_LUT_SEQ_END),
300 },
301 #endif
302
303 #if QSPI_ANY_INST_HAS_PROP_EQ(writeoc, 3)
304 [QSPI_SEQ_PP_1_4_4] = {
305 QSPI_LUT_OP(QSPI_IP_LUT_INSTR_CMD, QSPI_IP_LUT_PADS_1, SPI_NOR_CMD_PP_1_4_4),
306 QSPI_LUT_OP(QSPI_IP_LUT_INSTR_ADDR, QSPI_IP_LUT_PADS_4, 24U),
307 QSPI_LUT_OP(QSPI_IP_LUT_INSTR_WRITE, QSPI_IP_LUT_PADS_4, 16U),
308 QSPI_LUT_OP(QSPI_IP_LUT_INSTR_STOP, QSPI_IP_LUT_SEQ_END, QSPI_IP_LUT_SEQ_END),
309 },
310 #endif
311 };
312 #endif /* !defined(CONFIG_FLASH_NXP_S32_QSPI_NOR_SFDP_RUNTIME) */
313
get_memory_config(const struct device * dev)314 static ALWAYS_INLINE Qspi_Ip_MemoryConfigType *get_memory_config(const struct device *dev)
315 {
316 #if defined(CONFIG_FLASH_NXP_S32_QSPI_NOR_SFDP_RUNTIME)
317 return &((struct nxp_s32_qspi_data *)dev->data)->memory_cfg;
318 #else
319 return ((Qspi_Ip_MemoryConfigType *)
320 &((const struct nxp_s32_qspi_config *)dev->config)->memory_cfg);
321 #endif
322 }
323
area_is_subregion(const struct device * dev,off_t offset,size_t size)324 static ALWAYS_INLINE bool area_is_subregion(const struct device *dev, off_t offset, size_t size)
325 {
326 Qspi_Ip_MemoryConfigType *memory_cfg = get_memory_config(dev);
327
328 return ((offset >= 0) && (offset < memory_cfg->memSize)
329 && ((size + offset) <= memory_cfg->memSize));
330 }
331
nxp_s32_qspi_lock(const struct device * dev)332 static inline void nxp_s32_qspi_lock(const struct device *dev)
333 {
334 #ifdef CONFIG_MULTITHREADING
335 struct nxp_s32_qspi_data *data = dev->data;
336
337 k_sem_take(&data->sem, K_FOREVER);
338 #else
339 ARG_UNUSED(dev);
340 #endif
341 }
342
nxp_s32_qspi_unlock(const struct device * dev)343 static inline void nxp_s32_qspi_unlock(const struct device *dev)
344 {
345 #ifdef CONFIG_MULTITHREADING
346 struct nxp_s32_qspi_data *data = dev->data;
347
348 k_sem_give(&data->sem);
349 #else
350 ARG_UNUSED(dev);
351 #endif
352 }
353
354 /* Must be called with lock */
nxp_s32_qspi_wait_until_ready(const struct device * dev)355 static int nxp_s32_qspi_wait_until_ready(const struct device *dev)
356 {
357 struct nxp_s32_qspi_data *data = dev->data;
358 Qspi_Ip_StatusType status;
359 uint32_t timeout = 0xFFFFFF;
360 int ret = 0;
361
362 do {
363 status = Qspi_Ip_GetMemoryStatus(data->instance);
364 timeout--;
365 } while ((status == STATUS_QSPI_IP_BUSY) && (timeout > 0));
366
367 if (status != STATUS_QSPI_IP_SUCCESS) {
368 LOG_ERR("Failed to read memory status (%d)", status);
369 ret = -EIO;
370 } else if (timeout <= 0) {
371 LOG_ERR("Timeout, memory is busy");
372 ret = -ETIMEDOUT;
373 }
374
375 return ret;
376 }
377
378 #if !defined(CONFIG_FLASH_NXP_S32_QSPI_NOR_SFDP_RUNTIME)
nxp_s32_qspi_read_status_register(const struct device * dev,uint8_t reg_num,uint8_t * val)379 static int nxp_s32_qspi_read_status_register(const struct device *dev,
380 uint8_t reg_num,
381 uint8_t *val)
382 {
383 struct nxp_s32_qspi_data *data = dev->data;
384 uint16_t lut_idx;
385 Qspi_Ip_StatusType status;
386 int ret = 0;
387
388 switch (reg_num) {
389 case 1U:
390 lut_idx = QSPI_LUT_IDX(QSPI_SEQ_RDSR);
391 break;
392 case 2U:
393 lut_idx = QSPI_LUT_IDX(QSPI_SEQ_RDSR2);
394 break;
395 default:
396 LOG_ERR("Reading SR%u is not supported", reg_num);
397 return -EINVAL;
398 }
399
400 nxp_s32_qspi_lock(dev);
401
402 status = Qspi_Ip_RunReadCommand(data->instance, lut_idx, 0U, val, NULL, sizeof(*val));
403 if (status != STATUS_QSPI_IP_SUCCESS) {
404 LOG_ERR("Failed to read SR%u (%d)", reg_num, status);
405 ret = -EIO;
406 }
407
408 nxp_s32_qspi_unlock(dev);
409
410 return ret;
411 }
412
nxp_s32_qspi_write_enable(const struct device * dev)413 static int nxp_s32_qspi_write_enable(const struct device *dev)
414 {
415 struct nxp_s32_qspi_data *data = dev->data;
416 Qspi_Ip_MemoryConfigType *memory_cfg = get_memory_config(dev);
417 Qspi_Ip_StatusType status;
418 int ret = 0;
419
420 nxp_s32_qspi_lock(dev);
421
422 status = Qspi_Ip_RunCommand(data->instance, memory_cfg->statusConfig.writeEnableSRLut, 0U);
423 if (status != STATUS_QSPI_IP_SUCCESS) {
424 LOG_ERR("Failed to enable SR write (%d)", status);
425 ret = -EIO;
426 }
427
428 nxp_s32_qspi_unlock(dev);
429
430 return ret;
431 }
432
nxp_s32_qspi_write_status_register(const struct device * dev,uint8_t reg_num,uint8_t val)433 static int nxp_s32_qspi_write_status_register(const struct device *dev,
434 uint8_t reg_num,
435 uint8_t val)
436 {
437 const struct nxp_s32_qspi_config *config = dev->config;
438 struct nxp_s32_qspi_data *data = dev->data;
439 Qspi_Ip_StatusType status;
440 uint8_t buf[2] = { 0 };
441 uint16_t lut_idx;
442 size_t size;
443 int ret;
444
445 if (reg_num == 1) {
446 /* buf = [val] or [val, SR2] */
447 lut_idx = QSPI_LUT_IDX(QSPI_SEQ_WRSR);
448 size = 1U;
449 buf[0] = val;
450
451 if (config->qer_type == JESD216_DW15_QER_S2B1v1) {
452 /* Writing SR1 clears SR2 */
453 size = 2U;
454 ret = nxp_s32_qspi_read_status_register(dev, 2, &buf[1]);
455 if (ret < 0) {
456 return ret;
457 }
458 }
459 } else if (reg_num == 2) {
460 /* buf = [val] or [SR1, val] */
461 if ((config->qer_type == JESD216_DW15_QER_VAL_S2B1v1) ||
462 (config->qer_type == JESD216_DW15_QER_VAL_S2B1v4) ||
463 (config->qer_type == JESD216_DW15_QER_VAL_S2B1v5)) {
464 /* Writing SR2 requires writing SR1 as well */
465 lut_idx = QSPI_LUT_IDX(QSPI_SEQ_WRSR);
466 size = 2U;
467 buf[1] = val;
468 ret = nxp_s32_qspi_read_status_register(dev, 1, &buf[0]);
469 if (ret < 0) {
470 return ret;
471 }
472 } else {
473 lut_idx = QSPI_LUT_IDX(QSPI_SEQ_WRSR2);
474 size = 1U;
475 buf[0] = val;
476 }
477 } else {
478 return -EINVAL;
479 }
480
481 nxp_s32_qspi_lock(dev);
482
483 status = Qspi_Ip_RunWriteCommand(data->instance, lut_idx, 0U, (const uint8_t *)buf,
484 (uint32_t)size);
485 if (status == STATUS_QSPI_IP_SUCCESS) {
486 /* Wait for the write command to complete */
487 ret = nxp_s32_qspi_wait_until_ready(dev);
488 } else {
489 LOG_ERR("Failed to write to SR%u (%d)", reg_num, status);
490 ret = -EIO;
491 }
492
493 nxp_s32_qspi_unlock(dev);
494
495 return ret;
496 }
497
nxp_s32_qspi_set_quad_mode(const struct device * dev,bool enabled)498 static int nxp_s32_qspi_set_quad_mode(const struct device *dev, bool enabled)
499 {
500 const struct nxp_s32_qspi_config *config = dev->config;
501 uint8_t sr_num;
502 uint8_t sr_val;
503 uint8_t qe_mask;
504 bool qe_state;
505 int ret;
506
507 switch (config->qer_type) {
508 case JESD216_DW15_QER_NONE:
509 /* no QE bit, device detects reads based on opcode */
510 return 0;
511 case JESD216_DW15_QER_S1B6:
512 sr_num = 1U;
513 qe_mask = BIT(6U);
514 break;
515 case JESD216_DW15_QER_S2B7:
516 sr_num = 2U;
517 qe_mask = BIT(7U);
518 break;
519 case JESD216_DW15_QER_S2B1v1:
520 __fallthrough;
521 case JESD216_DW15_QER_S2B1v4:
522 __fallthrough;
523 case JESD216_DW15_QER_S2B1v5:
524 __fallthrough;
525 case JESD216_DW15_QER_S2B1v6:
526 sr_num = 2U;
527 qe_mask = BIT(1U);
528 break;
529 default:
530 return -ENOTSUP;
531 }
532
533 ret = nxp_s32_qspi_read_status_register(dev, sr_num, &sr_val);
534 if (ret < 0) {
535 return ret;
536 }
537
538 qe_state = ((sr_val & qe_mask) != 0U);
539 if (qe_state == enabled) {
540 return 0;
541 }
542 sr_val ^= qe_mask;
543
544 ret = nxp_s32_qspi_write_enable(dev);
545 if (ret < 0) {
546 return ret;
547 }
548
549 ret = nxp_s32_qspi_write_status_register(dev, sr_num, sr_val);
550 if (ret < 0) {
551 return ret;
552 }
553
554 /* Verify write was successful */
555 ret = nxp_s32_qspi_read_status_register(dev, sr_num, &sr_val);
556 if (ret < 0) {
557 return ret;
558 }
559
560 qe_state = ((sr_val & qe_mask) != 0U);
561 if (qe_state != enabled) {
562 LOG_ERR("Failed to %s Quad mode", enabled ? "enable" : "disable");
563 return -EIO;
564 }
565
566 return ret;
567 }
568 #endif /* !defined(CONFIG_FLASH_NXP_S32_QSPI_NOR_SFDP_RUNTIME) */
569
nxp_s32_qspi_read(const struct device * dev,off_t offset,void * dest,size_t size)570 static int nxp_s32_qspi_read(const struct device *dev, off_t offset, void *dest, size_t size)
571 {
572 struct nxp_s32_qspi_data *data = dev->data;
573 Qspi_Ip_StatusType status;
574 int ret = 0;
575
576 if (!dest) {
577 return -EINVAL;
578 }
579
580 if (!area_is_subregion(dev, offset, size)) {
581 return -ENODEV;
582 }
583
584 if (size) {
585 nxp_s32_qspi_lock(dev);
586
587 status = Qspi_Ip_Read(data->instance, (uint32_t)offset, (uint8_t *)dest,
588 (uint32_t)size);
589 if (status != STATUS_QSPI_IP_SUCCESS) {
590 LOG_ERR("Failed to read %zu bytes at 0x%lx (%d)",
591 size, offset, status);
592 ret = -EIO;
593 }
594
595 nxp_s32_qspi_unlock(dev);
596 }
597
598 return ret;
599 }
600
nxp_s32_qspi_write(const struct device * dev,off_t offset,const void * src,size_t size)601 static int nxp_s32_qspi_write(const struct device *dev, off_t offset, const void *src, size_t size)
602 {
603 struct nxp_s32_qspi_data *data = dev->data;
604 Qspi_Ip_MemoryConfigType *memory_cfg = get_memory_config(dev);
605 Qspi_Ip_StatusType status;
606 size_t max_write = (size_t)MIN(QSPI_IP_MAX_WRITE_SIZE, memory_cfg->pageSize);
607 size_t len;
608 int ret = 0;
609
610 if (!src) {
611 return -EINVAL;
612 }
613
614 if (!area_is_subregion(dev, offset, size)) {
615 return -ENODEV;
616 }
617
618 nxp_s32_qspi_lock(dev);
619
620 while (size) {
621 len = MIN(max_write - (offset % max_write), size);
622 status = Qspi_Ip_Program(data->instance, (uint32_t)offset,
623 (const uint8_t *)src, (uint32_t)len);
624 if (status != STATUS_QSPI_IP_SUCCESS) {
625 LOG_ERR("Failed to write %zu bytes at 0x%lx (%d)",
626 len, offset, status);
627 ret = -EIO;
628 break;
629 }
630
631 ret = nxp_s32_qspi_wait_until_ready(dev);
632 if (ret != 0) {
633 break;
634 }
635
636 if (IS_ENABLED(CONFIG_FLASH_NXP_S32_QSPI_VERIFY_WRITE)) {
637 status = Qspi_Ip_ProgramVerify(data->instance, (uint32_t)offset,
638 (const uint8_t *)src, (uint32_t)len);
639 if (status != STATUS_QSPI_IP_SUCCESS) {
640 LOG_ERR("Write verification failed at 0x%lx (%d)",
641 offset, status);
642 ret = -EIO;
643 break;
644 }
645 }
646
647 size -= len;
648 src = (const uint8_t *)src + len;
649 offset += len;
650 }
651
652 nxp_s32_qspi_unlock(dev);
653
654 return ret;
655 }
656
nxp_s32_qspi_erase_block(const struct device * dev,off_t offset,size_t size,size_t * erase_size)657 static int nxp_s32_qspi_erase_block(const struct device *dev, off_t offset,
658 size_t size, size_t *erase_size)
659 {
660 struct nxp_s32_qspi_data *data = dev->data;
661 Qspi_Ip_MemoryConfigType *memory_cfg = get_memory_config(dev);
662 Qspi_Ip_EraseVarConfigType *etp = NULL;
663 Qspi_Ip_EraseVarConfigType *etp_tmp;
664 Qspi_Ip_StatusType status;
665 int ret = 0;
666
667 /*
668 * Find the erase type with bigger size that can erase all or part of the
669 * requested memory size
670 */
671 for (uint8_t i = 0; i < QSPI_IP_ERASE_TYPES; i++) {
672 etp_tmp = (Qspi_Ip_EraseVarConfigType *)&(memory_cfg->eraseSettings.eraseTypes[i]);
673 if ((etp_tmp->eraseLut != QSPI_IP_LUT_INVALID)
674 && QSPI_IS_ALIGNED(offset, etp_tmp->size)
675 && (BIT(etp_tmp->size) <= size)
676 && ((etp == NULL) || (etp_tmp->size > etp->size))) {
677
678 etp = etp_tmp;
679 }
680 }
681 if (etp != NULL) {
682 *erase_size = BIT(etp->size);
683 status = Qspi_Ip_EraseBlock(data->instance, (uint32_t)offset, *erase_size);
684 if (status != STATUS_QSPI_IP_SUCCESS) {
685 LOG_ERR("Failed to erase %zu bytes at 0x%lx (%d)",
686 *erase_size, (long)offset, status);
687 ret = -EIO;
688 }
689 } else {
690 LOG_ERR("Can't find erase size to erase %zu bytes", size);
691 ret = -EINVAL;
692 }
693
694 return ret;
695 }
696
nxp_s32_qspi_erase(const struct device * dev,off_t offset,size_t size)697 static int nxp_s32_qspi_erase(const struct device *dev, off_t offset, size_t size)
698 {
699 struct nxp_s32_qspi_data *data = dev->data;
700 Qspi_Ip_MemoryConfigType *memory_cfg = get_memory_config(dev);
701 Qspi_Ip_StatusType status;
702 size_t erase_size;
703 int ret = 0;
704
705 if (!area_is_subregion(dev, offset, size)) {
706 return -ENODEV;
707 }
708
709 nxp_s32_qspi_lock(dev);
710
711 if (size == memory_cfg->memSize) {
712 status = Qspi_Ip_EraseChip(data->instance);
713 if (status != STATUS_QSPI_IP_SUCCESS) {
714 LOG_ERR("Failed to erase chip (%d)", status);
715 ret = -EIO;
716 }
717 } else {
718 while (size > 0) {
719 erase_size = 0;
720
721 ret = nxp_s32_qspi_erase_block(dev, offset, size, &erase_size);
722 if (ret != 0) {
723 break;
724 }
725
726 ret = nxp_s32_qspi_wait_until_ready(dev);
727 if (ret != 0) {
728 break;
729 }
730
731 if (IS_ENABLED(CONFIG_FLASH_NXP_S32_QSPI_VERIFY_ERASE)) {
732 status = Qspi_Ip_EraseVerify(data->instance, (uint32_t)offset,
733 erase_size);
734 if (status != STATUS_QSPI_IP_SUCCESS) {
735 LOG_ERR("Erase verification failed at 0x%lx (%d)",
736 offset, status);
737 ret = -EIO;
738 break;
739 }
740 }
741
742 offset += erase_size;
743 size -= erase_size;
744 }
745 }
746
747 nxp_s32_qspi_unlock(dev);
748
749 return ret;
750 }
751
752 #if defined(CONFIG_FLASH_JESD216_API) || !defined(CONFIG_FLASH_NXP_S32_QSPI_NOR_SFDP_RUNTIME)
nxp_s32_qspi_read_id(const struct device * dev,uint8_t * id)753 static int nxp_s32_qspi_read_id(const struct device *dev, uint8_t *id)
754 {
755 struct nxp_s32_qspi_data *data = dev->data;
756 Qspi_Ip_StatusType status;
757 int ret = 0;
758
759 nxp_s32_qspi_lock(dev);
760
761 status = Qspi_Ip_ReadId(data->instance, id);
762 if (status != STATUS_QSPI_IP_SUCCESS) {
763 LOG_ERR("Failed to read device ID (%d)", status);
764 ret = -EIO;
765 }
766
767 nxp_s32_qspi_unlock(dev);
768
769 return ret;
770 }
771 #endif /* CONFIG_FLASH_JESD216_API || !CONFIG_FLASH_NXP_S32_QSPI_NOR_SFDP_RUNTIME */
772
773 #if defined(CONFIG_FLASH_JESD216_API)
nxp_s32_qspi_sfdp_read(const struct device * dev,off_t offset,void * buf,size_t len)774 static int nxp_s32_qspi_sfdp_read(const struct device *dev, off_t offset, void *buf, size_t len)
775 {
776 struct nxp_s32_qspi_data *data = dev->data;
777 Qspi_Ip_StatusType status;
778 int ret = 0;
779
780 nxp_s32_qspi_lock(dev);
781
782 status = Qspi_Ip_RunReadCommand(data->instance, data->read_sfdp_lut_idx,
783 (uint32_t)offset, (uint8_t *)buf, NULL, (uint32_t)len);
784 if (status != STATUS_QSPI_IP_SUCCESS) {
785 LOG_ERR("Failed to read SFDP at 0x%lx (%d)", offset, status);
786 ret = -EIO;
787 }
788
789 nxp_s32_qspi_unlock(dev);
790
791 return ret;
792 }
793 #endif /* CONFIG_FLASH_JESD216_API */
794
795 #if defined(CONFIG_FLASH_NXP_S32_QSPI_NOR_SFDP_RUNTIME)
nxp_s32_qspi_sfdp_config(const struct device * dev)796 static int nxp_s32_qspi_sfdp_config(const struct device *dev)
797 {
798 struct nxp_s32_qspi_data *data = dev->data;
799 Qspi_Ip_MemoryConfigType *memory_cfg = get_memory_config(dev);
800 Qspi_Ip_StatusType status;
801
802 /* Populate memory configuration with values obtained from SFDP */
803 memory_cfg->memType = QSPI_IP_SERIAL_FLASH;
804 memory_cfg->lutSequences.opCount = QSPI_SFDP_LUT_SIZE;
805 memory_cfg->lutSequences.lutOps = (Qspi_Ip_InstrOpType *)data->lut_ops;
806 memory_cfg->initConfiguration.opCount = QSPI_SFDP_INIT_OP_SIZE;
807 memory_cfg->initConfiguration.operations = (Qspi_Ip_InitOperationType *)data->init_ops;
808
809 status = Qspi_Ip_ReadSfdp(memory_cfg, &data->memory_conn_cfg);
810 if (status != STATUS_QSPI_IP_SUCCESS) {
811 LOG_ERR("Fail to read SFDP (%d)", status);
812 return -EIO;
813 }
814
815 #if defined(CONFIG_FLASH_JESD216_API)
816 /* The HAL does not populate LUTs for read SFDP and read ID */
817 uint8_t lut_idx = QSPI_SFDP_LUT_SIZE;
818
819 for (int i = 0; i < QSPI_SFDP_LUT_SIZE - 1; i++) {
820 if ((data->lut_ops[i] == QSPI_IP_LUT_SEQ_END)
821 && (data->lut_ops[i+1] == QSPI_IP_LUT_SEQ_END)) {
822 lut_idx = i + 1;
823 break;
824 }
825 }
826
827 /* Make sure there's enough space to add the LUT sequences */
828 if ((lut_idx + QSPI_JESD216_SEQ_SIZE - 1) >= QSPI_SFDP_LUT_SIZE) {
829 return -ENOMEM;
830 }
831
832 data->read_sfdp_lut_idx = lut_idx;
833 data->lut_ops[lut_idx++] = QSPI_LUT_OP(QSPI_IP_LUT_INSTR_CMD, QSPI_IP_LUT_PADS_1,
834 JESD216_CMD_READ_SFDP);
835 data->lut_ops[lut_idx++] = QSPI_LUT_OP(QSPI_IP_LUT_INSTR_ADDR, QSPI_IP_LUT_PADS_1, 24U);
836 data->lut_ops[lut_idx++] = QSPI_LUT_OP(QSPI_IP_LUT_INSTR_DUMMY, QSPI_IP_LUT_PADS_1, 8U);
837 data->lut_ops[lut_idx++] = QSPI_LUT_OP(QSPI_IP_LUT_INSTR_READ, QSPI_IP_LUT_PADS_1, 16U);
838 data->lut_ops[lut_idx++] = QSPI_LUT_OP(QSPI_IP_LUT_INSTR_STOP, QSPI_IP_LUT_SEQ_END,
839 QSPI_IP_LUT_SEQ_END);
840
841 memory_cfg->readIdSettings.readIdLut = lut_idx;
842 memory_cfg->readIdSettings.readIdSize = JESD216_READ_ID_LEN;
843 data->lut_ops[lut_idx++] = QSPI_LUT_OP(QSPI_IP_LUT_INSTR_CMD, QSPI_IP_LUT_PADS_1,
844 JESD216_CMD_READ_ID);
845 data->lut_ops[lut_idx++] = QSPI_LUT_OP(QSPI_IP_LUT_INSTR_READ, QSPI_IP_LUT_PADS_1,
846 JESD216_READ_ID_LEN);
847 data->lut_ops[lut_idx++] = QSPI_LUT_OP(QSPI_IP_LUT_INSTR_STOP, QSPI_IP_LUT_SEQ_END,
848 QSPI_IP_LUT_SEQ_END);
849 #endif /* CONFIG_FLASH_JESD216_API */
850
851 return 0;
852 }
853 #endif
854
nxp_s32_qspi_get_parameters(const struct device * dev)855 static const struct flash_parameters *nxp_s32_qspi_get_parameters(const struct device *dev)
856 {
857 const struct nxp_s32_qspi_config *config = dev->config;
858
859 return &config->flash_parameters;
860 }
861
862 #if defined(CONFIG_FLASH_PAGE_LAYOUT)
nxp_s32_qspi_pages_layout(const struct device * dev,const struct flash_pages_layout ** layout,size_t * layout_size)863 static void nxp_s32_qspi_pages_layout(const struct device *dev,
864 const struct flash_pages_layout **layout,
865 size_t *layout_size)
866 {
867 const struct nxp_s32_qspi_config *config = dev->config;
868
869 *layout = &config->layout;
870 *layout_size = 1;
871 }
872 #endif /* CONFIG_FLASH_PAGE_LAYOUT */
873
nxp_s32_qspi_init(const struct device * dev)874 static int nxp_s32_qspi_init(const struct device *dev)
875 {
876 struct nxp_s32_qspi_data *data = dev->data;
877 const struct nxp_s32_qspi_config *config = dev->config;
878 Qspi_Ip_MemoryConfigType *memory_cfg = get_memory_config(dev);
879 Qspi_Ip_StatusType status;
880 static uint8_t instance_cnt;
881 int ret = 0;
882
883 /* Used by the HAL to retrieve the internal driver state */
884 data->instance = instance_cnt++;
885 __ASSERT_NO_MSG(data->instance < QSPI_IP_MEM_INSTANCE_COUNT);
886 data->memory_conn_cfg.qspiInstance = memc_nxp_s32_qspi_get_instance(config->controller);
887
888 #if defined(CONFIG_MULTITHREADING)
889 k_sem_init(&data->sem, 1, 1);
890 #endif
891
892 #if defined(CONFIG_FLASH_NXP_S32_QSPI_NOR_SFDP_RUNTIME)
893 nxp_s32_qspi_sfdp_config(dev);
894 #endif
895
896 /* Init memory device connected to the bus */
897 status = Qspi_Ip_Init(data->instance,
898 (const Qspi_Ip_MemoryConfigType *)memory_cfg,
899 (const Qspi_Ip_MemoryConnectionType *)&data->memory_conn_cfg);
900 if (status != STATUS_QSPI_IP_SUCCESS) {
901 LOG_ERR("Fail to init memory device %d (%d)", data->instance, status);
902 return -EIO;
903 }
904
905
906 #if !defined(CONFIG_FLASH_NXP_S32_QSPI_NOR_SFDP_RUNTIME)
907 uint8_t jedec_id[JESD216_READ_ID_LEN];
908
909 /* Verify connectivity by reading the device ID */
910 ret = nxp_s32_qspi_read_id(dev, jedec_id);
911 if (ret != 0) {
912 LOG_ERR("JEDEC ID read failed (%d)", ret);
913 return -ENODEV;
914 }
915
916 /*
917 * Check the memory device ID against the one configured from devicetree
918 * to verify we are talking to the correct device.
919 */
920 if (memcmp(jedec_id, memory_cfg->readIdSettings.readIdExpected, sizeof(jedec_id)) != 0) {
921 LOG_ERR("Device id %02x %02x %02x does not match config %02x %02x %02x",
922 jedec_id[0], jedec_id[1], jedec_id[2],
923 memory_cfg->readIdSettings.readIdExpected[0],
924 memory_cfg->readIdSettings.readIdExpected[1],
925 memory_cfg->readIdSettings.readIdExpected[2]);
926 return -EINVAL;
927 }
928
929 ret = nxp_s32_qspi_set_quad_mode(dev, config->quad_mode);
930 if (ret < 0) {
931 return ret;
932 }
933 #endif /* !CONFIG_FLASH_NXP_S32_QSPI_NOR_SFDP_RUNTIME */
934
935 return ret;
936 }
937
938 static const struct flash_driver_api nxp_s32_qspi_api = {
939 .erase = nxp_s32_qspi_erase,
940 .write = nxp_s32_qspi_write,
941 .read = nxp_s32_qspi_read,
942 .get_parameters = nxp_s32_qspi_get_parameters,
943 #if defined(CONFIG_FLASH_PAGE_LAYOUT)
944 .page_layout = nxp_s32_qspi_pages_layout,
945 #endif /* CONFIG_FLASH_PAGE_LAYOUT */
946 #if defined(CONFIG_FLASH_JESD216_API)
947 .sfdp_read = nxp_s32_qspi_sfdp_read,
948 .read_jedec_id = nxp_s32_qspi_read_id,
949 #endif /* CONFIG_FLASH_JESD216_API */
950 };
951
952 #define QSPI_PAGE_LAYOUT(n) \
953 .layout = { \
954 .pages_count = (DT_INST_PROP(n, size) / 8) \
955 / CONFIG_FLASH_NXP_S32_QSPI_LAYOUT_PAGE_SIZE, \
956 .pages_size = CONFIG_FLASH_NXP_S32_QSPI_LAYOUT_PAGE_SIZE, \
957 }
958
959 #define QSPI_READ_ID_CFG(n) \
960 { \
961 .readIdLut = QSPI_LUT_IDX(QSPI_SEQ_RDID), \
962 .readIdSize = DT_INST_PROP_LEN(n, jedec_id), \
963 .readIdExpected = DT_INST_PROP(n, jedec_id), \
964 }
965
966 #define QSPI_MEMORY_CONN_CFG(n) \
967 { \
968 .connectionType = (Qspi_Ip_ConnectionType)DT_INST_REG_ADDR(n), \
969 .memAlignment = DT_INST_PROP_OR(n, memory_alignment, 1) \
970 }
971
972 #define QSPI_ERASE_CFG(n) \
973 { \
974 .eraseTypes = { \
975 { \
976 .eraseLut = QSPI_LUT_IDX(QSPI_SEQ_SE), \
977 .size = 12, /* 4 KB */ \
978 }, \
979 { \
980 .eraseLut = QSPI_LUT_IDX(QSPI_SEQ_BE), \
981 .size = 16, /* 64 KB */ \
982 }, \
983 COND_CODE_1(DT_INST_PROP(n, has_32k_erase), ( \
984 { \
985 .eraseLut = QSPI_LUT_IDX(QSPI_SEQ_BE_32K), \
986 .size = 15, /* 32 KB */ \
987 }, \
988 ), ( \
989 { \
990 .eraseLut = QSPI_IP_LUT_INVALID, \
991 }, \
992 )) \
993 { \
994 .eraseLut = QSPI_IP_LUT_INVALID, \
995 }, \
996 }, \
997 .chipEraseLut = QSPI_LUT_IDX(QSPI_SEQ_CE), \
998 }
999
1000 #define QSPI_RESET_CFG(n) \
1001 { \
1002 .resetCmdLut = QSPI_LUT_IDX(QSPI_SEQ_RESET), \
1003 .resetCmdCount = 4U, \
1004 }
1005
1006 /*
1007 * SR information used internally by the HAL to access fields BUSY and WEL
1008 * during read/write/erase and polling status operations.
1009 */
1010 #define QSPI_STATUS_REG_CFG(n) \
1011 { \
1012 .statusRegInitReadLut = QSPI_LUT_IDX(QSPI_SEQ_RDSR), \
1013 .statusRegReadLut = QSPI_LUT_IDX(QSPI_SEQ_RDSR), \
1014 .statusRegWriteLut = QSPI_LUT_IDX(QSPI_SEQ_WRSR), \
1015 .writeEnableSRLut = QSPI_LUT_IDX(QSPI_SEQ_WREN), \
1016 .writeEnableLut = QSPI_LUT_IDX(QSPI_SEQ_WREN), \
1017 .regSize = 1U, \
1018 .busyOffset = 0U, \
1019 .busyValue = 1U, \
1020 .writeEnableOffset = 1U, \
1021 }
1022
1023 #define QSPI_INIT_CFG(n) \
1024 { \
1025 .opCount = 0U, \
1026 .operations = NULL, \
1027 }
1028
1029 #define QSPI_LUT_CFG(n) \
1030 { \
1031 .opCount = ARRAY_SIZE(nxp_s32_qspi_lut), \
1032 .lutOps = (Qspi_Ip_InstrOpType *)nxp_s32_qspi_lut, \
1033 }
1034
1035 #define QSPI_MEMORY_CFG(n) \
1036 { \
1037 .memType = QSPI_IP_SERIAL_FLASH, \
1038 .hfConfig = NULL, \
1039 .memSize = DT_INST_PROP(n, size) / 8, \
1040 .pageSize = CONFIG_FLASH_NXP_S32_QSPI_LAYOUT_PAGE_SIZE, \
1041 .writeLut = QSPI_LUT_IDX(QSPI_WRITE_SEQ(n)), \
1042 .readLut = QSPI_LUT_IDX(QSPI_READ_SEQ(n)), \
1043 .read0xxLut = QSPI_IP_LUT_INVALID, \
1044 .read0xxLutAHB = QSPI_IP_LUT_INVALID, \
1045 .eraseSettings = QSPI_ERASE_CFG(n), \
1046 .statusConfig = QSPI_STATUS_REG_CFG(n), \
1047 .resetSettings = QSPI_RESET_CFG(n), \
1048 .initResetSettings = QSPI_RESET_CFG(n), \
1049 .initConfiguration = QSPI_INIT_CFG(n), \
1050 .lutSequences = QSPI_LUT_CFG(n), \
1051 COND_CODE_1(CONFIG_FLASH_NXP_S32_QSPI_NOR_SFDP_RUNTIME, (), ( \
1052 .readIdSettings = QSPI_READ_ID_CFG(n),) \
1053 ) \
1054 .suspendSettings = { \
1055 .eraseSuspendLut = QSPI_IP_LUT_INVALID, \
1056 .eraseResumeLut = QSPI_IP_LUT_INVALID, \
1057 .programSuspendLut = QSPI_IP_LUT_INVALID, \
1058 .programResumeLut = QSPI_IP_LUT_INVALID, \
1059 }, \
1060 .initCallout = NULL, \
1061 .resetCallout = NULL, \
1062 .errorCheckCallout = NULL, \
1063 .eccCheckCallout = NULL, \
1064 .ctrlAutoCfgPtr = NULL, \
1065 }
1066
1067 #define FLASH_NXP_S32_QSPI_INIT_DEVICE(n) \
1068 COND_CODE_1(CONFIG_FLASH_NXP_S32_QSPI_NOR_SFDP_RUNTIME, (), ( \
1069 BUILD_ASSERT(DT_INST_NODE_HAS_PROP(n, jedec_id), \
1070 "jedec-id is required for non-runtime SFDP"); \
1071 BUILD_ASSERT(DT_INST_PROP_LEN(n, jedec_id) == JESD216_READ_ID_LEN,\
1072 "jedec-id must be of size JESD216_READ_ID_LEN bytes"); \
1073 )) \
1074 \
1075 static const struct nxp_s32_qspi_config nxp_s32_qspi_config_##n = { \
1076 .controller = DEVICE_DT_GET(DT_INST_BUS(n)), \
1077 .flash_parameters = { \
1078 .write_block_size = QSPI_WRITE_BLOCK_SIZE, \
1079 .erase_value = QSPI_ERASE_VALUE, \
1080 }, \
1081 IF_ENABLED(CONFIG_FLASH_PAGE_LAYOUT, \
1082 (QSPI_PAGE_LAYOUT(n),)) \
1083 COND_CODE_1(CONFIG_FLASH_NXP_S32_QSPI_NOR_SFDP_RUNTIME, (), ( \
1084 .memory_cfg = QSPI_MEMORY_CFG(n), \
1085 .qer_type = QSPI_QER_TYPE(n), \
1086 .quad_mode = QSPI_HAS_QUAD_MODE(n) \
1087 )) \
1088 }; \
1089 \
1090 static struct nxp_s32_qspi_data nxp_s32_qspi_data_##n = { \
1091 .memory_conn_cfg = QSPI_MEMORY_CONN_CFG(n), \
1092 COND_CODE_1(CONFIG_FLASH_NXP_S32_QSPI_NOR_SFDP_RUNTIME, (), ( \
1093 .read_sfdp_lut_idx = QSPI_LUT_IDX(QSPI_SEQ_READ_SFDP), \
1094 )) \
1095 }; \
1096 \
1097 DEVICE_DT_INST_DEFINE(n, \
1098 nxp_s32_qspi_init, \
1099 NULL, \
1100 &nxp_s32_qspi_data_##n, \
1101 &nxp_s32_qspi_config_##n, \
1102 POST_KERNEL, \
1103 CONFIG_FLASH_INIT_PRIORITY, \
1104 &nxp_s32_qspi_api);
1105
1106 DT_INST_FOREACH_STATUS_OKAY(FLASH_NXP_S32_QSPI_INIT_DEVICE)
1107
