1 /*
2 * Copyright 2020,2023 NXP
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #define DT_DRV_COMPAT nxp_imx_flexspi_nor
8
9 #include <zephyr/kernel.h>
10 #include <zephyr/drivers/flash.h>
11 #include <zephyr/irq.h>
12 #include <zephyr/logging/log.h>
13 #include <zephyr/sys/util.h>
14 #include "spi_nor.h"
15 #include "jesd216.h"
16 #include "memc_mcux_flexspi.h"
17
18 #ifdef CONFIG_HAS_MCUX_CACHE
19 #include <fsl_cache.h>
20 #endif
21
22 #define NOR_WRITE_SIZE 1
23 #define NOR_ERASE_VALUE 0xff
24
25 #ifdef CONFIG_FLASH_MCUX_FLEXSPI_NOR_WRITE_BUFFER
26 static uint8_t nor_write_buf[SPI_NOR_PAGE_SIZE];
27 #endif
28
29 /*
30 * NOTE: If CONFIG_FLASH_MCUX_FLEXSPI_XIP is selected, Any external functions
31 * called while interacting with the flexspi MUST be relocated to SRAM or ITCM
32 * at runtime, so that the chip does not access the flexspi to read program
33 * instructions while it is being written to
34 *
35 * Additionally, no data used by this driver should be stored in flash.
36 */
37 #if defined(CONFIG_FLASH_MCUX_FLEXSPI_XIP) && (CONFIG_FLASH_LOG_LEVEL > 0)
38 #warning "Enabling flash driver logging and XIP mode simultaneously can cause \
39 read-while-write hazards. This configuration is not recommended."
40 #endif
41
42 LOG_MODULE_REGISTER(flash_flexspi_nor, CONFIG_FLASH_LOG_LEVEL);
43
44 enum {
45 READ,
46 PAGE_PROGRAM,
47 READ_STATUS,
48 WRITE_ENABLE,
49 ERASE_SECTOR,
50 ERASE_BLOCK,
51 READ_ID,
52 READ_STATUS_REG,
53 ERASE_CHIP,
54 READ_JESD216,
55 /* Used for temporary commands during initialization */
56 SCRATCH_CMD,
57 SCRATCH_CMD2,
58 /* Must be last entry */
59 FLEXSPI_INSTR_END,
60 };
61
62 struct flash_flexspi_nor_config {
63 /* Note: don't use this controller reference in code. It is
64 * only used during init to copy the device structure from ROM
65 * into a RAM structure
66 */
67 const struct device *controller;
68 };
69
70 /* Device variables used in critical sections should be in this structure */
71 struct flash_flexspi_nor_data {
72 struct device controller;
73 flexspi_device_config_t config;
74 flexspi_port_t port;
75 bool legacy_poll;
76 struct flash_pages_layout layout;
77 struct flash_parameters flash_parameters;
78 };
79
80 /* Initial LUT table */
81 static const uint32_t flash_flexspi_nor_base_lut[][MEMC_FLEXSPI_CMD_PER_SEQ] = {
82 /* 1S-1S-1S flash read command, should be compatible with all SPI nor flashes */
83 [READ] = {
84 FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, SPI_NOR_CMD_READ,
85 kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 24),
86 FLEXSPI_LUT_SEQ(kFLEXSPI_Command_READ_SDR, kFLEXSPI_1PAD, 0x1,
87 kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0x0),
88 },
89 [READ_JESD216] = {
90 /* Install read SFDP command */
91 FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, JESD216_CMD_READ_SFDP,
92 kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 24),
93 FLEXSPI_LUT_SEQ(kFLEXSPI_Command_DUMMY_SDR, kFLEXSPI_1PAD, 8,
94 kFLEXSPI_Command_READ_SDR, kFLEXSPI_1PAD, 0x4),
95 FLEXSPI_LUT_SEQ(kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0x0,
96 kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0x0),
97 },
98 /* Standard 1S-1S-1S flash write command, can be switched to 1S-1S-4S when QE is set */
99 [PAGE_PROGRAM] = {
100 FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, SPI_NOR_CMD_PP,
101 kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 0x18),
102 FLEXSPI_LUT_SEQ(kFLEXSPI_Command_WRITE_SDR, kFLEXSPI_1PAD, 0x04,
103 kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0),
104 },
105
106 [WRITE_ENABLE] = {
107 FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, SPI_NOR_CMD_WREN,
108 kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0),
109 },
110
111 [ERASE_SECTOR] = {
112 FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, SPI_NOR_CMD_SE,
113 kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 0x18),
114 },
115
116 [ERASE_BLOCK] = {
117 FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, SPI_NOR_CMD_BE,
118 kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 0x18),
119 },
120
121 [ERASE_CHIP] = {
122 FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, SPI_NOR_CMD_CE,
123 kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0),
124 },
125
126 [READ_ID] = {
127 FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, SPI_NOR_CMD_RDID,
128 kFLEXSPI_Command_READ_SDR, kFLEXSPI_1PAD, 0x01),
129 },
130
131 [READ_STATUS_REG] = {
132 FLEXSPI_LUT_SEQ(kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, SPI_NOR_CMD_RDSR,
133 kFLEXSPI_Command_READ_SDR, kFLEXSPI_1PAD, 0x01),
134 },
135 };
136
137 /* Helper so we can read flash ID without flash access for XIP */
flash_flexspi_nor_read_id_helper(struct flash_flexspi_nor_data * data,uint8_t * vendor_id)138 static int flash_flexspi_nor_read_id_helper(struct flash_flexspi_nor_data *data,
139 uint8_t *vendor_id)
140 {
141 uint32_t buffer = 0;
142 int ret;
143
144 flexspi_transfer_t transfer = {
145 .deviceAddress = 0,
146 .port = data->port,
147 .cmdType = kFLEXSPI_Read,
148 .SeqNumber = 1,
149 .seqIndex = READ_ID,
150 .data = &buffer,
151 .dataSize = 3,
152 };
153
154 LOG_DBG("Reading id");
155
156 ret = memc_flexspi_transfer(&data->controller, &transfer);
157 if (ret < 0) {
158 return ret;
159 }
160
161 memcpy(vendor_id, &buffer, 3);
162
163 return ret;
164 }
165
flash_flexspi_nor_read_id(const struct device * dev,uint8_t * vendor_id)166 static int flash_flexspi_nor_read_id(const struct device *dev, uint8_t *vendor_id)
167 {
168 struct flash_flexspi_nor_data *data = dev->data;
169
170 return flash_flexspi_nor_read_id_helper(data, vendor_id);
171 }
172
flash_flexspi_nor_read_status(struct flash_flexspi_nor_data * data,uint32_t * status)173 static int flash_flexspi_nor_read_status(struct flash_flexspi_nor_data *data,
174 uint32_t *status)
175 {
176 flexspi_transfer_t transfer = {
177 .deviceAddress = 0,
178 .port = data->port,
179 .cmdType = kFLEXSPI_Read,
180 .SeqNumber = 1,
181 .seqIndex = READ_STATUS_REG,
182 .data = status,
183 .dataSize = 1,
184 };
185
186 LOG_DBG("Reading status register");
187
188 return memc_flexspi_transfer(&data->controller, &transfer);
189 }
190
flash_flexspi_nor_write_enable(struct flash_flexspi_nor_data * data)191 static int flash_flexspi_nor_write_enable(struct flash_flexspi_nor_data *data)
192 {
193 flexspi_transfer_t transfer = {
194 .deviceAddress = 0,
195 .port = data->port,
196 .cmdType = kFLEXSPI_Command,
197 .SeqNumber = 1,
198 .seqIndex = WRITE_ENABLE,
199 .data = NULL,
200 .dataSize = 0,
201 };
202
203 LOG_DBG("Enabling write");
204
205 return memc_flexspi_transfer(&data->controller, &transfer);
206 }
207
flash_flexspi_nor_erase_sector(struct flash_flexspi_nor_data * data,off_t offset)208 static int flash_flexspi_nor_erase_sector(struct flash_flexspi_nor_data *data,
209 off_t offset)
210 {
211 flexspi_transfer_t transfer = {
212 .deviceAddress = offset,
213 .port = data->port,
214 .cmdType = kFLEXSPI_Command,
215 .SeqNumber = 1,
216 .seqIndex = ERASE_SECTOR,
217 .data = NULL,
218 .dataSize = 0,
219 };
220
221 LOG_DBG("Erasing sector at 0x%08zx", (ssize_t) offset);
222
223 return memc_flexspi_transfer(&data->controller, &transfer);
224 }
225
flash_flexspi_nor_erase_block(struct flash_flexspi_nor_data * data,off_t offset)226 static int flash_flexspi_nor_erase_block(struct flash_flexspi_nor_data *data,
227 off_t offset)
228 {
229 flexspi_transfer_t transfer = {
230 .deviceAddress = offset,
231 .port = data->port,
232 .cmdType = kFLEXSPI_Command,
233 .SeqNumber = 1,
234 .seqIndex = ERASE_BLOCK,
235 .data = NULL,
236 .dataSize = 0,
237 };
238
239 LOG_DBG("Erasing block at 0x%08zx", (ssize_t) offset);
240
241 return memc_flexspi_transfer(&data->controller, &transfer);
242 }
243
flash_flexspi_nor_erase_chip(struct flash_flexspi_nor_data * data)244 static int flash_flexspi_nor_erase_chip(struct flash_flexspi_nor_data *data)
245 {
246 flexspi_transfer_t transfer = {
247 .deviceAddress = 0,
248 .port = data->port,
249 .cmdType = kFLEXSPI_Command,
250 .SeqNumber = 1,
251 .seqIndex = ERASE_CHIP,
252 .data = NULL,
253 .dataSize = 0,
254 };
255
256 LOG_DBG("Erasing chip");
257
258 return memc_flexspi_transfer(&data->controller, &transfer);
259 }
260
flash_flexspi_nor_page_program(struct flash_flexspi_nor_data * data,off_t offset,const void * buffer,size_t len)261 static int flash_flexspi_nor_page_program(struct flash_flexspi_nor_data *data,
262 off_t offset, const void *buffer, size_t len)
263 {
264 flexspi_transfer_t transfer = {
265 .deviceAddress = offset,
266 .port = data->port,
267 .cmdType = kFLEXSPI_Write,
268 .SeqNumber = 1,
269 .seqIndex = PAGE_PROGRAM,
270 .data = (uint32_t *) buffer,
271 .dataSize = len,
272 };
273
274 LOG_DBG("Page programming %d bytes to 0x%08zx", len, (ssize_t) offset);
275
276 return memc_flexspi_transfer(&data->controller, &transfer);
277 }
278
flash_flexspi_nor_wait_bus_busy(struct flash_flexspi_nor_data * data)279 static int flash_flexspi_nor_wait_bus_busy(struct flash_flexspi_nor_data *data)
280 {
281 uint32_t status = 0;
282 int ret;
283
284 while (1) {
285 ret = flash_flexspi_nor_read_status(data, &status);
286 LOG_DBG("status: 0x%x", status);
287 if (ret) {
288 LOG_ERR("Could not read status");
289 return ret;
290 }
291
292 if (data->legacy_poll) {
293 if ((status & BIT(0)) == 0) {
294 break;
295 }
296 } else {
297 if (status & BIT(7)) {
298 break;
299 }
300 }
301 }
302
303 return 0;
304 }
305
flash_flexspi_nor_read(const struct device * dev,off_t offset,void * buffer,size_t len)306 static int flash_flexspi_nor_read(const struct device *dev, off_t offset,
307 void *buffer, size_t len)
308 {
309 struct flash_flexspi_nor_data *data = dev->data;
310 uint8_t *src = memc_flexspi_get_ahb_address(&data->controller,
311 data->port,
312 offset);
313
314 memcpy(buffer, src, len);
315
316 return 0;
317 }
318
flash_flexspi_nor_write(const struct device * dev,off_t offset,const void * buffer,size_t len)319 static int flash_flexspi_nor_write(const struct device *dev, off_t offset,
320 const void *buffer, size_t len)
321 {
322 struct flash_flexspi_nor_data *data = dev->data;
323 size_t size = len;
324 uint8_t *src = (uint8_t *) buffer;
325 int i;
326 unsigned int key = 0;
327
328 uint8_t *dst = memc_flexspi_get_ahb_address(&data->controller,
329 data->port,
330 offset);
331
332 if (memc_flexspi_is_running_xip(&data->controller)) {
333 /*
334 * ==== ENTER CRITICAL SECTION ====
335 * No flash access should be performed in critical section. All
336 * code and data accessed must reside in ram.
337 */
338 key = irq_lock();
339 }
340
341 while (len) {
342 /* If the offset isn't a multiple of the NOR page size, we first need
343 * to write the remaining part that fits, otherwise the write could
344 * be wrapped around within the same page
345 */
346 i = MIN(SPI_NOR_PAGE_SIZE - (offset % SPI_NOR_PAGE_SIZE), len);
347 #ifdef CONFIG_FLASH_MCUX_FLEXSPI_NOR_WRITE_BUFFER
348 memcpy(nor_write_buf, src, i);
349 #endif
350 flash_flexspi_nor_write_enable(data);
351 #ifdef CONFIG_FLASH_MCUX_FLEXSPI_NOR_WRITE_BUFFER
352 flash_flexspi_nor_page_program(data, offset, nor_write_buf, i);
353 #else
354 flash_flexspi_nor_page_program(data, offset, src, i);
355 #endif
356 flash_flexspi_nor_wait_bus_busy(data);
357 memc_flexspi_reset(&data->controller);
358 src += i;
359 offset += i;
360 len -= i;
361 }
362
363 if (memc_flexspi_is_running_xip(&data->controller)) {
364 /* ==== EXIT CRITICAL SECTION ==== */
365 irq_unlock(key);
366 }
367
368 #ifdef CONFIG_HAS_MCUX_CACHE
369 DCACHE_InvalidateByRange((uint32_t) dst, size);
370 #endif
371
372 return 0;
373 }
374
flash_flexspi_nor_erase(const struct device * dev,off_t offset,size_t size)375 static int flash_flexspi_nor_erase(const struct device *dev, off_t offset,
376 size_t size)
377 {
378 struct flash_flexspi_nor_data *data = dev->data;
379 const size_t num_sectors = size / SPI_NOR_SECTOR_SIZE;
380 const size_t num_blocks = size / SPI_NOR_BLOCK_SIZE;
381
382 int i;
383 unsigned int key = 0;
384
385 uint8_t *dst = memc_flexspi_get_ahb_address(&data->controller,
386 data->port,
387 offset);
388
389 if (offset % SPI_NOR_SECTOR_SIZE) {
390 LOG_ERR("Invalid offset");
391 return -EINVAL;
392 }
393
394 if (size % SPI_NOR_SECTOR_SIZE) {
395 LOG_ERR("Invalid size");
396 return -EINVAL;
397 }
398
399 if (memc_flexspi_is_running_xip(&data->controller)) {
400 /*
401 * ==== ENTER CRITICAL SECTION ====
402 * No flash access should be performed in critical section. All
403 * code and data accessed must reside in ram.
404 */
405 key = irq_lock();
406 }
407
408 if ((offset == 0) && (size == data->config.flashSize * KB(1))) {
409 flash_flexspi_nor_write_enable(data);
410 flash_flexspi_nor_erase_chip(data);
411 flash_flexspi_nor_wait_bus_busy(data);
412 memc_flexspi_reset(&data->controller);
413 } else if ((0 == (offset % SPI_NOR_BLOCK_SIZE)) && (0 == (size % SPI_NOR_BLOCK_SIZE))) {
414 for (i = 0; i < num_blocks; i++) {
415 flash_flexspi_nor_write_enable(data);
416 flash_flexspi_nor_erase_block(data, offset);
417 flash_flexspi_nor_wait_bus_busy(data);
418 memc_flexspi_reset(&data->controller);
419 offset += SPI_NOR_BLOCK_SIZE;
420 }
421 } else {
422 for (i = 0; i < num_sectors; i++) {
423 flash_flexspi_nor_write_enable(data);
424 flash_flexspi_nor_erase_sector(data, offset);
425 flash_flexspi_nor_wait_bus_busy(data);
426 memc_flexspi_reset(&data->controller);
427 offset += SPI_NOR_SECTOR_SIZE;
428 }
429 }
430
431 if (memc_flexspi_is_running_xip(&data->controller)) {
432 /* ==== EXIT CRITICAL SECTION ==== */
433 irq_unlock(key);
434 }
435
436 #ifdef CONFIG_HAS_MCUX_CACHE
437 DCACHE_InvalidateByRange((uint32_t) dst, size);
438 #endif
439
440 return 0;
441 }
442
flash_flexspi_nor_get_parameters(const struct device * dev)443 static const struct flash_parameters *flash_flexspi_nor_get_parameters(
444 const struct device *dev)
445 {
446 struct flash_flexspi_nor_data *data = dev->data;
447
448 return &data->flash_parameters;
449 }
450
451 #if defined(CONFIG_FLASH_PAGE_LAYOUT)
flash_flexspi_nor_pages_layout(const struct device * dev,const struct flash_pages_layout ** layout,size_t * layout_size)452 static void flash_flexspi_nor_pages_layout(const struct device *dev,
453 const struct flash_pages_layout **layout, size_t *layout_size)
454 {
455 struct flash_flexspi_nor_data *data = dev->data;
456
457 *layout = &data->layout;
458 *layout_size = 1;
459 }
460 #endif /* CONFIG_FLASH_PAGE_LAYOUT */
461
462
463 /*
464 * This function enables quad mode, when supported. Otherwise it
465 * returns an error.
466 * @param dev: Flexspi device
467 * @param flexspi_lut: flexspi lut table, useful if instruction writes are needed
468 * @param qer: DW15 quad enable parameter
469 * @return 0 if quad mode was entered, or -ENOTSUP if quad mode is not supported
470 */
flash_flexspi_nor_quad_enable(struct flash_flexspi_nor_data * data,uint32_t (* flexspi_lut)[MEMC_FLEXSPI_CMD_PER_SEQ],uint8_t qer)471 static int flash_flexspi_nor_quad_enable(struct flash_flexspi_nor_data *data,
472 uint32_t (*flexspi_lut)[MEMC_FLEXSPI_CMD_PER_SEQ],
473 uint8_t qer)
474 {
475 int ret;
476 uint32_t buffer = 0;
477 uint16_t bit = 0;
478 uint8_t rd_size, wr_size;
479 flexspi_transfer_t transfer = {
480 .deviceAddress = 0,
481 .port = data->port,
482 .SeqNumber = 1,
483 .data = &buffer,
484 };
485 flexspi_device_config_t config = {
486 .flexspiRootClk = MHZ(50),
487 .flashSize = FLEXSPI_FLSHCR0_FLSHSZ_MASK, /* Max flash size */
488 .ARDSeqNumber = 1,
489 .ARDSeqIndex = READ,
490 };
491
492 switch (qer) {
493 case JESD216_DW15_QER_VAL_NONE:
494 /* No init needed */
495 return 0;
496 case JESD216_DW15_QER_VAL_S2B1v1:
497 case JESD216_DW15_QER_VAL_S2B1v4:
498 /* Install read and write status command */
499 flexspi_lut[SCRATCH_CMD][0] = FLEXSPI_LUT_SEQ(
500 kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, SPI_NOR_CMD_RDSR,
501 kFLEXSPI_Command_READ_SDR, kFLEXSPI_1PAD, 0x1);
502 flexspi_lut[SCRATCH_CMD2][0] = FLEXSPI_LUT_SEQ(
503 kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, SPI_NOR_CMD_WRSR,
504 kFLEXSPI_Command_WRITE_SDR, kFLEXSPI_1PAD, 0x1);
505
506 /* Set bit 1 of status register 2 */
507 bit = BIT(9);
508 rd_size = 2;
509 wr_size = 2;
510 break;
511 case JESD216_DW15_QER_VAL_S1B6:
512 /* Install read and write status command */
513 flexspi_lut[SCRATCH_CMD][0] = FLEXSPI_LUT_SEQ(
514 kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, SPI_NOR_CMD_RDSR,
515 kFLEXSPI_Command_READ_SDR, kFLEXSPI_1PAD, 0x1);
516 flexspi_lut[SCRATCH_CMD2][0] = FLEXSPI_LUT_SEQ(
517 kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, SPI_NOR_CMD_WRSR,
518 kFLEXSPI_Command_WRITE_SDR, kFLEXSPI_1PAD, 0x1);
519
520 /* Set bit 6 of status register 1 */
521 bit = BIT(6);
522 rd_size = 1;
523 wr_size = 1;
524 break;
525 case JESD216_DW15_QER_VAL_S2B7:
526 /* Install read and write status command */
527 flexspi_lut[SCRATCH_CMD][0] = FLEXSPI_LUT_SEQ(
528 kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x3F,
529 kFLEXSPI_Command_READ_SDR, kFLEXSPI_1PAD, 0x1);
530 flexspi_lut[SCRATCH_CMD2][0] = FLEXSPI_LUT_SEQ(
531 kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x3E,
532 kFLEXSPI_Command_WRITE_SDR, kFLEXSPI_1PAD, 0x1);
533
534 /* Set bit 7 of status register 2 */
535 bit = BIT(7);
536 rd_size = 1;
537 wr_size = 1;
538 break;
539 case JESD216_DW15_QER_VAL_S2B1v5:
540 /* Install read and write status command */
541 flexspi_lut[SCRATCH_CMD][0] = FLEXSPI_LUT_SEQ(
542 kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, SPI_NOR_CMD_RDSR2,
543 kFLEXSPI_Command_READ_SDR, kFLEXSPI_1PAD, 0x1);
544 flexspi_lut[SCRATCH_CMD2][0] = FLEXSPI_LUT_SEQ(
545 kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, SPI_NOR_CMD_WRSR,
546 kFLEXSPI_Command_WRITE_SDR, kFLEXSPI_1PAD, 0x1);
547
548 /* Set bit 1 of status register 2 */
549 bit = BIT(9);
550 rd_size = 1;
551 wr_size = 2;
552 break;
553 case JESD216_DW15_QER_VAL_S2B1v6:
554 /* Install read and write status command */
555 flexspi_lut[SCRATCH_CMD][0] = FLEXSPI_LUT_SEQ(
556 kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, SPI_NOR_CMD_RDSR2,
557 kFLEXSPI_Command_READ_SDR, kFLEXSPI_1PAD, 0x1);
558 flexspi_lut[SCRATCH_CMD2][0] = FLEXSPI_LUT_SEQ(
559 kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, SPI_NOR_CMD_WRSR2,
560 kFLEXSPI_Command_WRITE_SDR, kFLEXSPI_1PAD, 0x1);
561
562 /* Set bit 7 of status register 2 */
563 bit = BIT(7);
564 rd_size = 1;
565 wr_size = 1;
566 break;
567 default:
568 return -ENOTSUP;
569 }
570 ret = memc_flexspi_set_device_config(&data->controller,
571 &config,
572 (uint32_t *)flexspi_lut,
573 FLEXSPI_INSTR_END * MEMC_FLEXSPI_CMD_PER_SEQ,
574 data->port);
575 if (ret < 0) {
576 return ret;
577 }
578 transfer.dataSize = rd_size;
579 transfer.seqIndex = SCRATCH_CMD;
580 transfer.cmdType = kFLEXSPI_Read;
581 /* Read status register */
582 ret = memc_flexspi_transfer(&data->controller, &transfer);
583 if (ret < 0) {
584 return ret;
585 }
586 buffer |= bit;
587 transfer.dataSize = wr_size;
588 transfer.seqIndex = SCRATCH_CMD2;
589 transfer.cmdType = kFLEXSPI_Write;
590 return memc_flexspi_transfer(&data->controller, &transfer);
591 }
592
593 /*
594 * This function enables 4 byte addressing, when supported. Otherwise it
595 * returns an error.
596 * @param dev: Flexspi device
597 * @param flexspi_lut: flexspi lut table, useful if instruction writes are needed
598 * @param en4b: DW16 enable 4 byte mode parameter
599 * @return 0 if 4 byte mode was entered, or -ENOTSUP if 4 byte mode was not supported
600 */
flash_flexspi_nor_4byte_enable(struct flash_flexspi_nor_data * data,uint32_t (* flexspi_lut)[MEMC_FLEXSPI_CMD_PER_SEQ],uint32_t en4b)601 static int flash_flexspi_nor_4byte_enable(struct flash_flexspi_nor_data *data,
602 uint32_t (*flexspi_lut)[MEMC_FLEXSPI_CMD_PER_SEQ],
603 uint32_t en4b)
604 {
605 int ret;
606 uint32_t buffer = 0;
607 flexspi_transfer_t transfer = {
608 .deviceAddress = 0,
609 .port = data->port,
610 .SeqNumber = 1,
611 .data = &buffer,
612 };
613 flexspi_device_config_t config = {
614 .flexspiRootClk = MHZ(50),
615 .flashSize = FLEXSPI_FLSHCR0_FLSHSZ_MASK, /* Max flash size */
616 .ARDSeqNumber = 1,
617 .ARDSeqIndex = READ,
618 };
619 if (en4b & BIT(6)) {
620 /* Flash is always in 4 byte mode. We just need to configure LUT */
621 return 0;
622 } else if (en4b & BIT(5)) {
623 /* Dedicated vendor instruction set, which we don't support. Exit here */
624 return -ENOTSUP;
625 } else if (en4b & BIT(4)) {
626 /* Set bit 0 of 16 bit configuration register */
627 flexspi_lut[SCRATCH_CMD][0] = FLEXSPI_LUT_SEQ(
628 kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0xB5,
629 kFLEXSPI_Command_READ_SDR, kFLEXSPI_1PAD, 0x1);
630 flexspi_lut[SCRATCH_CMD2][0] = FLEXSPI_LUT_SEQ(
631 kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0xB1,
632 kFLEXSPI_Command_WRITE_SDR, kFLEXSPI_1PAD, 0x1);
633 ret = memc_flexspi_set_device_config(&data->controller,
634 &config,
635 (uint32_t *)flexspi_lut,
636 FLEXSPI_INSTR_END * MEMC_FLEXSPI_CMD_PER_SEQ,
637 data->port);
638 if (ret < 0) {
639 return ret;
640 }
641 transfer.dataSize = 2;
642 transfer.seqIndex = SCRATCH_CMD;
643 transfer.cmdType = kFLEXSPI_Read;
644 /* Read config register */
645 ret = memc_flexspi_transfer(&data->controller, &transfer);
646 if (ret < 0) {
647 return ret;
648 }
649 buffer |= BIT(0);
650 /* Set config register */
651 transfer.seqIndex = SCRATCH_CMD2;
652 transfer.cmdType = kFLEXSPI_Read;
653 return memc_flexspi_transfer(&data->controller, &transfer);
654 } else if (en4b & BIT(1)) {
655 /* Issue write enable, then instruction 0xB7 */
656 flash_flexspi_nor_write_enable(data);
657 flexspi_lut[SCRATCH_CMD][0] = FLEXSPI_LUT_SEQ(
658 kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0xB7,
659 kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0x0);
660 ret = memc_flexspi_set_device_config(&data->controller,
661 &config,
662 (uint32_t *)flexspi_lut,
663 FLEXSPI_INSTR_END * MEMC_FLEXSPI_CMD_PER_SEQ,
664 data->port);
665 if (ret < 0) {
666 return ret;
667 }
668 transfer.dataSize = 0;
669 transfer.seqIndex = SCRATCH_CMD;
670 transfer.cmdType = kFLEXSPI_Command;
671 return memc_flexspi_transfer(&data->controller, &transfer);
672 } else if (en4b & BIT(0)) {
673 /* Issue instruction 0xB7 */
674 flexspi_lut[SCRATCH_CMD][0] = FLEXSPI_LUT_SEQ(
675 kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0xB7,
676 kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0x0);
677 ret = memc_flexspi_set_device_config(&data->controller,
678 &config,
679 (uint32_t *)flexspi_lut,
680 FLEXSPI_INSTR_END * MEMC_FLEXSPI_CMD_PER_SEQ,
681 data->port);
682 if (ret < 0) {
683 return ret;
684 }
685 transfer.dataSize = 0;
686 transfer.seqIndex = SCRATCH_CMD;
687 transfer.cmdType = kFLEXSPI_Command;
688 return memc_flexspi_transfer(&data->controller, &transfer);
689 }
690 /* Other methods not supported */
691 return -ENOTSUP;
692 }
693
694 /*
695 * This function configures the FlexSPI to manage the flash device
696 * based on values in SFDP header
697 * @param data: Flexspi device data
698 * @param header: SFDP header for flash
699 * @param bfp: basic flash parameters for flash
700 * @param flexspi_lut: LUT table, filled with READ LUT command
701 * @return 0 on success, or negative value on error
702 */
flash_flexspi_nor_config_flash(struct flash_flexspi_nor_data * data,struct jesd216_sfdp_header * header,struct jesd216_bfp * bfp,uint32_t (* flexspi_lut)[MEMC_FLEXSPI_CMD_PER_SEQ])703 static int flash_flexspi_nor_config_flash(struct flash_flexspi_nor_data *data,
704 struct jesd216_sfdp_header *header,
705 struct jesd216_bfp *bfp,
706 uint32_t (*flexspi_lut)[MEMC_FLEXSPI_CMD_PER_SEQ])
707 {
708 struct jesd216_instr instr;
709 struct jesd216_bfp_dw16 dw16;
710 struct jesd216_bfp_dw15 dw15;
711 struct jesd216_bfp_dw14 dw14;
712 uint8_t addr_width;
713 uint8_t mode_cmd;
714 int ret;
715
716 addr_width = jesd216_bfp_addrbytes(bfp) ==
717 JESD216_SFDP_BFP_DW1_ADDRBYTES_VAL_4B ? 32 : 24;
718
719 /* Check to see if we can enable 4 byte addressing */
720 ret = jesd216_bfp_decode_dw16(&header->phdr[0], bfp, &dw16);
721 if (ret < 0) {
722 return ret;
723 }
724
725 /* Attempt to enable 4 byte addressing */
726 ret = flash_flexspi_nor_4byte_enable(data, flexspi_lut, dw16.enter_4ba);
727 if (ret == 0) {
728 /* Use 4 byte address width */
729 addr_width = 32;
730 /* Update LUT for ERASE_SECTOR and ERASE_BLOCK to use 32 bit addr */
731 flexspi_lut[ERASE_SECTOR][0] = FLEXSPI_LUT_SEQ(
732 kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, SPI_NOR_CMD_SE,
733 kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, addr_width);
734 flexspi_lut[ERASE_BLOCK][0] = FLEXSPI_LUT_SEQ(
735 kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, SPI_NOR_CMD_BE,
736 kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, addr_width);
737 }
738 /* Extract the read command.
739 * Note- enhanced XIP not currently supported, nor is 4-4-4 mode.
740 */
741 if (jesd216_bfp_read_support(&header->phdr[0], bfp,
742 JESD216_MODE_144, &instr) > 0) {
743 LOG_DBG("Enable 144 mode");
744 /* Configure for 144 QUAD read mode */
745 if (instr.mode_clocks == 2) {
746 mode_cmd = kFLEXSPI_Command_MODE8_SDR;
747 } else if (instr.mode_clocks == 1) {
748 mode_cmd = kFLEXSPI_Command_MODE4_SDR;
749 } else if (instr.mode_clocks == 0) {
750 /* Just send dummy cycles during mode clock period */
751 mode_cmd = kFLEXSPI_Command_DUMMY_SDR;
752 } else {
753 return -ENOTSUP;
754 }
755 flexspi_lut[READ][0] = FLEXSPI_LUT_SEQ(
756 kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, instr.instr,
757 kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_4PAD, addr_width);
758 /* Note- we always set mode bits to 0x0 */
759 flexspi_lut[READ][1] = FLEXSPI_LUT_SEQ(
760 mode_cmd, kFLEXSPI_4PAD, 0x00,
761 kFLEXSPI_Command_DUMMY_SDR, kFLEXSPI_4PAD, instr.wait_states);
762 flexspi_lut[READ][2] = FLEXSPI_LUT_SEQ(
763 kFLEXSPI_Command_READ_SDR, kFLEXSPI_4PAD, 0x04,
764 kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0x0);
765 /* Read 1S-4S-4S enable method */
766 ret = jesd216_bfp_decode_dw15(&header->phdr[0], bfp, &dw15);
767 if (ret < 0) {
768 return ret;
769 }
770 ret = flash_flexspi_nor_quad_enable(data, flexspi_lut, dw15.qer);
771 if (ret < 0) {
772 return ret;
773 }
774 /* Now, install 1S-1S-4S page program command */
775 flexspi_lut[PAGE_PROGRAM][0] = FLEXSPI_LUT_SEQ(
776 kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, SPI_NOR_CMD_PP_1_1_4,
777 kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, addr_width);
778 flexspi_lut[PAGE_PROGRAM][1] = FLEXSPI_LUT_SEQ(
779 kFLEXSPI_Command_WRITE_SDR, kFLEXSPI_4PAD, 0x4,
780 kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0x0);
781
782 } else if (jesd216_bfp_read_support(&header->phdr[0], bfp,
783 JESD216_MODE_122, &instr) > 0) {
784 LOG_DBG("Enable 122 mode");
785 if (instr.mode_clocks == 4) {
786 mode_cmd = kFLEXSPI_Command_MODE8_SDR;
787 } else if (instr.mode_clocks == 2) {
788 mode_cmd = kFLEXSPI_Command_MODE4_SDR;
789 } else if (instr.mode_clocks == 1) {
790 mode_cmd = kFLEXSPI_Command_MODE2_SDR;
791 } else if (instr.mode_clocks == 0) {
792 /* Just send dummy cycles during mode clock period */
793 mode_cmd = kFLEXSPI_Command_DUMMY_SDR;
794 } else {
795 return -ENOTSUP;
796 }
797 flexspi_lut[READ][0] = FLEXSPI_LUT_SEQ(
798 kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, instr.instr,
799 kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_2PAD, addr_width);
800 /* Note- we always set mode bits to 0x0 */
801 flexspi_lut[READ][1] = FLEXSPI_LUT_SEQ(
802 mode_cmd, kFLEXSPI_2PAD, 0x0,
803 kFLEXSPI_Command_DUMMY_SDR, kFLEXSPI_2PAD, instr.wait_states);
804 flexspi_lut[READ][2] = FLEXSPI_LUT_SEQ(
805 kFLEXSPI_Command_READ_SDR, kFLEXSPI_2PAD, 0x02,
806 kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0x0);
807 /* Now, install 1S-1S-2S page program command */
808 flexspi_lut[PAGE_PROGRAM][0] = FLEXSPI_LUT_SEQ(
809 kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, SPI_NOR_CMD_PP_1_1_2,
810 kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, addr_width);
811 flexspi_lut[PAGE_PROGRAM][1] = FLEXSPI_LUT_SEQ(
812 kFLEXSPI_Command_WRITE_SDR, kFLEXSPI_2PAD, 0x4,
813 kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0x0);
814 }
815 /* Default to 111 mode if no support exists, leave READ/WRITE untouched */
816
817 /* Now, read DW14 to determine the polling method we should use while programming */
818 ret = jesd216_bfp_decode_dw14(&header->phdr[0], bfp, &dw14);
819 if (ret < 0) {
820 return ret;
821 }
822 if (dw14.poll_options & BIT(1)) {
823 /* Read instruction used for polling is 0x70 */
824 data->legacy_poll = false;
825 flexspi_lut[READ_STATUS_REG][0] = FLEXSPI_LUT_SEQ(
826 kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0x70,
827 kFLEXSPI_Command_READ_SDR, kFLEXSPI_1PAD, 0x01);
828 } else {
829 /* Read instruction used for polling is 0x05 */
830 data->legacy_poll = true;
831 flexspi_lut[READ_STATUS_REG][0] = FLEXSPI_LUT_SEQ(
832 kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, SPI_NOR_CMD_RDSR,
833 kFLEXSPI_Command_READ_SDR, kFLEXSPI_1PAD, 0x01);
834 }
835
836 return 0;
837 }
838
839 /* Helper so we can avoid flash access while performing SFDP probe */
flash_flexspi_nor_sfdp_read_helper(struct flash_flexspi_nor_data * dev_data,off_t offset,void * data,size_t len)840 static int flash_flexspi_nor_sfdp_read_helper(struct flash_flexspi_nor_data *dev_data,
841 off_t offset, void *data, size_t len)
842 {
843 flexspi_transfer_t transfer = {
844 .deviceAddress = offset,
845 .port = dev_data->port,
846 .cmdType = kFLEXSPI_Read,
847 .seqIndex = READ_JESD216,
848 .SeqNumber = 1,
849 .data = (uint32_t *)data,
850 .dataSize = len,
851 };
852
853 /* Get SFDP data */
854 return memc_flexspi_transfer(&dev_data->controller, &transfer);
855 }
856
857
858 #if defined(CONFIG_FLASH_JESD216_API)
859
flash_flexspi_nor_sfdp_read(const struct device * dev,off_t offset,void * data,size_t len)860 static int flash_flexspi_nor_sfdp_read(const struct device *dev,
861 off_t offset, void *data, size_t len)
862 {
863 struct flash_flexspi_nor_data *dev_data = dev->data;
864
865 return flash_flexspi_nor_sfdp_read_helper(dev_data, offset, data, len);
866 }
867
868 #endif
869
870 /* Checks JEDEC ID of flash. If supported, installs custom LUT table */
flash_flexspi_nor_check_jedec(struct flash_flexspi_nor_data * data,uint32_t (* flexspi_lut)[MEMC_FLEXSPI_CMD_PER_SEQ])871 static int flash_flexspi_nor_check_jedec(struct flash_flexspi_nor_data *data,
872 uint32_t (*flexspi_lut)[MEMC_FLEXSPI_CMD_PER_SEQ])
873 {
874 int ret;
875 uint32_t vendor_id;
876
877 ret = flash_flexspi_nor_read_id_helper(data, (uint8_t *)&vendor_id);
878 if (ret < 0) {
879 return ret;
880 }
881
882 /* Switch on manufacturer and vendor ID */
883 switch (vendor_id & 0xFFFF) {
884 case 0x25C2:
885 /* MX25 flash, use 4 byte read/write */
886 flexspi_lut[READ][0] = FLEXSPI_LUT_SEQ(
887 kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, SPI_NOR_CMD_4READ_4B,
888 kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_4PAD, 32);
889 /* Flash needs 10 dummy cycles */
890 flexspi_lut[READ][1] = FLEXSPI_LUT_SEQ(
891 kFLEXSPI_Command_DUMMY_SDR, kFLEXSPI_4PAD, 10,
892 kFLEXSPI_Command_READ_SDR, kFLEXSPI_4PAD, 0x04);
893 /* Only 1S-4S-4S page program supported */
894 flexspi_lut[PAGE_PROGRAM][0] = FLEXSPI_LUT_SEQ(
895 kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, SPI_NOR_CMD_PP_1_4_4_4B,
896 kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_4PAD, 32);
897 flexspi_lut[PAGE_PROGRAM][1] = FLEXSPI_LUT_SEQ(
898 kFLEXSPI_Command_WRITE_SDR, kFLEXSPI_4PAD, 0x4,
899 kFLEXSPI_Command_STOP, kFLEXSPI_1PAD, 0x0);
900 /* Update ERASE commands for 4 byte mode */
901 flexspi_lut[ERASE_SECTOR][0] = FLEXSPI_LUT_SEQ(
902 kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, SPI_NOR_CMD_SE_4B,
903 kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 32);
904 flexspi_lut[ERASE_BLOCK][0] = FLEXSPI_LUT_SEQ(
905 kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, 0xDC,
906 kFLEXSPI_Command_RADDR_SDR, kFLEXSPI_1PAD, 32),
907 /* Read instruction used for polling is 0x05 */
908 data->legacy_poll = true;
909 flexspi_lut[READ_STATUS_REG][0] = FLEXSPI_LUT_SEQ(
910 kFLEXSPI_Command_SDR, kFLEXSPI_1PAD, SPI_NOR_CMD_RDSR,
911 kFLEXSPI_Command_READ_SDR, kFLEXSPI_1PAD, 0x01);
912 /* Device uses bit 6 of status reg 1 for QE */
913 return flash_flexspi_nor_quad_enable(data, flexspi_lut, JESD216_DW15_QER_VAL_S1B6);
914 default:
915 return -ENOTSUP;
916 }
917 }
918
919 /* Probe parameters from flash SFDP header, and use them to configure the FlexSPI */
flash_flexspi_nor_probe(struct flash_flexspi_nor_data * data)920 static int flash_flexspi_nor_probe(struct flash_flexspi_nor_data *data)
921 {
922 uint32_t flexspi_lut[FLEXSPI_INSTR_END][MEMC_FLEXSPI_CMD_PER_SEQ] = {0};
923 /* JESD216B defines up to 23 basic flash parameters */
924 uint32_t param_buf[23];
925 /* Space to store SFDP header and first parameter header */
926 uint8_t sfdp_buf[JESD216_SFDP_SIZE(1)] __aligned(4);
927 struct jesd216_bfp *bfp = (struct jesd216_bfp *)param_buf;
928 struct jesd216_sfdp_header *header = (struct jesd216_sfdp_header *)sfdp_buf;
929 int ret;
930 unsigned int key = 0U;
931
932 flexspi_device_config_t config = {
933 .flexspiRootClk = MHZ(50),
934 .flashSize = FLEXSPI_FLSHCR0_FLSHSZ_MASK, /* Max flash size */
935 .ARDSeqNumber = 1,
936 .ARDSeqIndex = READ,
937 };
938
939 if (memc_flexspi_is_running_xip(&data->controller)) {
940 /*
941 * ==== ENTER CRITICAL SECTION ====
942 * No flash access should be performed in critical section. All
943 * code and data accessed must reside in ram.
944 */
945 key = irq_lock();
946 memc_flexspi_wait_bus_idle(&data->controller);
947 }
948
949 /* SFDP spec requires that we downclock the FlexSPI to 50MHz or less */
950 ret = memc_flexspi_update_clock(&data->controller, &config,
951 data->port, MHZ(50));
952 if (ret < 0) {
953 goto _exit;
954 }
955
956 /* Setup initial LUT table and FlexSPI configuration */
957 memcpy(flexspi_lut, flash_flexspi_nor_base_lut, sizeof(flash_flexspi_nor_base_lut));
958
959 ret = memc_flexspi_set_device_config(&data->controller, &config,
960 (uint32_t *)flexspi_lut,
961 FLEXSPI_INSTR_END * MEMC_FLEXSPI_CMD_PER_SEQ,
962 data->port);
963 if (ret < 0) {
964 goto _exit;
965 }
966
967 /* First, check if the JEDEC ID of this flash has explicit support
968 * in this driver
969 */
970 ret = flash_flexspi_nor_check_jedec(data, flexspi_lut);
971 if (ret == 0) {
972 /* Flash was supported, SFDP probe not needed */
973 goto _program_lut;
974 }
975
976 ret = flash_flexspi_nor_sfdp_read_helper(data, 0, sfdp_buf, sizeof(sfdp_buf));
977 if (ret < 0) {
978 goto _exit;
979 }
980
981 LOG_DBG("SFDP header magic: 0x%x", header->magic);
982 if (jesd216_sfdp_magic(header) != JESD216_SFDP_MAGIC) {
983 /* Header was read incorrectly */
984 LOG_WRN("Invalid header, using legacy SPI mode");
985 data->legacy_poll = true;
986 goto _program_lut;
987 }
988
989 if (header->phdr[0].len_dw > ARRAY_SIZE(param_buf)) {
990 /* Not enough space to read parameter table */
991 ret = -ENOBUFS;
992 goto _exit;
993 }
994
995 /* Read basic flash parameter table */
996 ret = flash_flexspi_nor_sfdp_read_helper(data,
997 jesd216_param_addr(&header->phdr[0]),
998 param_buf,
999 sizeof(uint32_t) * header->phdr[0].len_dw);
1000 if (ret < 0) {
1001 goto _exit;
1002 }
1003
1004 /* Configure flash */
1005 ret = flash_flexspi_nor_config_flash(data, header, bfp, flexspi_lut);
1006 if (ret < 0) {
1007 goto _exit;
1008 }
1009
1010 _program_lut:
1011 /*
1012 * Update the FlexSPI with the config structure provided
1013 * from devicetree and the configured LUT
1014 */
1015 ret = memc_flexspi_set_device_config(&data->controller, &data->config,
1016 (uint32_t *)flexspi_lut,
1017 FLEXSPI_INSTR_END * MEMC_FLEXSPI_CMD_PER_SEQ,
1018 data->port);
1019 if (ret < 0) {
1020 return ret;
1021 }
1022
1023 _exit:
1024 memc_flexspi_reset(&data->controller);
1025
1026 if (memc_flexspi_is_running_xip(&data->controller)) {
1027 /* ==== EXIT CRITICAL SECTION ==== */
1028 irq_unlock(key);
1029 }
1030
1031 return ret;
1032 }
1033
flash_flexspi_nor_init(const struct device * dev)1034 static int flash_flexspi_nor_init(const struct device *dev)
1035 {
1036 const struct flash_flexspi_nor_config *config = dev->config;
1037 struct flash_flexspi_nor_data *data = dev->data;
1038 uint32_t vendor_id;
1039
1040 /* First step- use ROM pointer to controller device to create
1041 * a copy of the device structure in RAM we can use while in
1042 * critical sections of code.
1043 */
1044 memcpy(&data->controller, config->controller, sizeof(struct device));
1045
1046 if (!device_is_ready(&data->controller)) {
1047 LOG_ERR("Controller device is not ready");
1048 return -ENODEV;
1049 }
1050
1051 if (flash_flexspi_nor_probe(data)) {
1052 if (memc_flexspi_is_running_xip(&data->controller)) {
1053 /* We can't continue from here- the LUT stored in
1054 * the FlexSPI will be invalid so we cannot XIP.
1055 * Instead, spin here
1056 */
1057 while (1) {
1058 /* Spin */
1059 }
1060 }
1061 LOG_ERR("SFDP probe failed");
1062 return -EIO;
1063 }
1064
1065 /* Set the FlexSPI to full clock speed */
1066 if (memc_flexspi_update_clock(&data->controller, &data->config,
1067 data->port, data->config.flexspiRootClk)) {
1068 LOG_ERR("Could not set flexspi clock speed");
1069 return -ENOTSUP;
1070 }
1071
1072
1073 memc_flexspi_reset(&data->controller);
1074
1075 if (flash_flexspi_nor_read_id(dev, (uint8_t *)&vendor_id)) {
1076 LOG_ERR("Could not read vendor id");
1077 return -EIO;
1078 }
1079 LOG_DBG("Vendor id: 0x%0x", vendor_id);
1080
1081 return 0;
1082 }
1083
1084 static const struct flash_driver_api flash_flexspi_nor_api = {
1085 .erase = flash_flexspi_nor_erase,
1086 .write = flash_flexspi_nor_write,
1087 .read = flash_flexspi_nor_read,
1088 .get_parameters = flash_flexspi_nor_get_parameters,
1089 #if defined(CONFIG_FLASH_PAGE_LAYOUT)
1090 .page_layout = flash_flexspi_nor_pages_layout,
1091 #endif
1092 #if defined(CONFIG_FLASH_JESD216_API)
1093 .sfdp_read = flash_flexspi_nor_sfdp_read,
1094 .read_jedec_id = flash_flexspi_nor_read_id,
1095 #endif
1096 };
1097
1098 #define CONCAT3(x, y, z) x ## y ## z
1099
1100 #define CS_INTERVAL_UNIT(unit) \
1101 CONCAT3(kFLEXSPI_CsIntervalUnit, unit, SckCycle)
1102
1103 #define AHB_WRITE_WAIT_UNIT(unit) \
1104 CONCAT3(kFLEXSPI_AhbWriteWaitUnit, unit, AhbCycle)
1105
1106 #define FLASH_FLEXSPI_DEVICE_CONFIG(n) \
1107 { \
1108 .flexspiRootClk = DT_INST_PROP(n, spi_max_frequency), \
1109 .flashSize = DT_INST_PROP(n, size) / 8 / KB(1), \
1110 .CSIntervalUnit = \
1111 CS_INTERVAL_UNIT( \
1112 DT_INST_PROP(n, cs_interval_unit)), \
1113 .CSInterval = DT_INST_PROP(n, cs_interval), \
1114 .CSHoldTime = DT_INST_PROP(n, cs_hold_time), \
1115 .CSSetupTime = DT_INST_PROP(n, cs_setup_time), \
1116 .dataValidTime = DT_INST_PROP(n, data_valid_time), \
1117 .columnspace = DT_INST_PROP(n, column_space), \
1118 .enableWordAddress = DT_INST_PROP(n, word_addressable), \
1119 .AWRSeqIndex = 0, \
1120 .AWRSeqNumber = 0, \
1121 .ARDSeqIndex = READ, \
1122 .ARDSeqNumber = 1, \
1123 .AHBWriteWaitUnit = \
1124 AHB_WRITE_WAIT_UNIT( \
1125 DT_INST_PROP(n, ahb_write_wait_unit)), \
1126 .AHBWriteWaitInterval = \
1127 DT_INST_PROP(n, ahb_write_wait_interval), \
1128 } \
1129
1130 #define FLASH_FLEXSPI_NOR(n) \
1131 static const struct flash_flexspi_nor_config \
1132 flash_flexspi_nor_config_##n = { \
1133 .controller = DEVICE_DT_GET(DT_INST_BUS(n)), \
1134 }; \
1135 static struct flash_flexspi_nor_data \
1136 flash_flexspi_nor_data_##n = { \
1137 .config = FLASH_FLEXSPI_DEVICE_CONFIG(n), \
1138 .port = DT_INST_REG_ADDR(n), \
1139 .layout = { \
1140 .pages_count = DT_INST_PROP(n, size) / 8 \
1141 / SPI_NOR_SECTOR_SIZE, \
1142 .pages_size = SPI_NOR_SECTOR_SIZE, \
1143 }, \
1144 .flash_parameters = { \
1145 .write_block_size = NOR_WRITE_SIZE, \
1146 .erase_value = NOR_ERASE_VALUE, \
1147 }, \
1148 }; \
1149 \
1150 DEVICE_DT_INST_DEFINE(n, \
1151 flash_flexspi_nor_init, \
1152 NULL, \
1153 &flash_flexspi_nor_data_##n, \
1154 &flash_flexspi_nor_config_##n, \
1155 POST_KERNEL, \
1156 CONFIG_FLASH_INIT_PRIORITY, \
1157 &flash_flexspi_nor_api);
1158
1159 DT_INST_FOREACH_STATUS_OKAY(FLASH_FLEXSPI_NOR)
1160
