1 /*
2 * Copyright (c) 2021 ITE Corporation. All Rights Reserved.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #define DT_DRV_COMPAT ite_it8xxx2_flash_controller
8 #define SOC_NV_FLASH_NODE DT_INST(0, soc_nv_flash)
9
10 #define FLASH_WRITE_BLK_SZ DT_PROP(SOC_NV_FLASH_NODE, write_block_size)
11 #define FLASH_ERASE_BLK_SZ DT_PROP(SOC_NV_FLASH_NODE, erase_block_size)
12
13 #include <string.h>
14
15 #include <zephyr/device.h>
16 #include <zephyr/drivers/flash.h>
17 #include <zephyr/init.h>
18 #include <zephyr/kernel.h>
19 #include <zephyr/linker/linker-defs.h>
20
21 #include <ilm.h>
22 #include <soc.h>
23
24 #define LOG_LEVEL CONFIG_FLASH_LOG_LEVEL
25 #include <zephyr/logging/log.h>
26 LOG_MODULE_REGISTER(flash_ite_it8xxx2);
27
28 #define FLASH_IT8XXX2_REG_BASE \
29 ((struct smfi_it8xxx2_regs *)DT_INST_REG_ADDR(0))
30
31 struct flash_it8xxx2_dev_data {
32 struct k_sem sem;
33 };
34
35 /*
36 * One page program instruction allows maximum 256 bytes (a page) of data
37 * to be programmed.
38 */
39 #define CHIP_FLASH_WRITE_PAGE_MAX_SIZE 256
40 /* Program is run directly from storage */
41 #define CHIP_MAPPED_STORAGE_BASE DT_REG_ADDR(DT_NODELABEL(flash0))
42 /* flash size */
43 #define CHIP_FLASH_SIZE_BYTES DT_REG_SIZE(DT_NODELABEL(flash0))
44 /* protect bank size */
45 #define CHIP_FLASH_BANK_SIZE 0x00001000
46
47 /*
48 * This is the block size of the ILM on the it8xxx2 chip.
49 * The ILM for static code cache, CPU fetch instruction from
50 * ILM(ILM -> CPU)instead of flash(flash -> I-Cache -> CPU) if enabled.
51 */
52 #define IT8XXX2_ILM_BLOCK_SIZE 0x00001000
53
54 /* page program command */
55 #define FLASH_CMD_PAGE_WRITE 0x2
56 /* sector erase command (erase size is 4KB) */
57 #define FLASH_CMD_SECTOR_ERASE 0x20
58 /* command for flash write */
59 #define FLASH_CMD_WRITE FLASH_CMD_PAGE_WRITE
60 /* Write status register */
61 #define FLASH_CMD_WRSR 0x01
62 /* Write disable */
63 #define FLASH_CMD_WRDI 0x04
64 /* Write enable */
65 #define FLASH_CMD_WREN 0x06
66 /* Read status register */
67 #define FLASH_CMD_RS 0x05
68
69 /* Set FSCE# as high level by writing 0 to address xfff_fe00h */
70 #define FLASH_FSCE_HIGH_ADDRESS 0x0FFFFE00
71 /* Set FSCE# as low level by writing data to address xfff_fd00h */
72 #define FLASH_FSCE_LOW_ADDRESS 0x0FFFFD00
73
74 enum flash_status_mask {
75 FLASH_SR_NO_BUSY = 0,
76 /* Internal write operation is in progress */
77 FLASH_SR_BUSY = 0x01,
78 /* Device is memory Write enabled */
79 FLASH_SR_WEL = 0x02,
80
81 FLASH_SR_ALL = (FLASH_SR_BUSY | FLASH_SR_WEL),
82 };
83
84 enum flash_transaction_cmd {
85 CMD_CONTINUE,
86 CMD_END,
87 };
88
89 static const struct flash_parameters flash_it8xxx2_parameters = {
90 .write_block_size = FLASH_WRITE_BLK_SZ,
91 .erase_value = 0xff,
92 };
93
ramcode_reset_i_cache(void)94 void __soc_ram_code ramcode_reset_i_cache(void)
95 {
96 struct gctrl_it8xxx2_regs *const gctrl_regs = GCTRL_IT8XXX2_REGS_BASE;
97
98 /* I-Cache tag sram reset */
99 gctrl_regs->GCTRL_MCCR |= IT8XXX2_GCTRL_ICACHE_RESET;
100 /* Make sure the I-Cache is reset */
101 __asm__ volatile ("fence.i" ::: "memory");
102
103 gctrl_regs->GCTRL_MCCR &= ~IT8XXX2_GCTRL_ICACHE_RESET;
104 __asm__ volatile ("fence.i" ::: "memory");
105 }
106
ramcode_flash_follow_mode(void)107 void __soc_ram_code ramcode_flash_follow_mode(void)
108 {
109 struct smfi_it8xxx2_regs *const flash_regs = FLASH_IT8XXX2_REG_BASE;
110 /*
111 * ECINDAR3-0 are EC-indirect memory address registers.
112 *
113 * Enter follow mode by writing 0xf to low nibble of ECINDAR3 register,
114 * and set high nibble as 0x4 to select internal flash.
115 */
116 flash_regs->SMFI_ECINDAR3 = (EC_INDIRECT_READ_INTERNAL_FLASH |
117 ((FLASH_FSCE_HIGH_ADDRESS >> 24) & GENMASK(3, 0)));
118
119 /* Set FSCE# as high level by writing 0 to address xfff_fe00h */
120 flash_regs->SMFI_ECINDAR2 = (FLASH_FSCE_HIGH_ADDRESS >> 16) & GENMASK(7, 0);
121 flash_regs->SMFI_ECINDAR1 = (FLASH_FSCE_HIGH_ADDRESS >> 8) & GENMASK(7, 0);
122 flash_regs->SMFI_ECINDAR0 = FLASH_FSCE_HIGH_ADDRESS & GENMASK(7, 0);
123
124 /* Writing 0 to EC-indirect memory data register */
125 flash_regs->SMFI_ECINDDR = 0x00;
126 }
127
ramcode_flash_follow_mode_exit(void)128 void __soc_ram_code ramcode_flash_follow_mode_exit(void)
129 {
130 struct smfi_it8xxx2_regs *const flash_regs = FLASH_IT8XXX2_REG_BASE;
131
132 /* Exit follow mode, and keep the setting of selecting internal flash */
133 flash_regs->SMFI_ECINDAR3 = EC_INDIRECT_READ_INTERNAL_FLASH;
134 flash_regs->SMFI_ECINDAR2 = 0x00;
135 }
136
ramcode_flash_fsce_high(void)137 void __soc_ram_code ramcode_flash_fsce_high(void)
138 {
139 struct smfi_it8xxx2_regs *const flash_regs = FLASH_IT8XXX2_REG_BASE;
140 struct gctrl_it8xxx2_regs *const gctrl_regs = GCTRL_IT8XXX2_REGS_BASE;
141
142 /* FSCE# high level */
143 flash_regs->SMFI_ECINDAR1 = (FLASH_FSCE_HIGH_ADDRESS >> 8) & GENMASK(7, 0);
144
145 /*
146 * A short delay (15~30 us) before #CS be driven high to ensure
147 * last byte has been latched in.
148 *
149 * For a loop that writing 0 to WNCKR register for N times, the delay
150 * value will be: ((N-1) / 65.536 kHz) to (N / 65.536 kHz).
151 * So we perform 2 consecutive writes to WNCKR here to ensure the
152 * minimum delay is 15us.
153 */
154 gctrl_regs->GCTRL_WNCKR = 0;
155 gctrl_regs->GCTRL_WNCKR = 0;
156
157 /* Writing 0 to EC-indirect memory data register */
158 flash_regs->SMFI_ECINDDR = 0x00;
159 }
160
ramcode_flash_write_dat(uint8_t wdata)161 void __soc_ram_code ramcode_flash_write_dat(uint8_t wdata)
162 {
163 struct smfi_it8xxx2_regs *const flash_regs = FLASH_IT8XXX2_REG_BASE;
164
165 /* Write data to FMOSI */
166 flash_regs->SMFI_ECINDDR = wdata;
167 }
168
ramcode_flash_transaction(int wlen,uint8_t * wbuf,int rlen,uint8_t * rbuf,enum flash_transaction_cmd cmd_end)169 void __soc_ram_code ramcode_flash_transaction(int wlen, uint8_t *wbuf, int rlen, uint8_t *rbuf,
170 enum flash_transaction_cmd cmd_end)
171 {
172 struct smfi_it8xxx2_regs *const flash_regs = FLASH_IT8XXX2_REG_BASE;
173 int i;
174
175 /* FSCE# with low level */
176 flash_regs->SMFI_ECINDAR1 = (FLASH_FSCE_LOW_ADDRESS >> 8) & GENMASK(7, 0);
177 /* Write data to FMOSI */
178 for (i = 0; i < wlen; i++) {
179 flash_regs->SMFI_ECINDDR = wbuf[i];
180 }
181 /* Read data from FMISO */
182 for (i = 0; i < rlen; i++) {
183 rbuf[i] = flash_regs->SMFI_ECINDDR;
184 }
185 /* FSCE# high level if transaction done */
186 if (cmd_end == CMD_END) {
187 ramcode_flash_fsce_high();
188 }
189 }
190
ramcode_flash_cmd_read_status(enum flash_status_mask mask,enum flash_status_mask target)191 void __soc_ram_code ramcode_flash_cmd_read_status(enum flash_status_mask mask,
192 enum flash_status_mask target)
193 {
194 struct smfi_it8xxx2_regs *const flash_regs = FLASH_IT8XXX2_REG_BASE;
195 uint8_t cmd_rs[] = {FLASH_CMD_RS};
196
197 /* Send read status command */
198 ramcode_flash_transaction(sizeof(cmd_rs), cmd_rs, 0, NULL, CMD_CONTINUE);
199
200 /*
201 * We prefer no timeout here. We can always get the status
202 * we want, or wait for watchdog triggered to check
203 * e-flash's status instead of breaking loop.
204 * This will avoid fetching unknown instruction from e-flash
205 * and causing exception.
206 */
207 while ((flash_regs->SMFI_ECINDDR & mask) != target) {
208 /* read status and check if it is we want. */
209 ;
210 }
211
212 /* transaction done, drive #CS high */
213 ramcode_flash_fsce_high();
214 }
215
ramcode_flash_cmd_write_enable(void)216 void __soc_ram_code ramcode_flash_cmd_write_enable(void)
217 {
218 uint8_t cmd_we[] = {FLASH_CMD_WREN};
219
220 /* enter EC-indirect follow mode */
221 ramcode_flash_follow_mode();
222 /* send write enable command */
223 ramcode_flash_transaction(sizeof(cmd_we), cmd_we, 0, NULL, CMD_END);
224 /* read status and make sure busy bit cleared and write enabled. */
225 ramcode_flash_cmd_read_status(FLASH_SR_ALL, FLASH_SR_WEL);
226 /* exit EC-indirect follow mode */
227 ramcode_flash_follow_mode_exit();
228 }
229
ramcode_flash_cmd_write_disable(void)230 void __soc_ram_code ramcode_flash_cmd_write_disable(void)
231 {
232 uint8_t cmd_wd[] = {FLASH_CMD_WRDI};
233
234 /* enter EC-indirect follow mode */
235 ramcode_flash_follow_mode();
236 /* send write disable command */
237 ramcode_flash_transaction(sizeof(cmd_wd), cmd_wd, 0, NULL, CMD_END);
238 /* make sure busy bit cleared. */
239 ramcode_flash_cmd_read_status(FLASH_SR_ALL, FLASH_SR_NO_BUSY);
240 /* exit EC-indirect follow mode */
241 ramcode_flash_follow_mode_exit();
242 }
243
ramcode_flash_verify(int addr,int size,const char * data)244 int __soc_ram_code ramcode_flash_verify(int addr, int size, const char *data)
245 {
246 int i;
247 uint8_t *wbuf = (uint8_t *)data;
248 uint8_t *flash = (uint8_t *)addr;
249
250 if (data == NULL) {
251 /* verify for erase */
252 for (i = 0; i < size; i++) {
253 if (flash[i] != 0xFF) {
254 return -EINVAL;
255 }
256 }
257 } else {
258 /* verify for write */
259 for (i = 0; i < size; i++) {
260 if (flash[i] != wbuf[i]) {
261 return -EINVAL;
262 }
263 }
264 }
265
266 return 0;
267 }
268
ramcode_flash_cmd_write(int addr,int wlen,uint8_t * wbuf)269 void __soc_ram_code ramcode_flash_cmd_write(int addr, int wlen, uint8_t *wbuf)
270 {
271 int i;
272 uint8_t flash_write[] = {FLASH_CMD_WRITE, ((addr >> 16) & 0xFF),
273 ((addr >> 8) & 0xFF), (addr & 0xFF)};
274
275 /* enter EC-indirect follow mode */
276 ramcode_flash_follow_mode();
277 /* send flash write command (aai word or page program) */
278 ramcode_flash_transaction(sizeof(flash_write), flash_write, 0, NULL, CMD_CONTINUE);
279
280 for (i = 0; i < wlen; i++) {
281 /* send data byte */
282 ramcode_flash_write_dat(wbuf[i]);
283
284 /*
285 * we want to restart the write sequence every IDEAL_SIZE
286 * chunk worth of data.
287 */
288 if (!(++addr % CHIP_FLASH_WRITE_PAGE_MAX_SIZE)) {
289 uint8_t w_en[] = {FLASH_CMD_WREN};
290
291 ramcode_flash_fsce_high();
292 /* make sure busy bit cleared. */
293 ramcode_flash_cmd_read_status(FLASH_SR_BUSY, FLASH_SR_NO_BUSY);
294 /* send write enable command */
295 ramcode_flash_transaction(sizeof(w_en), w_en, 0, NULL, CMD_END);
296 /* make sure busy bit cleared and write enabled. */
297 ramcode_flash_cmd_read_status(FLASH_SR_ALL, FLASH_SR_WEL);
298 /* re-send write command */
299 flash_write[1] = (addr >> 16) & GENMASK(7, 0);
300 flash_write[2] = (addr >> 8) & GENMASK(7, 0);
301 flash_write[3] = addr & GENMASK(7, 0);
302 ramcode_flash_transaction(sizeof(flash_write), flash_write,
303 0, NULL, CMD_CONTINUE);
304 }
305 }
306 ramcode_flash_fsce_high();
307 /* make sure busy bit cleared. */
308 ramcode_flash_cmd_read_status(FLASH_SR_BUSY, FLASH_SR_NO_BUSY);
309 /* exit EC-indirect follow mode */
310 ramcode_flash_follow_mode_exit();
311 }
312
ramcode_flash_write(int addr,int wlen,const char * wbuf)313 void __soc_ram_code ramcode_flash_write(int addr, int wlen, const char *wbuf)
314 {
315 ramcode_flash_cmd_write_enable();
316 ramcode_flash_cmd_write(addr, wlen, (uint8_t *)wbuf);
317 ramcode_flash_cmd_write_disable();
318 }
319
ramcode_flash_cmd_erase(int addr,int cmd)320 void __soc_ram_code ramcode_flash_cmd_erase(int addr, int cmd)
321 {
322 uint8_t cmd_erase[] = {cmd, ((addr >> 16) & 0xFF),
323 ((addr >> 8) & 0xFF), (addr & 0xFF)};
324
325 /* enter EC-indirect follow mode */
326 ramcode_flash_follow_mode();
327 /* send erase command */
328 ramcode_flash_transaction(sizeof(cmd_erase), cmd_erase, 0, NULL, CMD_END);
329 /* make sure busy bit cleared. */
330 ramcode_flash_cmd_read_status(FLASH_SR_BUSY, FLASH_SR_NO_BUSY);
331 /* exit EC-indirect follow mode */
332 ramcode_flash_follow_mode_exit();
333 }
334
ramcode_flash_erase(int addr,int cmd)335 void __soc_ram_code ramcode_flash_erase(int addr, int cmd)
336 {
337 ramcode_flash_cmd_write_enable();
338 ramcode_flash_cmd_erase(addr, cmd);
339 ramcode_flash_cmd_write_disable();
340 }
341
342 /* Read data from flash */
flash_it8xxx2_read(const struct device * dev,off_t offset,void * data,size_t len)343 static int __soc_ram_code flash_it8xxx2_read(const struct device *dev, off_t offset, void *data,
344 size_t len)
345 {
346 struct smfi_it8xxx2_regs *const flash_regs = FLASH_IT8XXX2_REG_BASE;
347 uint8_t *data_t = data;
348 int i;
349
350 for (i = 0; i < len; i++) {
351 flash_regs->SMFI_ECINDAR3 = EC_INDIRECT_READ_INTERNAL_FLASH;
352 flash_regs->SMFI_ECINDAR2 = (offset >> 16) & GENMASK(7, 0);
353 flash_regs->SMFI_ECINDAR1 = (offset >> 8) & GENMASK(7, 0);
354 flash_regs->SMFI_ECINDAR0 = (offset & GENMASK(7, 0));
355
356 /*
357 * Read/Write to this register will access one byte on the
358 * flash with the 32-bit flash address defined in ECINDAR3-0
359 */
360 data_t[i] = flash_regs->SMFI_ECINDDR;
361
362 offset++;
363 }
364
365 return 0;
366 }
367
368 /* Write data to the flash, page by page */
flash_it8xxx2_write(const struct device * dev,off_t offset,const void * src_data,size_t len)369 static int __soc_ram_code flash_it8xxx2_write(const struct device *dev, off_t offset,
370 const void *src_data, size_t len)
371 {
372 struct flash_it8xxx2_dev_data *data = dev->data;
373 int ret = -EINVAL;
374 unsigned int key;
375
376 /*
377 * Check that the offset and length are multiples of the write
378 * block size.
379 */
380 if ((offset % FLASH_WRITE_BLK_SZ) != 0) {
381 return -EINVAL;
382 }
383 if ((len % FLASH_WRITE_BLK_SZ) != 0) {
384 return -EINVAL;
385 }
386 if (!it8xxx2_is_ilm_configured()) {
387 return -EACCES;
388 }
389
390 k_sem_take(&data->sem, K_FOREVER);
391 /*
392 * CPU can't fetch instruction from flash while use
393 * EC-indirect follow mode to access flash, interrupts need to be
394 * disabled.
395 */
396 key = irq_lock();
397
398 ramcode_flash_write(offset, len, src_data);
399 ramcode_reset_i_cache();
400 /* Get the ILM address of a flash offset. */
401 offset |= CHIP_MAPPED_STORAGE_BASE;
402 ret = ramcode_flash_verify(offset, len, src_data);
403
404 irq_unlock(key);
405
406 k_sem_give(&data->sem);
407
408 return ret;
409 }
410
411 /* Erase multiple blocks */
flash_it8xxx2_erase(const struct device * dev,off_t offset,size_t len)412 static int __soc_ram_code flash_it8xxx2_erase(const struct device *dev, off_t offset, size_t len)
413 {
414 struct flash_it8xxx2_dev_data *data = dev->data;
415 int v_size = len, v_addr = offset, ret = -EINVAL;
416 unsigned int key;
417
418 /*
419 * Check that the offset and length are multiples of the write
420 * erase block size.
421 */
422 if ((offset % FLASH_ERASE_BLK_SZ) != 0) {
423 return -EINVAL;
424 }
425 if ((len % FLASH_ERASE_BLK_SZ) != 0) {
426 return -EINVAL;
427 }
428 if (!it8xxx2_is_ilm_configured()) {
429 return -EACCES;
430 }
431
432 k_sem_take(&data->sem, K_FOREVER);
433 /*
434 * CPU can't fetch instruction from flash while use
435 * EC-indirect follow mode to access flash, interrupts need to be
436 * disabled.
437 */
438 key = irq_lock();
439
440 /* Always use sector erase command */
441 for (; len > 0; len -= FLASH_ERASE_BLK_SZ) {
442 ramcode_flash_erase(offset, FLASH_CMD_SECTOR_ERASE);
443 offset += FLASH_ERASE_BLK_SZ;
444 }
445 ramcode_reset_i_cache();
446 /* get the ILM address of a flash offset. */
447 v_addr |= CHIP_MAPPED_STORAGE_BASE;
448 ret = ramcode_flash_verify(v_addr, v_size, NULL);
449
450 irq_unlock(key);
451
452 k_sem_give(&data->sem);
453
454 return ret;
455 }
456
457 static const struct flash_parameters *
flash_it8xxx2_get_parameters(const struct device * dev)458 flash_it8xxx2_get_parameters(const struct device *dev)
459 {
460 ARG_UNUSED(dev);
461
462 return &flash_it8xxx2_parameters;
463 }
464
flash_it8xxx2_init(const struct device * dev)465 static int flash_it8xxx2_init(const struct device *dev)
466 {
467 struct smfi_it8xxx2_regs *const flash_regs = FLASH_IT8XXX2_REG_BASE;
468 struct flash_it8xxx2_dev_data *data = dev->data;
469
470 /* By default, select internal flash for indirect fast read. */
471 flash_regs->SMFI_ECINDAR3 = EC_INDIRECT_READ_INTERNAL_FLASH;
472
473 /*
474 * If the embedded flash's size of this part number is larger
475 * than 256K-byte, enable the page program cycle constructed
476 * by EC-Indirect Follow Mode.
477 */
478 flash_regs->SMFI_FLHCTRL6R |= IT8XXX2_SMFI_MASK_ECINDPP;
479
480 /* Initialize mutex for flash controller */
481 k_sem_init(&data->sem, 1, 1);
482
483 return 0;
484 }
485
486 #if defined(CONFIG_FLASH_PAGE_LAYOUT)
487 static const struct flash_pages_layout dev_layout = {
488 .pages_count = DT_REG_SIZE(SOC_NV_FLASH_NODE) /
489 DT_PROP(SOC_NV_FLASH_NODE, erase_block_size),
490 .pages_size = DT_PROP(SOC_NV_FLASH_NODE, erase_block_size),
491 };
492
flash_it8xxx2_pages_layout(const struct device * dev,const struct flash_pages_layout ** layout,size_t * layout_size)493 static void flash_it8xxx2_pages_layout(const struct device *dev,
494 const struct flash_pages_layout **layout,
495 size_t *layout_size)
496 {
497 *layout = &dev_layout;
498 *layout_size = 1;
499 }
500 #endif /* CONFIG_FLASH_PAGE_LAYOUT */
501
502 static const struct flash_driver_api flash_it8xxx2_api = {
503 .erase = flash_it8xxx2_erase,
504 .write = flash_it8xxx2_write,
505 .read = flash_it8xxx2_read,
506 .get_parameters = flash_it8xxx2_get_parameters,
507 #if defined(CONFIG_FLASH_PAGE_LAYOUT)
508 .page_layout = flash_it8xxx2_pages_layout,
509 #endif
510 };
511
512 static struct flash_it8xxx2_dev_data flash_it8xxx2_data;
513
514 DEVICE_DT_INST_DEFINE(0, flash_it8xxx2_init, NULL,
515 &flash_it8xxx2_data, NULL,
516 PRE_KERNEL_1,
517 CONFIG_FLASH_INIT_PRIORITY,
518 &flash_it8xxx2_api);
519
