1 /*
2  * Copyright (c) 2022 Intel Corporation
3  *
4  * SPDX-License-Identifier: Apache-2.0
5  */
6 
7 #ifndef CAD_QSPI_NOR_LL_H
8 #define CAD_QSPI_NOR_LL_H
9 
10 #include <zephyr/device.h>
11 
12 #define CAD_QSPI_MICRON_N25Q_SUPPORT		CONFIG_CAD_QSPI_MICRON_N25Q_SUPPORT
13 
14 #define CAD_INVALID				-1
15 #define CAD_QSPI_ERROR				-2
16 
17 #define CAD_QSPI_ADDR_FASTREAD			0
18 #define CAD_QSPI_ADDR_FASTREAD_DUAL_IO		1
19 #define CAD_QSPI_ADDR_FASTREAD_QUAD_IO		2
20 #define CAT_QSPI_ADDR_SINGLE_IO			0
21 #define CAT_QSPI_ADDR_DUAL_IO			1
22 #define CAT_QSPI_ADDR_QUAD_IO			2
23 
24 #define CAD_QSPI_BANK_ADDR(x)			((x) >> 24)
25 #define CAD_QSPI_BANK_ADDR_MSK			GENMASK(31, 24)
26 
27 #define CAD_QSPI_COMMAND_TIMEOUT		0x10000000
28 
29 #define CAD_QSPI_CFG				0x0
30 #define CAD_QSPI_CFG_BAUDDIV_MSK		0xff87ffff
31 #define CAD_QSPI_CFG_BAUDDIV(x)			FIELD_PREP(0x780000, x)
32 #define CAD_QSPI_CFG_CS_MSK			~0x3c00
33 #define CAD_QSPI_CFG_CS(x)			(((x) << 11))
34 #define CAD_QSPI_CFG_ENABLE			(BIT(0))
35 #define CAD_QSPI_CFG_ENDMA_CLR_MSK		0xffff7fff
36 #define CAD_QSPI_CFG_IDLE			(BIT(31))
37 #define CAD_QSPI_CFG_SELCLKPHASE_CLR_MSK	0xfffffffb
38 #define CAD_QSPI_CFG_SELCLKPOL_CLR_MSK		0xfffffffd
39 
40 #define CAD_QSPI_DELAY				0xc
41 #define CAD_QSPI_DELAY_CSSOT(x)			(FIELD_GET(0xff, (x)) << 0)
42 #define CAD_QSPI_DELAY_CSEOT(x)			(FIELD_GET(0xff, (x)) << 8)
43 #define CAD_QSPI_DELAY_CSDADS(x)		(FIELD_GET(0xff, (x)) << 16)
44 #define CAD_QSPI_DELAY_CSDA(x)			(FIELD_GET(0xff, (x)) << 24)
45 
46 #define CAD_QSPI_DEVSZ				0x14
47 #define CAD_QSPI_DEVSZ_ADDR_BYTES(x)		((x) << 0)
48 #define CAD_QSPI_DEVSZ_BYTES_PER_PAGE(x)	((x) << 4)
49 #define CAD_QSPI_DEVSZ_BYTES_PER_BLOCK(x)	((x) << 16)
50 
51 #define CAD_QSPI_DEVWR				0x8
52 #define CAD_QSPI_DEVRD				0x4
53 #define CAD_QSPI_DEV_OPCODE(x)			(FIELD_GET(0xff, (x)) << 0)
54 #define CAD_QSPI_DEV_INST_TYPE(x)		(FIELD_GET(0x03, (x)) << 8)
55 #define CAD_QSPI_DEV_ADDR_TYPE(x)		(FIELD_GET(0x03, (x)) << 12)
56 #define CAD_QSPI_DEV_DATA_TYPE(x)		(FIELD_GET(0x03, (x)) << 16)
57 #define CAD_QSPI_DEV_MODE_BIT(x)		(FIELD_GET(0x01, (x)) << 20)
58 #define CAD_QSPI_DEV_DUMMY_CLK_CYCLE(x)		(FIELD_GET(0x0f, (x)) << 24)
59 
60 #define CAD_QSPI_FLASHCMD			0x90
61 #define CAD_QSPI_FLASHCMD_ADDR			0x94
62 #define CAD_QSPI_FLASHCMD_EXECUTE		0x1
63 #define CAD_QSPI_FLASHCMD_EXECUTE_STAT		0x2
64 #define CAD_QSPI_FLASHCMD_NUM_DUMMYBYTES_MAX	5
65 #define CAD_QSPI_FLASHCMD_NUM_DUMMYBYTES(x)     (FIELD_PREP(0x000f80, (x)))
66 #define CAD_QSPI_FLASHCMD_OPCODE(x)             (FIELD_GET(0xff, (x)) << 24)
67 #define CAD_QSPI_FLASHCMD_ENRDDATA(x)           (FIELD_GET(1, (x)) << 23)
68 #define CAD_QSPI_FLASHCMD_NUMRDDATABYTES(x)     (FIELD_GET(0xf, (x)) << 20)
69 #define CAD_QSPI_FLASHCMD_ENCMDADDR(x)          (FIELD_GET(1, (x)) << 19)
70 #define CAD_QSPI_FLASHCMD_ENMODEBIT(x)		(FIELD_GET(1, (x)) << 18)
71 #define CAD_QSPI_FLASHCMD_NUMADDRBYTES(x)	(FIELD_GET(0x3, (x)) << 16)
72 #define CAD_QSPI_FLASHCMD_ENWRDATA(x)		(FIELD_GET(1, (x)) << 15)
73 #define CAD_QSPI_FLASHCMD_NUMWRDATABYTES(x)	(FIELD_GET(0x7, (x)) << 12)
74 #define CAD_QSPI_FLASHCMD_NUMDUMMYBYTES(x)	(FIELD_GET(0x1f, (x)) << 7)
75 #define CAD_QSPI_FLASHCMD_RDDATA0		0xa0
76 #define CAD_QSPI_FLASHCMD_RDDATA1		0xa4
77 #define CAD_QSPI_FLASHCMD_WRDATA0		0xa8
78 #define CAD_QSPI_FLASHCMD_WRDATA1		0xac
79 
80 #define CAD_QSPI_RDDATACAP			0x10
81 #define CAD_QSPI_RDDATACAP_BYP(x)		(FIELD_GET(1, (x)) << 0)
82 #define CAD_QSPI_RDDATACAP_DELAY(x)		(FIELD_GET(0xf, (x)) << 1)
83 
84 #define CAD_QSPI_REMAPADDR			0x24
85 #define CAD_QSPI_REMAPADDR_VALUE_SET(x)		(FIELD_GET(0xffffffff, (x)) << 0)
86 
87 #define CAD_QSPI_SRAMPART			0x18
88 #define CAD_QSPI_SRAMFILL			0x2c
89 #define CAD_QSPI_SRAMPART_ADDR(x)		(FIELD_GET(0x3ff, ((x) >> 0)))
90 #define CAD_QSPI_SRAM_FIFO_ENTRY_COUNT		(512 / sizeof(uint32_t))
91 #define CAD_QSPI_SRAMFILL_INDWRPART(x)		(FIELD_GET(0x00ffff, ((x) >> 16)))
92 #define CAD_QSPI_SRAMFILL_INDRDPART(x)		(FIELD_GET(0x00ffff, ((x) >> 0)))
93 
94 #define CAD_QSPI_SELCLKPHASE(x)			(FIELD_GET(1, (x)) << 2)
95 #define CAD_QSPI_SELCLKPOL(x)			(FIELD_GET(1, (x)) << 1)
96 
97 #define CAD_QSPI_STIG_FLAGSR_PROGRAMREADY(x)	(FIELD_GET(1, ((x) >> 7)))
98 #define CAD_QSPI_STIG_FLAGSR_ERASEREADY(x)	(FIELD_GET(1, ((x) >> 7)))
99 #define CAD_QSPI_STIG_FLAGSR_ERASEERROR(x)	(FIELD_GET(1, ((x) >> 5)))
100 #define CAD_QSPI_STIG_FLAGSR_PROGRAMERROR(x)	(FIELD_GET(1, ((x) >> 4)))
101 #define CAD_QSPI_STIG_OPCODE_CLFSR		0x50
102 #define CAD_QSPI_STIG_OPCODE_RDID		0x9f
103 #define CAD_QSPI_STIG_OPCODE_WRDIS		0x4
104 #define CAD_QSPI_STIG_OPCODE_WREN		0x6
105 #define CAD_QSPI_STIG_OPCODE_SUBSEC_ERASE	0x20
106 #define CAD_QSPI_STIG_OPCODE_SEC_ERASE		0xd8
107 #define CAD_QSPI_STIG_OPCODE_WREN_EXT_REG	0xc5
108 #define CAD_QSPI_STIG_OPCODE_DIE_ERASE		0xc4
109 #define CAD_QSPI_STIG_OPCODE_BULK_ERASE		0xc7
110 #define CAD_QSPI_STIG_OPCODE_RDSR		0x5
111 #define CAD_QSPI_STIG_OPCODE_RDFLGSR		0x70
112 #define CAD_QSPI_STIG_OPCODE_RESET_EN		0x66
113 #define CAD_QSPI_STIG_OPCODE_RESET_MEM		0x99
114 #define CAD_QSPI_STIG_RDID_CAPACITYID(x)	(FIELD_GET(0xff, ((x) >> 16)))
115 #define CAD_QSPI_STIG_SR_BUSY(x)		(FIELD_GET(1, ((x))))
116 
117 
118 #define CAD_QSPI_INST_SINGLE			0
119 #define CAD_QSPI_INST_DUAL			1
120 #define CAD_QSPI_INST_QUAD			2
121 
122 #define CAD_QSPI_INDRDSTADDR			0x68
123 #define CAD_QSPI_INDRDCNT			0x6c
124 #define CAD_QSPI_INDRD				0x60
125 #define CAD_QSPI_INDRD_RD_STAT(x)		(FIELD_GET(1, ((x) >> 2)))
126 #define CAD_QSPI_INDRD_START			1
127 #define CAD_QSPI_INDRD_IND_OPS_DONE		0x20
128 
129 #define CAD_QSPI_INDWR				0x70
130 #define CAD_QSPI_INDWR_RDSTAT(x)		(FIELD_GET(1, ((x) >> 2)))
131 #define CAD_QSPI_INDWRSTADDR			0x78
132 #define CAD_QSPI_INDWRCNT			0x7c
133 #define CAD_QSPI_INDWR				0x70
134 #define CAD_QSPI_INDWR_START			0x1
135 #define CAD_QSPI_INDWR_INDDONE			0x20
136 
137 #define CAD_QSPI_INT_STATUS_ALL			0x0000ffff
138 
139 #define CAD_QSPI_N25Q_DIE_SIZE			0x02000000
140 #define CAD_QSPI_BANK_SIZE			0x01000000
141 #define CAD_QSPI_PAGE_SIZE			0x00000100
142 
143 #define CAD_QSPI_IRQMSK				0x44
144 
145 #define CAD_QSPI_SUBSECTOR_SIZE			CONFIG_CAD_QSPI_NOR_SUBSECTOR_SIZE
146 #define QSPI_ADDR_BYTES				CONFIG_QSPI_ADDR_BYTES
147 #define QSPI_BYTES_PER_DEV			CONFIG_QSPI_BYTES_PER_DEV
148 #define QSPI_BYTES_PER_BLOCK			CONFIG_QSPI_BYTES_PER_BLOCK
149 
150 #define QSPI_FAST_READ				0xb
151 
152 #define QSPI_WRITE				0x2
153 
154 /* QSPI CONFIGURATIONS */
155 
156 #define QSPI_CONFIG_CPOL			1
157 #define QSPI_CONFIG_CPHA			1
158 
159 #define QSPI_CONFIG_CSSOT			0x14
160 #define QSPI_CONFIG_CSEOT			0x14
161 #define QSPI_CONFIG_CSDADS			0xff
162 #define QSPI_CONFIG_CSDA			0xc8
163 
164 struct cad_qspi_params {
165 	uintptr_t	reg_base;
166 	uintptr_t	data_base;
167 	uint32_t	data_size;
168 	int		clk_rate;
169 	uint32_t	qspi_device_size;
170 	int		cad_qspi_cs;
171 };
172 
173 int cad_qspi_init(struct cad_qspi_params *cad_params,
174 	uint32_t clk_phase, uint32_t clk_pol, uint32_t csda,
175 	uint32_t csdads, uint32_t cseot, uint32_t cssot,
176 	uint32_t rddatacap);
177 void cad_qspi_set_chip_select(struct cad_qspi_params *cad_params,
178 	int cs);
179 int cad_qspi_erase(struct cad_qspi_params *cad_params,
180 	uint32_t offset, uint32_t size);
181 int cad_qspi_write(struct cad_qspi_params *cad_params, void *buffer,
182 	uint32_t offset, uint32_t size);
183 int cad_qspi_read(struct cad_qspi_params *cad_params, void *buffer,
184 	uint32_t offset, uint32_t size);
185 int cad_qspi_update(struct cad_qspi_params *cad_params, void *buffer,
186 	uint32_t offset, uint32_t size);
187 
188 #endif
189