1 /*
2  * Copyright (c) 2023, Intel Corporation.
3  *
4  * SPDX-License-Identifier: Apache-2.0
5  */
6 
7 #ifndef CDNS_NAND_LL_H
8 #define CDNS_NAND_LL_H
9 
10 #include <zephyr/device.h>
11 #include <zephyr/kernel.h>
12 #include <zephyr/logging/log.h>
13 
14 #define NAND_INT_SEM_TAKE(param_ptr)						\
15 		COND_CODE_1(IS_ENABLED(CONFIG_CDNS_NAND_INTERRUPT_SUPPORT),     \
16 		(k_sem_take(&(param_ptr->interrupt_sem_t), K_FOREVER)), ())
17 
18 #define CNF_GET_INIT_COMP(x)				(FIELD_GET(BIT(9), x))
19 #define CNF_GET_INIT_FAIL(x)				(FIELD_GET(BIT(10), x))
20 #define CNF_GET_CTRL_BUSY(x)				(FIELD_GET(BIT(8), x))
21 #define GET_PAGE_SIZE(x)				(FIELD_GET(GENMASK(15, 0), x))
22 #define GET_PAGES_PER_BLOCK(x)				(FIELD_GET(GENMASK(15, 0), x))
23 #define GET_SPARE_SIZE(x)				(FIELD_GET(GENMASK(31, 16), x))
24 #define ONFI_TIMING_MODE_SDR(x)				(FIELD_GET(GENMASK(15, 0), x))
25 #define ONFI_TIMING_MODE_NVDDR(x)			(FIELD_GET(GENMASK(31, 15), x))
26 
27 /* Controller parameter registers */
28 #define CNF_GET_NLUNS(x)				(FIELD_GET(GENMASK(7, 0), x))
29 #define CNF_GET_DEV_TYPE(x)				(FIELD_GET(GENMASK(31, 30), x))
30 
31 #define CNF_CTRLPARAM_VERSION				(0x800)
32 #define CNF_CTRLPARAM_FEATURE				(0x804)
33 #define CNF_CTRLPARAM_MFR_ID				(0x808)
34 #define CNF_CTRLPARAM_DEV_AREA				(0x80C)
35 #define CNF_CTRLPARAM_DEV_PARAMS0			(0x810)
36 #define CNF_CTRLPARAM_DEV_PARAMS1			(0x814)
37 #define CNF_CTRLPARAM_DEV_FEATUERS			(0x818)
38 #define CNF_CTRLPARAM_DEV_BLOCKS_PLUN		        (0x81C)
39 #define CNF_CTRLPARAM_ONFI_TIMING_0			(0x824)
40 #define CNF_CTRLPARAM(_base, _reg)			(_base + (CNF_CTRLPARAM_##_reg))
41 
42 #define CNF_CMDREG_CTRL_STATUS				(0x118)
43 #define CNF_CMDREG(_base, _reg)				(_base + (CNF_CMDREG_##_reg))
44 #define PINSEL(_x)					(PINSEL##_x)
45 #define PIN(_x)						PINSEL(_x)##SEL
46 
47 /*Hardware Features Support*/
48 #define CNF_HW_NF_16_SUPPORT(x)				(FIELD_GET(BIT(29), x))
49 #define CNF_HW_NVDDR_SS_SUPPORT(x)			(FIELD_GET(BIT(27), x))
50 #define CNF_HW_ASYNC_SUPPORT(x)				(FIELD_GET(BIT(26), x))
51 #define CNF_HW_DMA_DATA_WIDTH_SUPPORT(x)		(FIELD_GET(BIT(21), x))
52 #define CNF_HW_DMA_ADDR_WIDTH_SUPPORT(x)		(FIELD_GET(BIT(20), x))
53 #define CNF_HW_DI_PR_SUPPORT(x)				(FIELD_GET(BIT(14), x))
54 #define CNF_HW_ECC_SUPPORT(x)				(FIELD_GET(BIT(17), x))
55 #define CNF_HW_RMP_SUPPORT(x)				(FIELD_GET(BIT(12), x))
56 #define CNF_HW_DI_CRC_SUPPORT(x)			(FIELD_GET(BIT(8), x))
57 #define CNF_HW_WR_PT_SUPPORT(x)				(FIELD_GET(BIT(9), x))
58 
59 /* Device types */
60 #define CNF_DT_UNKNOWN					(0x00)
61 #define CNF_DT_ONFI					(0x01)
62 #define CNF_DT_JEDEC					(0x02)
63 #define CNF_DT_LEGACY					(0x03)
64 
65 /* Controller configuration registers */
66 #define CNF_CTRLCFG_TRANS_CFG0				(0x400)
67 #define CNF_CTRLCFG_TRANS_CFG1				(0x404)
68 #define CNF_CTRLCFG_LONG_POLL				(0x408)
69 #define CNF_CTRLCFG_SHORT_POLL				(0x40C)
70 #define CNF_CTRLCFG_DEV_STAT				(0x410)
71 #define CNF_CTRLCFG_DEV_LAYOUT				(0x424)
72 #define CNF_CTRLCFG_ECC_CFG0				(0x428)
73 #define CNF_CTRLCFG_ECC_CFG1				(0x42C)
74 #define CNF_CTRLCFG_MULTIPLANE_CFG			(0x434)
75 #define CNF_CTRLCFG_CACHE_CFG				(0x438)
76 #define CNF_CTRLCFG_DMA_SETTINGS			(0x43C)
77 #define CNF_CTRLCFG_FIFO_TLEVEL				(0x454)
78 
79 #define CNF_CTRLCFG(_base, _reg)			(_base + (CNF_CTRLCFG_##_reg))
80 
81 /* Data integrity registers */
82 #define CNF_DI_PAR_EN					(0)
83 #define CNF_DI_CRC_EN					(1)
84 #define CNF_DI_CONTROL					(0x700)
85 #define CNF_DI_INJECT0					(0x704)
86 #define CNF_DI_INJECT1					(0x708)
87 #define CNF_DI_ERR_REG_ADDR				(0x70C)
88 #define CNF_DI_INJECT2					(0x710)
89 
90 #define CNF_DI(_base, _reg)				(_base + (CNF_DI_##_reg))
91 
92 /* Thread idle timeout */
93 #define THREAD_IDLE_TIME_OUT				500U
94 
95 /* Operation work modes */
96 #define CNF_OPR_WORK_MODE_SDR				(0)
97 #define CNF_OPR_WORK_MODE_NVDDR				(1)
98 #define CNF_OPR_WORK_MODE_SDR_MASK                      (GENMASK(1, 0))
99 #define CNF_OPR_WORK_MODE_NVDDR_MASK			(BIT(0))
100 
101 #define ONFI_INTERFACE					(0x01)
102 #define NV_DDR_TIMING_READ				(16)
103 
104 /* Interrupt register field offsets */
105 #define INTERRUPT_STATUS_REG				(0x0114)
106 #define THREAD_INTERRUPT_STATUS				(0x0138)
107 
108 /* Mini controller DLL PHY controller register field offsets */
109 #define CNF_DLL_PHY_RST_N				(24)
110 #define CNF_DLL_PHY_EXT_WR_MODE				(17)
111 #define CNF_DLL_PHY_EXT_RD_MODE				(16)
112 
113 #define CNF_MINICTRL_WP_SETTINGS			(0x1000)
114 #define CNF_MINICTRL_RBN_SETTINGS			(0x1004)
115 #define CNF_MINICTRL_CMN_SETTINGS			(0x1008)
116 #define CNF_MINICTRL_SKIP_BYTES_CFG			(0x100C)
117 #define CNF_MINICTRL_SKIP_BYTES_OFFSET			(0x1010)
118 #define CNF_MINICTRL_TOGGLE_TIMINGS0			(0x1014)
119 #define CNF_MINICTRL_TOGGLE_TIMINGS1			(0x1018)
120 #define CNF_MINICTRL_ASYNC_TOGGLE_TIMINGS		(0x101C)
121 #define CNF_MINICTRL_SYNC_TIMINGS			(0x1020)
122 #define CNF_MINICTRL_DLL_PHY_CTRL			(0x1034)
123 
124 #define CNF_MINICTRL(_base, _reg)			(_base + (CNF_MINICTRL_##_reg))
125 
126 /* Async mode register field offsets */
127 #define CNF_ASYNC_TIMINGS_TRH				FIELD_PREP(GENMASK(28, 24), 2)
128 #define CNF_ASYNC_TIMINGS_TRP				FIELD_PREP(GENMASK(20, 16), 4)
129 #define CNF_ASYNC_TIMINGS_TWH				FIELD_PREP(GENMASK(12, 8), 2)
130 #define CNF_ASYNC_TIMINGS_TWP				FIELD_PREP(GENMASK(4, 0), 4)
131 
132 /* Mini controller common settings register field offsets */
133 #define CNF_CMN_SETTINGS_WR_WUP				(20)
134 #define CNF_CMN_SETTINGS_RD_WUP				(16)
135 #define CNF_CMN_SETTINGS_DEV16				(8)
136 #define CNF_CMN_SETTINGS_OPR				(0)
137 
138 /* Interrupt status register. */
139 #define INTR_STATUS					(0x0110)
140 #define GINTR_ENABLE					(31)
141 #define INTERRUPT_DISABLE				(0)
142 #define INTERRUPT_ENABLE				(1)
143 
144 /* CDMA Command type descriptor*/
145 /* CDMA Command type Erase*/
146 #define CNF_CMD_ERASE					(0x1000)
147 /* CDMA Program Page type */
148 #define CNF_CMD_WR					(0x2100)
149 /* CDMA Read Page type */
150 #define CNF_CMD_RD					(0x2200)
151 #define DMA_MS_SEL					(1)
152 #define VOL_ID						(0)
153 #define CDMA_CF_DMA_MASTER				(10)
154 #define CDMA_CF_DMA_MASTER_SET(x)			FIELD_PREP(BIT(CDMA_CF_DMA_MASTER), x)
155 #define F_CFLAGS_VOL_ID					(4)
156 #define F_CFLAGS_VOL_ID_SET(x)				FIELD_PREP(GENMASK(7, 4), x)
157 #define CDMA_CF_INT					(8)
158 #define CDMA_CF_INT_SET				        BIT(CDMA_CF_INT)
159 #define	COMMON_SET_DEVICE_16BIT				(8)
160 #define CDNS_READ					(0)
161 #define CDNS_WRITE					(1)
162 #define MAX_PAGES_IN_ONE_DSC				(8)
163 #define CFLAGS_MPTRPC					(0)
164 #define CFLAGS_MPTRPC_SET				FIELD_PREP(BIT(CFLAGS_MPTRPC), 1)
165 #define CFLAGS_FPTRPC					(1)
166 #define CFLAGS_FPTRPC_SET				FIELD_PREP(BIT(CFLAGS_FPTRPC), 1)
167 #define CFLAGS_CONT					(9)
168 #define CFLAGS_CONT_SET					FIELD_PREP(BIT(CFLAGS_CONT), 1)
169 #define CLEAR_ALL_INTERRUPT                             (0xFFFFFFFF)
170 #define ENABLE                                          (1)
171 #define DISABLE                                         (0)
172 #define DEV_STAT_DEF_VALUE                              (0x40400000)
173 
174 /*Command Resister*/
175 #define CDNS_CMD_REG0					(0x00)
176 #define CDNS_CMD_REG1					(0x04)
177 #define CDNS_CMD_REG2					(0x08)
178 #define CDNS_CMD_REG3					(0x0C)
179 #define CMD_STATUS_PTR_ADDR				(0x10)
180 #define CMD_STAT_CMD_STATUS				(0x14)
181 #define CDNS_CMD_REG4					(0x20)
182 
183 /* Cdns Nand Operation Modes*/
184 #define CT_CDMA_MODE					(0)
185 #define CT_PIO_MODE					(1)
186 #define CT_GENERIC_MODE					(3)
187 #define OPERATING_MODE_CDMA				(0)
188 #define OPERATING_MODE_PIO				(1)
189 #define OPERATING_MODE_GENERIC				(2)
190 
191 #define THR_STATUS					(0x120)
192 #define CMD_0_THREAD_POS				(24)
193 #define CMD_0_THREAD_POS_SET(x)                         (FIELD_PREP(GENMASK(26, 24), x))
194 #define CMD_0_C_MODE					(30)
195 #define CMD_0_C_MODE_SET(x)                             (FIELD_PREP(GENMASK(31, 30), x))
196 #define CMD_0_VOL_ID_SET(x)                             (FIELD_PREP(GENMASK(19, 16), x))
197 #define PIO_SET_FEA_MODE				(0x0100)
198 #define SET_FEAT_TIMING_MODE_ADDRESS			(0x01)
199 
200  /* default thread number*/
201 #define NF_TDEF_TRD_NUM					(0)
202 
203 /* NF device number */
204 #define NF_TDEF_DEV_NUM					(0)
205 #define F_OTE						(16)
206 #define F_BURST_SEL_SET(x)				(FIELD_PREP(GENMASK(7, 0), x))
207 
208 /* DMA maximum burst size (0-127)*/
209 #define NF_TDEF_BURST_SEL				(127)
210 #define NF_DMA_SETTING					(0x043C)
211 #define NF_PRE_FETCH					(0x0454)
212 #define PRE_FETCH_VALUE					(1024/8)
213 #define NF_FIFO_TRIGG_LVL_SET(x)			(FIELD_PREP(GENMASK(15, 0), x))
214 #define NF_DMA_PACKAGE_SIZE_SET(x)			(FIELD_PREP(GENMASK(31, 16), x))
215 #define NF_FIFO_TRIGG_LVL				(0)
216 
217 /* BCH correction strength */
218 #define NF_TDEF_CORR_STR				(0)
219 #define F_CSTAT_COMP					(15)
220 #define F_CSTAT_FAIL					(14)
221 #define HPNFC_STAT_INPR					(0)
222 #define HPNFC_STAT_FAIL					(2)
223 #define HPNFC_STAT_OK					(1)
224 #define NF_16_ENABLE					(1)
225 #define NF_16_DISABLE					(0)
226 
227 /*PIO Mode*/
228 #define NF_CMD4_BANK_SET(x)				(FIELD_PREP(GENMASK(31, 24), x))
229 #define PIO_CMD0_CT_POS					(0)
230 #define PIO_CMD0_CT_SET(x)                              (FIELD_PREP(GENMASK(15, 0), x))
231 #define PIO_CF_INT					(20)
232 #define PIO_CF_INT_SET					(FIELD_PREP(BIT(PIO_CF_INT), 1))
233 #define PIO_CF_DMA_MASTER				(21)
234 #define PIO_CF_DMA_MASTER_SET(x)			(FIELD_PREP(BIT(PIO_CF_DMA_MASTER), x))
235 
236 /* Phy registers*/
237 #define PHY_DQ_TIMING_REG_OFFSET			(0x00002000)
238 #define PHY_DQS_TIMING_REG_OFFSET			(0x00002004)
239 #define PHY_GATE_LPBK_OFFSET				(0x00002008)
240 #define PHY_DLL_MASTER_OFFSET				(0x0000200c)
241 #define PHY_CTRL_REG_OFFSET				(0x00002080)
242 #define PHY_TSEL_REG_OFFSET				(0x00002084)
243 
244 #define PHY_CTRL_REG_SDR				(0x00004040)
245 #define PHY_TSEL_REG_SDR				(0x00000000)
246 #define PHY_DQ_TIMING_REG_SDR				(0x00000002)
247 #define PHY_DQS_TIMING_REG_SDR				(0x00100004)
248 #define PHY_GATE_LPBK_CTRL_REG_SDR			(0x00D80000)
249 #define PHY_DLL_MASTER_CTRL_REG_SDR			(0x00800000)
250 #define PHY_DLL_SLAVE_CTRL_REG_SDR			(0x00000000)
251 
252 #define PHY_CTRL_REG_DDR				(0x00000000)
253 #define PHY_TSEL_REG_DDR				(0x00000000)
254 #define PHY_DQ_TIMING_REG_DDR				(0x00000002)
255 #define PHY_DQS_TIMING_REG_DDR				(0x00000004)
256 #define PHY_GATE_LPBK_CTRL_REG_DDR			(0x00380002)
257 #define PHY_DLL_MASTER_CTRL_REG_DDR			(0x001400fe)
258 #define PHY_DLL_SLAVE_CTRL_REG_DDR			(0x00003f3f)
259 
260 /*SDMA*/
261 #define GCMD_TWB_VALUE					BIT64(6)
262 #define GCMCD_ADDR_SEQ					(1)
263 #define GCMCD_DATA_SEQ					(2)
264 #define ERASE_ADDR_SIZE					(FIELD_PREP(GENMASK64(13, 11), 3ULL))
265 #define GEN_SECTOR_COUNT				(1ULL)
266 #define GEN_SECTOR_COUNT_SET				(FIELD_PREP(GENMASK64(39, 32),\
267 								GEN_SECTOR_COUNT))
268 #define GEN_SECTOR_SIZE					(0x100ULL)
269 #define GEN_LAST_SECTOR_SIZE_SET(x)                     (FIELD_PREP(GENMASK64(55, 40), x))
270 #define SDMA_TRIGG					(21ULL)
271 #define SDMA_SIZE_ADDR					(0x0440)
272 #define SDMA_TRD_NUM_ADDR				(0x0444)
273 #define SDMA_ADDR0_ADDR					(0x044c)
274 #define SDMA_ADDR1_ADDR					(0x0450)
275 #define PAGE_READ_CMD					(0x3ULL)
276 #define PAGE_WRITE_CMD					(0x4ULL)
277 #define PAGE_ERASE_CMD					(0x6ULL)
278 #define PAGE_CMOD_CMD					(0x00)
279 #define PAGE_MAX_SIZE					(4)
280 #define PAGE_MAX_BYTES(x)				(FIELD_PREP(GENMASK64(13, 11), x))
281 #define GEN_CF_INT					(20)
282 #define GEN_CF_INT_SET(x)				(FIELD_PREP(BIT(GEN_CF_INT), x))
283 #define GEN_CF_INT_ENABLE				(1)
284 #define GEN_ADDR_POS					(16)
285 #define GEN_DIR_SET(x)					(FIELD_PREP(BIT64(11), x))
286 #define GEN_SECTOR_SET(x)			        (FIELD_PREP(GENMASK64(31, 16), x))
287 #define PAGE_WRITE_10H_CMD				(FIELD_PREP(GENMASK64(23, 16), 0x10ULL))
288 #define GEN_ADDR_WRITE_DATA(x)                          (FIELD_PREP(GENMASK64(63, 32), x))
289 #define NUM_ONE						(1)
290 #define U32_MASK_VAL					(0xFFFFFFFF)
291 #define BIT16_CHECK                                     (16)
292 #define IDLE_TIME_OUT                                   (5000U)
293 #define ROW_VAL_SET(x, y, z)                            (FIELD_PREP(GENMASK(x, y), z))
294 #define SET_FEAT_ADDR(x)				(FIELD_PREP(GENMASK(7, 0), x))
295 #define THREAD_VAL(x)					(FIELD_PREP(GENMASK(2, 0), x))
296 #define INCR_CMD_TYPE(x)				(x++)
297 #define DECR_CNT_ONE(x)					(--x)
298 #define GET_INIT_SET_CHECK(x, y)			(FIELD_GET(BIT(y), x))
299 struct nf_ctrl_version {
300 	uint32_t ctrl_rev:8;
301 	uint32_t ctrl_fix:8;
302 	uint32_t hpnfc_magic_number:16;
303 };
304 
305 /* Cadence cdma command descriptor*/
306 struct cdns_cdma_command_descriptor {
307 	/* Next descriptor address*/
308 	uint64_t next_pointer;
309 	/* Flash address is a 32-bit address comprising of ROW ADDR. */
310 	uint32_t flash_pointer;
311 	uint16_t bank_number;
312 	uint16_t reserved_0;
313 	/*operation the controller needs to perform*/
314 	uint16_t command_type;
315 	uint16_t reserved_1;
316 	/* Flags for operation of this command. */
317 	uint16_t command_flags;
318 	uint16_t reserved_2;
319 	/* System/host memory address required for data DMA commands. */
320 	uint64_t memory_pointer;
321 	/* Status of operation. */
322 	uint64_t status;
323 	/* Address pointer to sync buffer location. */
324 	uint64_t sync_flag_pointer;
325 	/* Controls the buffer sync mechanism. */
326 	uint32_t sync_arguments;
327 	uint32_t reserved_4;
328 	/* Control data pointer. */
329 	uint64_t ctrl_data_ptr;
330 
331 } __aligned(64);
332 
333 /* Row Address */
334 union row_address {
335 	struct {
336 		uint32_t page_address:7;
337 		uint32_t block_address:10;
338 		uint32_t lun_address:3;
339 	} row_bit_reg;
340 
341 	uint32_t row_address_raw;
342 };
343 
344 /* device info structure */
345 struct cadence_nand_params {
346 	uintptr_t nand_base;
347 	uintptr_t sdma_base;
348 	uint8_t datarate_mode;
349 	uint8_t nluns;
350 	uint16_t page_size;
351 	uint16_t spare_size;
352 	uint16_t npages_per_block;
353 	uint32_t nblocks_per_lun;
354 	uint32_t block_size;
355 	uint8_t total_bit_row;
356 	uint8_t page_size_bit;
357 	uint8_t block_size_bit;
358 	uint8_t lun_size_bit;
359 	size_t page_count;
360 	unsigned long long device_size;
361 #ifdef CONFIG_CDNS_NAND_INTERRUPT_SUPPORT
362 	struct k_sem interrupt_sem_t;
363 #endif
364 } __aligned(32);
365 
366 /* Global function Api */
367 int cdns_nand_init(struct cadence_nand_params *params);
368 int cdns_nand_read(struct cadence_nand_params *params, const void *buffer, uint32_t offset,
369 										uint32_t size);
370 int cdns_nand_write(struct cadence_nand_params *params, const void *buffer, uint32_t offset,
371 										uint32_t len);
372 int cdns_nand_erase(struct cadence_nand_params *params, uint32_t offset, uint32_t size);
373 #if CONFIG_CDNS_NAND_INTERRUPT_SUPPORT
374 void cdns_nand_irq_handler_ll(struct cadence_nand_params *params);
375 #endif
376 
377 #endif
378