1 /*
2 * Copyright (c) 2023 Andes Technology Corporation.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #define DT_DRV_COMPAT andestech_qspi_nor
8
9 #include <errno.h>
10 #include <zephyr/kernel.h>
11 #include <zephyr/device.h>
12 #include <zephyr/drivers/flash.h>
13 #include <zephyr/init.h>
14 #include <string.h>
15 #include <zephyr/logging/log.h>
16
17 #include "flash_andes_qspi.h"
18 #include "spi_nor.h"
19 #include "jesd216.h"
20 #include "flash_priv.h"
21
22 LOG_MODULE_REGISTER(flash_andes, CONFIG_FLASH_LOG_LEVEL);
23
24 /* Indicates that an access command includes bytes for the address.
25 * If not provided the opcode is not followed by address bytes.
26 */
27 #define ANDES_ACCESS_ADDRESSED BIT(0)
28
29 /* Indicates that an access command is performing a write. If not
30 * provided access is a read.
31 */
32 #define ANDES_ACCESS_WRITE BIT(7)
33
34 #define flash_andes_qspi_cmd_read(dev, opcode, dest, length) \
35 flash_andes_qspi_access(dev, opcode, 0, 0, dest, length)
36 #define flash_andes_qspi_cmd_addr_read(dev, opcode, addr, dest, length) \
37 flash_andes_qspi_access(dev, opcode, ANDES_ACCESS_ADDRESSED, addr, \
38 dest, length)
39 #define flash_andes_qspi_cmd_write(dev, opcode) \
40 flash_andes_qspi_access(dev, opcode, ANDES_ACCESS_WRITE, 0, NULL, 0)
41 #define flash_andes_qspi_cmd_addr_write(dev, opcode, addr, src, length) \
42 flash_andes_qspi_access(dev, opcode, \
43 ANDES_ACCESS_WRITE | ANDES_ACCESS_ADDRESSED, \
44 addr, (void *)src, length)
45
46
47 typedef void (*flash_andes_qspi_config_func_t)(void);
48 struct flash_andes_qspi_config {
49 flash_andes_qspi_config_func_t cfg_func;
50 uint32_t base;
51 uint32_t irq_num;
52 struct flash_parameters parameters;
53 bool xip;
54 #if defined(CONFIG_FLASH_ANDES_QSPI_SFDP_DEVICETREE)
55 uint8_t jedec_id[SPI_NOR_MAX_ID_LEN];
56 uint32_t flash_size;
57 uint8_t bfp_len;
58 const struct jesd216_bfp *bfp;
59 #ifdef CONFIG_FLASH_PAGE_LAYOUT
60 struct flash_pages_layout layout;
61 #endif /* CONFIG_FLASH_PAGE_LAYOUT */
62 #endif /* CONFIG_FLASH_ANDES_QSPI_SFDP_DEVICETREE */
63 };
64
65 struct flash_andes_qspi_data {
66 struct k_sem sem;
67 struct k_sem device_sync_sem;
68 uint32_t tx_fifo_size;
69 uint32_t rx_fifo_size;
70 uint8_t *tx_buf;
71 uint8_t *rx_buf;
72 uint32_t tx_len;
73 uint32_t rx_len;
74 uint32_t tx_ptr; /* write pointer */
75 uint32_t rx_ptr; /* read pointer */
76 struct jesd216_erase_type erase_types[JESD216_NUM_ERASE_TYPES];
77 uint16_t page_size;
78 #ifdef CONFIG_FLASH_ANDES_QSPI_SFDP_RUNTIME
79 uint32_t flash_size;
80 #ifdef CONFIG_FLASH_PAGE_LAYOUT
81 struct flash_pages_layout layout;
82 #endif /* CONFIG_FLASH_PAGE_LAYOUT */
83 #endif
84 };
85
86 static int flash_andes_qspi_write_protection_set(const struct device *dev,
87 bool write_protect);
88
89 /* Get pointer to array of supported erase types. */
90 static inline const struct jesd216_erase_type *
dev_erase_types(const struct device * dev)91 dev_erase_types(const struct device *dev)
92 {
93 const struct flash_andes_qspi_data *dev_data = dev->data;
94
95 return dev_data->erase_types;
96 }
97
98 /* Get the size of the flash device. */
dev_flash_size(const struct device * dev)99 static inline uint32_t dev_flash_size(const struct device *dev)
100 {
101 #ifdef CONFIG_FLASH_ANDES_QSPI_SFDP_RUNTIME
102 const struct flash_andes_qspi_data *dev_data = dev->data;
103
104 return dev_data->flash_size;
105 #else /* CONFIG_FLASH_ANDES_QSPI_SFDP_RUNTIME */
106 const struct flash_andes_qspi_config *config = dev->config;
107
108 return config->flash_size;
109 #endif /* CONFIG_FLASH_ANDES_QSPI_SFDP_RUNTIME */
110 }
111
112 /* Get the flash device page size. */
dev_page_size(const struct device * dev)113 static inline uint16_t dev_page_size(const struct device *dev)
114 {
115 const struct flash_andes_qspi_data *dev_data = dev->data;
116
117 return dev_data->page_size;
118 }
119
120 /*
121 * @brief Send an SPI command
122 *
123 * @param dev Device struct
124 * @param opcode The command to send
125 * @param access flags that determine how the command is constructed.
126 * @param addr The address to send
127 * @param data The buffer to store or read the value
128 * @param length The size of the buffer
129 * @return 0 on success
130 */
flash_andes_qspi_access(const struct device * const dev,uint8_t opcode,uint8_t access,off_t addr,void * data,size_t length)131 static int flash_andes_qspi_access(const struct device *const dev,
132 uint8_t opcode, uint8_t access, off_t addr,
133 void *data, size_t length)
134 {
135 struct flash_andes_qspi_data *dev_data = dev->data;
136 const struct flash_andes_qspi_config *config = dev->config;
137 uint32_t base = config->base;
138
139 bool is_addressed = (access & ANDES_ACCESS_ADDRESSED) != 0U;
140 bool is_write = (access & ANDES_ACCESS_WRITE) != 0U;
141 int ret = 0;
142
143 uint32_t tctrl, int_msk;
144
145 /* Command phase enable */
146 tctrl = TCTRL_CMD_EN_MSK;
147 if (is_addressed) {
148 /* Enable and set ADDR len */
149 sys_write32((sys_read32(QSPI_TFMAT(base)) |
150 (0x2 << TFMAT_ADDR_LEN_OFFSET)), QSPI_TFMAT(base));
151 sys_write32(addr, QSPI_ADDR(base));
152 /* Address phase enable */
153 tctrl |= TCTRL_ADDR_EN_MSK;
154 }
155
156 if (length == 0) {
157 if ((opcode == FLASH_ANDES_CMD_4PP) ||
158 (opcode == FLASH_ANDES_CMD_4READ)) {
159 goto exit;
160 }
161 tctrl |= TRNS_MODE_NONE_DATA;
162 int_msk = IEN_END_MSK;
163 } else if (is_write) {
164 dev_data->tx_ptr = 0;
165 dev_data->tx_buf = (uint8_t *)data;
166 dev_data->tx_len = length;
167
168 tctrl |= (TRNS_MODE_WRITE_ONLY |
169 ((length - 1) << TCTRL_WR_TCNT_OFFSET));
170 int_msk = IEN_TX_FIFO_MSK | IEN_END_MSK;
171 } else {
172 dev_data->rx_ptr = 0;
173 dev_data->rx_buf = (uint8_t *)data;
174
175 tctrl |= (TRNS_MODE_READ_ONLY |
176 ((length - 1) << TCTRL_RD_TCNT_OFFSET));
177 int_msk = IEN_RX_FIFO_MSK | IEN_END_MSK;
178 }
179
180 switch (opcode) {
181 case FLASH_ANDES_CMD_4PP:
182 tctrl = ((tctrl & ~TCTRL_TRNS_MODE_MSK) |
183 DUAL_IO_MODE |
184 TCTRL_ADDR_FMT_MSK |
185 TCTRL_ADDR_EN_MSK |
186 TRNS_MODE_WRITE_ONLY);
187 break;
188 case FLASH_ANDES_CMD_4READ:
189 tctrl = ((tctrl & ~TCTRL_TRNS_MODE_MSK) |
190 DUAL_IO_MODE |
191 TCTRL_ADDR_FMT_MSK |
192 TCTRL_ADDR_EN_MSK |
193 TRNS_MODE_DUMMY_READ |
194 DUMMY_CNT_3);
195 break;
196 case JESD216_CMD_READ_SFDP:
197 tctrl = ((tctrl & ~TCTRL_TRNS_MODE_MSK) |
198 TCTRL_ADDR_EN_MSK |
199 TRNS_MODE_DUMMY_READ);
200 break;
201 default:
202 break;
203 }
204
205 sys_write32(tctrl, QSPI_TCTRL(base));
206 /* Enable TX/RX FIFO interrupts */
207 sys_write32(int_msk, QSPI_INTEN(base));
208 /* write CMD register to send command*/
209 sys_write32(opcode, QSPI_CMD(base));
210 k_sem_take(&dev_data->device_sync_sem, K_FOREVER);
211 exit:
212 return ret;
213 }
214
215 /* Everything necessary to acquire owning access to the device. */
acquire_device(const struct device * dev)216 static void acquire_device(const struct device *dev)
217 {
218 struct flash_andes_qspi_data *dev_data = dev->data;
219
220 k_sem_take(&dev_data->sem, K_FOREVER);
221 }
222
223 /* Everything necessary to release access to the device. */
release_device(const struct device * dev)224 static void release_device(const struct device *dev)
225 {
226 struct flash_andes_qspi_data *dev_data = dev->data;
227
228 k_sem_give(&dev_data->sem);
229 }
230
231 /**
232 * @brief Wait until the flash is ready
233 *
234 * @param dev The device structure
235 * @return 0 on success, negative errno code otherwise
236 */
flash_andes_qspi_wait_until_ready(const struct device * dev)237 static int flash_andes_qspi_wait_until_ready(const struct device *dev)
238 {
239 int ret;
240 uint8_t reg;
241
242 do {
243 ret = flash_andes_qspi_cmd_read(dev,
244 FLASH_ANDES_CMD_RDSR, ®, 1);
245 } while (!ret && (reg & FLASH_ANDES_WIP_BIT));
246
247 return ret;
248 }
249
250 #if defined(CONFIG_FLASH_ANDES_QSPI_SFDP_RUNTIME) || \
251 defined(CONFIG_FLASH_JESD216_API)
252 /*
253 * @brief Read content from the SFDP hierarchy
254 *
255 * @note The device must be externally acquired before invoking this
256 * function.
257 *
258 * @param dev Device struct
259 * @param addr The address to send
260 * @param data The buffer to store or read the value
261 * @param length The size of the buffer
262 * @return 0 on success, negative errno code otherwise
263 */
read_sfdp(const struct device * const dev,off_t addr,void * data,size_t length)264 static int read_sfdp(const struct device *const dev,
265 off_t addr, void *data, size_t length)
266 {
267 /* READ_SFDP requires a 24-bit address followed by a single
268 * byte for a wait state. This is effected by using 32-bit
269 * address by shifting the 24-bit address up 8 bits.
270 */
271 return flash_andes_qspi_access(dev, JESD216_CMD_READ_SFDP,
272 ANDES_ACCESS_ADDRESSED,
273 addr, data, length);
274 }
275 #endif /* CONFIG_FLASH_ANDES_QSPI_SFDP_RUNTIME */
276
277 /**
278 * @brief Write the status register.
279 *
280 * @note The device must be externally acquired before invoking this
281 * function.
282 *
283 * @param dev Device struct
284 * @param sr The new value of the status register
285 *
286 * @return 0 on success or a negative error code.
287 */
flash_andes_qspi_wrsr(const struct device * dev,uint8_t sr)288 static int flash_andes_qspi_wrsr(const struct device *dev,
289 uint8_t sr)
290 {
291 int ret = flash_andes_qspi_cmd_write(dev, FLASH_ANDES_CMD_WREN);
292
293 if (ret == 0) {
294 ret = flash_andes_qspi_access(dev, FLASH_ANDES_CMD_WRSR,
295 ANDES_ACCESS_WRITE, 0, &sr,
296 sizeof(sr));
297 flash_andes_qspi_wait_until_ready(dev);
298 }
299
300 return ret;
301 }
302
flash_andes_qspi_read(const struct device * dev,off_t addr,void * dest,size_t size)303 static int flash_andes_qspi_read(const struct device *dev,
304 off_t addr, void *dest, size_t size)
305 {
306 const size_t flash_size = dev_flash_size(dev);
307 int ret;
308
309 /* should be between 0 and flash size */
310 if ((addr < 0 || addr >= flash_size || ((flash_size - addr) < size))) {
311 return -EINVAL;
312 }
313
314 if (size == 0) {
315 return 0;
316 }
317
318 acquire_device(dev);
319
320 ret = flash_andes_qspi_cmd_addr_read(dev,
321 FLASH_ANDES_CMD_4READ, addr, dest, size);
322
323 release_device(dev);
324 return ret;
325 }
326
flash_andes_qspi_write(const struct device * dev,off_t addr,const void * src,size_t size)327 static int flash_andes_qspi_write(const struct device *dev, off_t addr,
328 const void *src, size_t size)
329 {
330 const size_t flash_size = dev_flash_size(dev);
331 const uint16_t page_size = dev_page_size(dev);
332 size_t to_write = size;
333 int ret = 0;
334
335 /* should be between 0 and flash size */
336 if ((addr < 0 || addr >= flash_size || ((flash_size - addr) < size))) {
337 return -EINVAL;
338 }
339
340 if (size == 0) {
341 return 0;
342 }
343
344 acquire_device(dev);
345
346 ret = flash_andes_qspi_write_protection_set(dev, false);
347
348 if (ret != 0) {
349 goto out;
350 }
351
352 do {
353 /* Get the adequate size to send*/
354 to_write = MIN(page_size - (addr % page_size), size);
355
356 ret = flash_andes_qspi_cmd_addr_write(dev,
357 FLASH_ANDES_CMD_4PP, addr, src, to_write);
358
359 if (ret != 0) {
360 break;
361 }
362
363 size -= to_write;
364 src = (const uint8_t *)src + to_write;
365 addr += to_write;
366
367 flash_andes_qspi_wait_until_ready(dev);
368 } while (size > 0);
369
370
371 int ret2 = flash_andes_qspi_write_protection_set(dev, true);
372
373 if (!ret) {
374 ret = ret2;
375 }
376
377 out:
378 release_device(dev);
379 return ret;
380 }
381
flash_andes_qspi_erase(const struct device * dev,off_t addr,size_t size)382 static int flash_andes_qspi_erase(const struct device *dev,
383 off_t addr, size_t size)
384 {
385 const size_t flash_size = dev_flash_size(dev);
386 int ret = 0;
387
388 /* erase area must be subregion of device */
389 if ((addr < 0 || addr >= flash_size || ((flash_size - addr) < size))) {
390 return -EINVAL;
391 }
392
393 if (size == 0) {
394 return 0;
395 }
396
397 /* address must be sector-aligned */
398 if (!SPI_NOR_IS_SECTOR_ALIGNED(addr)) {
399 return -EINVAL;
400 }
401
402 /* size must be a multiple of sectors */
403 if ((size % SPI_NOR_SECTOR_SIZE) != 0) {
404 return -EINVAL;
405 }
406
407 acquire_device(dev);
408
409 ret = flash_andes_qspi_write_protection_set(dev, false);
410
411 if (ret != 0) {
412 goto out;
413 }
414
415 if (size == flash_size) {
416 /* chip erase */
417 flash_andes_qspi_cmd_write(dev, FLASH_ANDES_CMD_CE);
418 size -= flash_size;
419 flash_andes_qspi_wait_until_ready(dev);
420 }
421
422 while (size > 0) {
423 const struct jesd216_erase_type *erase_types =
424 dev_erase_types(dev);
425 const struct jesd216_erase_type *bet = NULL;
426
427 for (uint8_t ei = 0; ei < JESD216_NUM_ERASE_TYPES; ++ei) {
428 const struct jesd216_erase_type *etp =
429 &erase_types[ei];
430
431 if ((etp->exp != 0) &&
432 SPI_NOR_IS_ALIGNED(addr, etp->exp) &&
433 SPI_NOR_IS_ALIGNED(size, etp->exp) &&
434 ((bet == NULL) || (etp->exp > bet->exp))) {
435 bet = etp;
436 }
437 }
438
439 if (bet != NULL) {
440 flash_andes_qspi_cmd_addr_write(dev, bet->cmd,
441 addr, NULL, 0);
442 addr += BIT(bet->exp);
443 size -= BIT(bet->exp);
444 } else {
445 LOG_DBG("Can't erase %zu at 0x%lx",
446 size, (long)addr);
447 ret = -EINVAL;
448 break;
449 }
450
451 flash_andes_qspi_wait_until_ready(dev);
452 }
453
454 int ret2 = flash_andes_qspi_write_protection_set(dev, true);
455
456 if (!ret) {
457 ret = ret2;
458 }
459
460 out:
461 release_device(dev);
462
463 return ret;
464 }
465
flash_andes_qspi_write_protection_set(const struct device * dev,bool write_protect)466 static int flash_andes_qspi_write_protection_set(const struct device *dev,
467 bool write_protect)
468 {
469 return flash_andes_qspi_cmd_write(dev, (write_protect) ?
470 FLASH_ANDES_CMD_WRDI : FLASH_ANDES_CMD_WREN);
471 }
472
473 #if defined(CONFIG_FLASH_JESD216_API)
474
flash_andes_qspi_sfdp_read(const struct device * dev,off_t addr,void * dest,size_t size)475 static int flash_andes_qspi_sfdp_read(const struct device *dev, off_t addr,
476 void *dest, size_t size)
477 {
478 acquire_device(dev);
479
480 int ret = read_sfdp(dev, addr, dest, size);
481
482 release_device(dev);
483
484 return ret;
485 }
486
487 #endif /* CONFIG_FLASH_JESD216_API */
488
flash_andes_qspi_read_jedec_id(const struct device * dev,uint8_t * id)489 static int flash_andes_qspi_read_jedec_id(const struct device *dev,
490 uint8_t *id)
491 {
492 if (id == NULL) {
493 return -EINVAL;
494 }
495
496 acquire_device(dev);
497
498 int ret = flash_andes_qspi_cmd_read(dev, FLASH_ANDES_CMD_RDID, id, 3);
499
500 release_device(dev);
501
502 return ret;
503 }
504
spi_nor_process_bfp(const struct device * dev,const struct jesd216_param_header * php,const struct jesd216_bfp * bfp)505 static int spi_nor_process_bfp(const struct device *dev,
506 const struct jesd216_param_header *php,
507 const struct jesd216_bfp *bfp)
508 {
509 struct flash_andes_qspi_data *dev_data = dev->data;
510 struct jesd216_erase_type *etp = dev_data->erase_types;
511 const size_t flash_size = jesd216_bfp_density(bfp) / 8U;
512
513 LOG_DBG("%s: %u MiBy flash", dev->name, (uint32_t)(flash_size >> 20));
514
515 /* Copy over the erase types, preserving their order. (The
516 * Sector Map Parameter table references them by index.)
517 */
518 memset(dev_data->erase_types, 0, sizeof(dev_data->erase_types));
519 for (uint8_t ti = 1; ti <= ARRAY_SIZE(dev_data->erase_types); ++ti) {
520 if (jesd216_bfp_erase(bfp, ti, etp) == 0) {
521 LOG_DBG("Erase %u with %02x",
522 (uint32_t)BIT(etp->exp), etp->cmd);
523 }
524 ++etp;
525 }
526
527 dev_data->page_size = jesd216_bfp_page_size(php, bfp);
528 #ifdef CONFIG_FLASH_ANDES_QSPI_SFDP_RUNTIME
529 dev_data->flash_size = flash_size;
530 #else /* CONFIG_FLASH_ANDES_QSPI_SFDP_RUNTIME */
531 if (flash_size != dev_flash_size(dev)) {
532 LOG_ERR("BFP flash size mismatch with devicetree");
533 return -EINVAL;
534 }
535 #endif /* CONFIG_FLASH_ANDES_QSPI_SFDP_RUNTIME */
536
537 return 0;
538 }
539
spi_nor_process_sfdp(const struct device * dev)540 static int spi_nor_process_sfdp(const struct device *dev)
541 {
542 int ret;
543
544 #if defined(CONFIG_FLASH_ANDES_QSPI_SFDP_RUNTIME)
545
546 const uint8_t decl_nph = 2;
547 union {
548 /* We only process BFP so use one parameter block */
549 uint8_t raw[JESD216_SFDP_SIZE(decl_nph)];
550 struct jesd216_sfdp_header sfdp;
551 } u;
552 const struct jesd216_sfdp_header *hp = &u.sfdp;
553
554 ret = read_sfdp(dev, 0, u.raw, sizeof(u.raw));
555 if (ret != 0) {
556 LOG_ERR("SFDP read failed: %d", ret);
557 return ret;
558 }
559
560 uint32_t magic = jesd216_sfdp_magic(hp);
561
562 if (magic != JESD216_SFDP_MAGIC) {
563 LOG_ERR("SFDP magic %08x invalid", magic);
564 return -EINVAL;
565 }
566
567 LOG_DBG("%s: SFDP v %u.%u AP %x with %u PH", dev->name,
568 hp->rev_major, hp->rev_minor, hp->access, 1 + hp->nph);
569
570 const struct jesd216_param_header *php = hp->phdr;
571 const struct jesd216_param_header *phpe =
572 php + MIN(decl_nph, 1 + hp->nph);
573
574 while (php != phpe) {
575 uint16_t id = jesd216_param_id(php);
576
577 LOG_DBG("PH%zu: %04x rev %u.%u: %u DW @ %x",
578 (php - hp->phdr), id, php->rev_major, php->rev_minor,
579 php->len_dw, jesd216_param_addr(php));
580
581 if (id == JESD216_SFDP_PARAM_ID_BFP) {
582 union {
583 uint32_t dw[MIN(php->len_dw, 20)];
584 struct jesd216_bfp bfp;
585 } u;
586 const struct jesd216_bfp *bfp = &u.bfp;
587
588 ret = read_sfdp(dev,
589 jesd216_param_addr(php), u.dw, sizeof(u.dw));
590
591 if (ret != 0) {
592 break;
593 }
594
595 ret = spi_nor_process_bfp(dev, php, bfp);
596
597 if (ret != 0) {
598 break;
599 }
600 }
601 ++php;
602 }
603 #elif defined(CONFIG_FLASH_ANDES_QSPI_SFDP_DEVICETREE)
604 /* For devicetree we need to synthesize a parameter header and
605 * process the stored BFP data as if we had read it.
606 */
607 const struct flash_andes_qspi_config *config = dev->config;
608 struct jesd216_param_header bfp_hdr = {
609 .len_dw = config->bfp_len,
610 };
611
612 ret = spi_nor_process_bfp(dev, &bfp_hdr, cfg->bfp);
613 #else
614 #error Unhandled SFDP choice
615 #endif
616 return ret;
617 }
618
619 #if defined(CONFIG_FLASH_PAGE_LAYOUT)
setup_pages_layout(const struct device * dev)620 static int setup_pages_layout(const struct device *dev)
621 {
622 int ret = 0;
623
624 #if defined(CONFIG_FLASH_ANDES_QSPI_SFDP_RUNTIME)
625
626 struct flash_andes_qspi_data *dev_data = dev->data;
627 const size_t flash_size = dev_flash_size(dev);
628 const uint32_t layout_page_size =
629 CONFIG_FLASH_ANDES_QSPI_LAYOUT_PAGE_SIZE;
630 uint8_t exponent = 0;
631
632 /* Find the smallest erase size. */
633 for (size_t i = 0; i < ARRAY_SIZE(dev_data->erase_types); ++i) {
634 const struct jesd216_erase_type *etp =
635 &dev_data->erase_types[i];
636
637 if ((etp->cmd != 0) &&
638 ((exponent == 0) || (etp->exp < exponent))) {
639 exponent = etp->exp;
640 }
641 }
642
643 if (exponent == 0) {
644 return -ENOTSUP;
645 }
646
647 uint32_t erase_size = BIT(exponent);
648
649 /* Error if layout page size is not a multiple of smallest
650 * erase size.
651 */
652 if ((layout_page_size % erase_size) != 0) {
653 LOG_ERR("layout page %u not compatible with erase size %u",
654 layout_page_size, erase_size);
655 return -EINVAL;
656 }
657
658 /* Warn but accept layout page sizes that leave inaccessible
659 * space.
660 */
661 if ((flash_size % layout_page_size) != 0) {
662 LOG_WRN("layout page %u wastes space with device size %zu",
663 layout_page_size, flash_size);
664 }
665
666 dev_data->layout.pages_size = layout_page_size;
667 dev_data->layout.pages_count = flash_size / layout_page_size;
668 LOG_DBG("layout %zu x %zu By pages", dev_data->layout.pages_count,
669 dev_data->layout.pages_size);
670
671 #elif defined(CONFIG_FLASH_ANDES_QSPI_SFDP_DEVICETREE)
672 const struct flash_andes_qspi_config *config = dev->config;
673 const struct flash_pages_layout *layout = &config->layout;
674 const size_t flash_size = dev_flash_size(dev);
675 size_t layout_size = layout->pages_size * layout->pages_count;
676
677 if (!SPI_NOR_IS_SECTOR_ALIGNED(layout->pages_size)) {
678 LOG_ERR("ANDES_QSPI_FLASH_LAYOUT_PAGE_SIZE must be "
679 "multiple of 4096");
680 return -EINVAL;
681 }
682
683 if (flash_size != layout_size) {
684 LOG_ERR("device size %zu mismatch %zu * %zu By pages",
685 flash_size, layout->pages_count, layout->pages_size);
686 return -EINVAL;
687 }
688 #else /* CONFIG_FLASH_ANDES_QSPI_SFDP_RUNTIME */
689 #error Unhandled SFDP choice
690 #endif /* CONFIG_FLASH_ANDES_QSPI_SFDP_RUNTIME */
691 return ret;
692 }
693 #endif /* CONFIG_FLASH_PAGE_LAYOUT */
694
qspi_andes_configure(const struct device * dev)695 static int qspi_andes_configure(const struct device *dev)
696 {
697 const struct flash_andes_qspi_config *config = dev->config;
698 uint32_t base = config->base;
699
700 /* Setting the divisor value to 0xff indicates the SCLK
701 * frequency should be the same as the spi_clock frequency.
702 */
703 sys_set_bits(QSPI_TIMIN(base), TIMIN_SCLK_DIV_MSK);
704
705 /* Set Master mode */
706 sys_clear_bits(QSPI_TFMAT(base), TFMAT_SLVMODE_MSK);
707
708 /* Disable data merge mode */
709 sys_clear_bits(QSPI_TFMAT(base), TFMAT_DATA_MERGE_MSK);
710
711 /* Set data length */
712 sys_clear_bits(QSPI_TFMAT(base), TFMAT_DATA_LEN_MSK);
713 sys_set_bits(QSPI_TFMAT(base), (7 << TFMAT_DATA_LEN_OFFSET));
714
715 /* Set TX/RX FIFO threshold */
716 sys_clear_bits(QSPI_CTRL(base), CTRL_TX_THRES_MSK);
717 sys_clear_bits(QSPI_CTRL(base), CTRL_RX_THRES_MSK);
718
719 sys_set_bits(QSPI_CTRL(base), TX_FIFO_THRESHOLD);
720 sys_set_bits(QSPI_CTRL(base), RX_FIFO_THRESHOLD);
721
722 return 0;
723 }
724
qspi_andes_irq_handler(const struct device * dev)725 static void qspi_andes_irq_handler(const struct device *dev)
726 {
727 struct flash_andes_qspi_data *data = dev->data;
728 const struct flash_andes_qspi_config *config = dev->config;
729 uint32_t base = config->base;
730
731 uint32_t i, intr_status, spi_status;
732 uint32_t rx_data, cur_tx_fifo_num, cur_rx_fifo_num;
733 uint32_t tx_num = 0, tx_data = 0;
734
735 intr_status = sys_read32(QSPI_INTST(base));
736
737 if ((intr_status & INTST_TX_FIFO_INT_MSK) &&
738 !(intr_status & INTST_END_INT_MSK)) {
739
740 spi_status = sys_read32(QSPI_STAT(base));
741 cur_tx_fifo_num = GET_TX_NUM(base);
742
743 tx_num = data->tx_fifo_size - cur_tx_fifo_num;
744
745 if (tx_num > data->tx_len) {
746 tx_num = data->tx_len;
747 }
748
749 for (i = tx_num; i > 0; i--) {
750 tx_data = data->tx_buf[data->tx_ptr];
751 sys_write32(tx_data, QSPI_DATA(base));
752 data->tx_ptr++;
753 if (data->tx_ptr == data->tx_len) {
754 sys_clear_bits(QSPI_INTEN(base), IEN_TX_FIFO_MSK);
755 break;
756 }
757 }
758 sys_write32(INTST_TX_FIFO_INT_MSK, QSPI_INTST(base));
759 }
760
761 if (intr_status & INTST_RX_FIFO_INT_MSK) {
762 cur_rx_fifo_num = GET_RX_NUM(base);
763
764 for (i = cur_rx_fifo_num; i > 0; i--) {
765 rx_data = sys_read32(QSPI_DATA(base));
766 data->rx_buf[data->rx_ptr] = rx_data;
767 data->rx_ptr++;
768 if (data->rx_ptr == data->rx_len) {
769 sys_clear_bits(QSPI_INTEN(base), IEN_RX_FIFO_MSK);
770 break;
771 }
772 }
773 sys_write32(INTST_RX_FIFO_INT_MSK, QSPI_INTST(base));
774 }
775
776 if (intr_status & INTST_END_INT_MSK) {
777
778 /* Clear end interrupt */
779 sys_write32(INTST_END_INT_MSK, QSPI_INTST(base));
780
781 /* Disable all SPI interrupts */
782 sys_write32(0, QSPI_INTEN(base));
783
784 k_sem_give(&data->device_sync_sem);
785 }
786 }
787
788 /**
789 * @brief Initialize and configure the flash
790 *
791 * @param name The flash name
792 * @return 0 on success, negative errno code otherwise
793 */
flash_andes_qspi_init(const struct device * dev)794 static int flash_andes_qspi_init(const struct device *dev)
795 {
796 const struct flash_andes_qspi_config *config = dev->config;
797 struct flash_andes_qspi_data *dev_data = dev->data;
798 uint32_t base = config->base;
799
800 uint8_t ret, reg = (0x1UL << 6);
801 uint8_t jedec_id[SPI_NOR_MAX_ID_LEN];
802
803 /* we should not configure the device we are running on */
804 if (config->xip) {
805 return -EINVAL;
806 }
807
808 k_sem_init(&dev_data->sem, 1, 1);
809 k_sem_init(&dev_data->device_sync_sem, 0, 1);
810
811 /* Get the TX/RX FIFO size of this device */
812 dev_data->tx_fifo_size = TX_FIFO_SIZE(base);
813 dev_data->rx_fifo_size = RX_FIFO_SIZE(base);
814
815 config->cfg_func();
816 irq_enable(config->irq_num);
817
818 qspi_andes_configure(dev);
819
820 ret = flash_andes_qspi_read_jedec_id(dev, jedec_id);
821 if (ret != 0) {
822 LOG_ERR("JEDEC ID read failed: %d", ret);
823 return -ENODEV;
824 }
825
826 #ifndef CONFIG_FLASH_ANDES_QSPI_SFDP_RUNTIME
827
828 if (memcmp(jedec_id, cfg->jedec_id, sizeof(jedec_id)) != 0) {
829 LOG_ERR("Device id %02x %02x %02x does not match config"
830 "%02x %02x %02x", jedec_id[0], jedec_id[1], jedec_id[2],
831 cfg->jedec_id[0], cfg->jedec_id[1], cfg->jedec_id[2]);
832 return -EINVAL;
833 }
834 #endif
835
836 ret = spi_nor_process_sfdp(dev);
837 if (ret != 0) {
838 LOG_ERR("SFDP read failed: %d", ret);
839 return -ENODEV;
840 }
841
842 #if defined(CONFIG_FLASH_PAGE_LAYOUT)
843 ret = setup_pages_layout(dev);
844 if (ret != 0) {
845 LOG_ERR("layout setup failed: %d", ret);
846 return -ENODEV;
847 }
848 #endif /* CONFIG_FLASH_PAGE_LAYOUT */
849
850 /* Set status register QE bit. */
851 flash_andes_qspi_wrsr(dev, reg);
852
853 return 0;
854 }
855
856 #if defined(CONFIG_FLASH_PAGE_LAYOUT)
flash_andes_qspi_pages_layout(const struct device * dev,const struct flash_pages_layout ** layout,size_t * layout_size)857 static void flash_andes_qspi_pages_layout(const struct device *dev,
858 const struct flash_pages_layout **layout,
859 size_t *layout_size)
860 {
861 #ifdef CONFIG_FLASH_ANDES_QSPI_SFDP_RUNTIME
862 const struct flash_andes_qspi_data *dev_data = dev->data;
863
864 *layout = &dev_data->layout;
865 #else /* CONFIG_FLASH_ANDES_QSPI_SFDP_RUNTIME */
866 const struct flash_andes_qspi_config *config = dev->config;
867
868 *layout = &config->layout;
869 #endif /* CONFIG_FLASH_ANDES_QSPI_SFDP_RUNTIME */
870 *layout_size = 1;
871 }
872 #endif
873
874
875 static const struct flash_parameters *
flash_andes_qspi_get_parameters(const struct device * dev)876 flash_andes_qspi_get_parameters(const struct device *dev)
877 {
878 const struct flash_andes_qspi_config *config = dev->config;
879
880 return &config->parameters;
881 }
882
883 static const struct flash_driver_api flash_andes_qspi_api = {
884 .read = flash_andes_qspi_read,
885 .write = flash_andes_qspi_write,
886 .erase = flash_andes_qspi_erase,
887 .get_parameters = flash_andes_qspi_get_parameters,
888 #if defined(CONFIG_FLASH_PAGE_LAYOUT)
889 .page_layout = flash_andes_qspi_pages_layout,
890 #endif
891 #if defined(CONFIG_FLASH_JESD216_API)
892 .sfdp_read = flash_andes_qspi_sfdp_read,
893 .read_jedec_id = flash_andes_qspi_read_jedec_id,
894 #endif
895 };
896
897 #if (CONFIG_XIP)
898 #define QSPI_ROM_CFG_XIP(node_id) DT_SAME_NODE(node_id, DT_CHOSEN(zephyr_flash))
899 #else
900 #define QSPI_ROM_CFG_XIP(node_id) false
901 #endif
902
903 #define LAYOUT_PAGES_PROP(n) \
904 IF_ENABLED(CONFIG_FLASH_PAGE_LAYOUT, \
905 (.layout = { \
906 .pages_count = ((DT_INST_PROP(n, size) / 8) / \
907 CONFIG_FLASH_ANDES_QSPI_LAYOUT_PAGE_SIZE), \
908 .pages_size = \
909 CONFIG_FLASH_ANDES_QSPI_LAYOUT_PAGE_SIZE, \
910 }, \
911 ))
912
913 #define ANDES_QSPI_SFDP_DEVICETREE_CONFIG(n) \
914 IF_ENABLED(CONFIG_FLASH_ANDES_QSPI_SFDP_DEVICETREE, \
915 ( \
916 static const __aligned(4) uint8_t bfp_data_##n[] = \
917 DT_INST_PROP(n, sfdp_bfp); \
918 ))
919
920 #define ANDES_QSPI_SFDP_DEVICETREE_PROP(n) \
921 IF_ENABLED(CONFIG_FLASH_ANDES_QSPI_SFDP_DEVICETREE, \
922 (.jedec_id = DT_INST_PROP(n, jedec_id), \
923 .flash_size = DT_INST_PROP(n, size) / 8, \
924 .bfp_len = sizeof(bfp_data_##n) / 4, \
925 .bfp = (const struct jesd216_bfp *)bfp_data_##n, \
926 LAYOUT_PAGES_PROP(n) \
927 ))
928
929 #define FLASH_ANDES_QSPI_INIT(n) \
930 static struct flash_andes_qspi_data flash_andes_qspi_data_##n; \
931 ANDES_QSPI_SFDP_DEVICETREE_CONFIG(n) \
932 \
933 static void flash_andes_qspi_configure_##n(void); \
934 static const struct flash_andes_qspi_config \
935 flash_andes_qspi_config_##n = { \
936 .cfg_func = flash_andes_qspi_configure_##n, \
937 .base = DT_REG_ADDR(DT_INST_BUS(n)), \
938 .irq_num = DT_IRQN(DT_INST_BUS(n)), \
939 .parameters = { \
940 .write_block_size = 1, \
941 .erase_value = 0xff \
942 }, \
943 .xip = QSPI_ROM_CFG_XIP(DT_DRV_INST(n)), \
944 ANDES_QSPI_SFDP_DEVICETREE_PROP(n) \
945 }; \
946 \
947 DEVICE_DT_INST_DEFINE(n, \
948 &flash_andes_qspi_init, \
949 NULL, \
950 &flash_andes_qspi_data_##n, \
951 &flash_andes_qspi_config_##n, \
952 POST_KERNEL, \
953 CONFIG_FLASH_ANDES_QSPI_INIT_PRIORITY, \
954 &flash_andes_qspi_api); \
955 \
956 static void flash_andes_qspi_configure_##n(void) \
957 { \
958 IRQ_CONNECT(DT_IRQN(DT_INST_BUS(n)), \
959 DT_IRQ(DT_INST_BUS(n), priority), \
960 qspi_andes_irq_handler, \
961 DEVICE_DT_INST_GET(n), \
962 0); \
963 } \
964
965 DT_INST_FOREACH_STATUS_OKAY(FLASH_ANDES_QSPI_INIT)
966
