1;/**************************************************************************//**
2; * @file     startup_cm0plus.s
3; * @brief    CMSIS Core Device Startup File for
4; *           ARMCM0plus Device
5; * @version  V1.0.1
6; * @date     23. July 2019
7; ******************************************************************************/
8;/*
9; * Copyright (c) 2009-2019 Arm Limited. All rights reserved.
10; *
11; * SPDX-License-Identifier: Apache-2.0
12; *
13; * Licensed under the Apache License, Version 2.0 (the License); you may
14; * not use this file except in compliance with the License.
15; * You may obtain a copy of the License at
16; *
17; * www.apache.org/licenses/LICENSE-2.0
18; *
19; * Unless required by applicable law or agreed to in writing, software
20; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
21; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
22; * See the License for the specific language governing permissions and
23; * limitations under the License.
24; */
25
26;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
27
28
29;<h> Stack Configuration
30;  <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
31;</h>
32
33CPUSS_RAM0_CTL0     EQU 0x40201300
34CPUSS_RAM1_CTL0     EQU 0x40201380
35CPUSS_RAM2_CTL0     EQU 0x402013a0
36
37
38
39                PRESERVE8
40                THUMB
41
42
43; Vector Table Mapped to Address 0 at Reset
44
45                AREA     RESET, DATA, READONLY
46                EXPORT   __Vectors
47                EXPORT   __Vectors_End
48                EXPORT   __Vectors_Size
49
50                IMPORT |Image$$ARM_LIB_STACK$$ZI$$Base|
51                IMPORT |Image$$ARM_LIB_STACK$$ZI$$Length|
52
53__Vectors       DCD      |Image$$ARM_LIB_STACK$$ZI$$Base| + |Image$$ARM_LIB_STACK$$ZI$$Length|         ;     Top of Stack
54                DCD      Reset_Handler                       ;     Reset Handler
55                DCD      NMI_Handler                         ; -14 NMI Handler
56                DCD      HardFault_Handler                   ; -13 Hard Fault Handler
57                DCD      0                                   ;     Reserved
58                DCD      0                                   ;     Reserved
59                DCD      0                                   ;     Reserved
60                DCD      0                                   ;     Reserved
61                DCD      0                                   ;     Reserved
62                DCD      0                                   ;     Reserved
63                DCD      0                                   ;     Reserved
64                DCD      SVC_Handler                         ;  -5 SVCall Handler
65                DCD      0                                   ;     Reserved
66                DCD      0                                   ;     Reserved
67                DCD      PendSV_Handler                      ;  -2 PendSV Handler
68                DCD      SysTick_Handler                     ;  -1 SysTick Handler
69
70                ; Interrupts
71                DCD     Default_Intr_Handler                   ; CPU User Interrupt #0
72                DCD     Default_Intr_Handler                   ; CPU User Interrupt #1
73                DCD     CM0P_CpuIntr2_Handler                   ; CPU User Interrupt #2
74                DCD     CM0P_CpuIntr3_Handler                   ; CPU User Interrupt #3
75                DCD     CM0P_CpuIntr4_Handler                   ; CPU User Interrupt #4
76                DCD     CM0P_CpuIntr5_Handler                   ; CPU User Interrupt #5
77                DCD     CM0P_CpuIntr6_Handler                   ; CPU User Interrupt #6
78                DCD     CM0P_CpuIntr7_Handler                   ; CPU User Interrupt #7
79                DCD     Default_Intr_Handler                  ; Internal SW Interrupt #0
80                DCD     Default_Intr_Handler                  ; Internal SW Interrupt #1
81                DCD     Default_Intr_Handler                  ; Internal SW Interrupt #2
82                DCD     Default_Intr_Handler                  ; Internal SW Interrupt #3
83                DCD     Default_Intr_Handler                  ; Internal SW Interrupt #4
84                DCD     Default_Intr_Handler                  ; Internal SW Interrupt #5
85                DCD     Default_Intr_Handler                  ; Internal SW Interrupt #6
86                DCD     Default_Intr_Handler                  ; Internal SW Interrupt #7
87
88__Vectors_End
89__Vectors_Size  EQU      __Vectors_End - __Vectors
90                EXPORT __ramVectors
91                AREA    RESET_RAM, READWRITE, NOINIT
92__ramVectors    SPACE   __Vectors_Size
93
94                AREA     |.text|, CODE, READONLY
95
96; Reset Handler
97
98Reset_Handler   PROC
99                EXPORT   Reset_Handler             [WEAK]
100                IMPORT   SystemInit
101                IMPORT   CyMain
102
103                ; Disable global interrupts
104                CPSID I
105
106                ; CM0+ bus width is 32-bit, but SRAM is built with 64-bit based ECC on Traveo II parts with CM7 core
107                ; Set CPUSS->RAMx_CTL0.ECC_CHECK_DIS bits to avoid causing unintentional ECC faults during startup while SRAM ECC has not been initialized yet
108                ; Generic code can be used, even if RAMx_CTL0 (x > 0) registers are not implemented in a device
109                ; or if no ECC_CHECK_DIS bits are available in the registers in case of m4cpuss with 32-bit ECC SRAM
110                MOVS r0, #1
111                LSLS r0, r0, #19
112                LDR  r1, =CPUSS_RAM0_CTL0
113                LDR  r2, [r1]
114                ORRS r2, r0
115                STR  r2, [r1]
116                LDR  r1, =CPUSS_RAM1_CTL0
117                LDR  r2, [r1]
118                ORRS r2, r0
119                STR  r2, [r1]
120                LDR  r1, =CPUSS_RAM2_CTL0
121                LDR  r2, [r1]
122                ORRS r2, r0
123                STR  r2, [r1]
124
125                ; Initialize ECC of startup stack (needed for local variables in C startup code) by processing 8 bytes per loop iteration,
126                ; because the ECC initialization feature uses this generic granularity that will cover any memory (SRAM/TCM) in any TVII device
127                ; Prerequisite: Stack Pointer (SP) has not been modified (from the vector table init value) by above code (otherwise code must be adapted)
128                LDR     r3, =|Image$$ARM_LIB_STACK$$ZI$$Base|
129                LDR     r1, =|Image$$ARM_LIB_STACK$$ZI$$Length|
130                ADD     r1, r1, r3 ; r1 = stack top
131                MOV     r0, r1
132                LDR     r3, =0x100
133                SUBS    r0, r0, r3 ; r0 = stack offset
134
135                MOVS    r2, #0  ; clear value
136                MOVS    r3, #0  ; clear value
137loopstackclean
138                STM     r0!, {r2, r3}
139                CMP     r0, r1
140                BNE     loopstackclean
141
142                LDR      R0, =SystemInit
143                BLX      R0
144                LDR      R0, =CyMain
145                BX       R0
146                ENDP
147
148Default_Handler     PROC
149                    EXPORT  Default_Handler                         [WEAK]
150                    EXPORT  CM0P_CpuIntr2_Handler                   [WEAK]
151                    EXPORT  CM0P_CpuIntr3_Handler                   [WEAK]
152                    EXPORT  CM0P_CpuIntr4_Handler                   [WEAK]
153                    EXPORT  CM0P_CpuIntr5_Handler                   [WEAK]
154                    EXPORT  CM0P_CpuIntr6_Handler                   [WEAK]
155                    EXPORT  CM0P_CpuIntr7_Handler                   [WEAK]
156
157CM0P_CpuIntr2_Handler
158CM0P_CpuIntr3_Handler
159CM0P_CpuIntr4_Handler
160CM0P_CpuIntr5_Handler
161CM0P_CpuIntr6_Handler
162CM0P_CpuIntr7_Handler
163                    B       .
164                    ENDP
165
166Cy_SysLib_FaultHandler PROC
167                    EXPORT  Cy_SysLib_FaultHandler    [WEAK]
168                    B       .
169                    ENDP
170
171; The default macro is not used for HardFault_Handler
172; because this results in a poor debug illusion.
173HardFault_Handler   PROC
174                    EXPORT HardFault_Handler          [WEAK]
175                    movs r0, #4
176                    mov r1, LR
177                    tst r0, r1
178                    beq L_MSP
179                    mrs r0, PSP
180                    bl L_API_call
181L_MSP
182                    mrs r0, MSP
183L_API_call
184                    bl Cy_SysLib_FaultHandler
185                    ENDP
186
187; Macro to define default exception/interrupt handlers.
188; Default handler are weak symbols with an endless loop.
189; They can be overwritten by real handlers.
190                MACRO
191                Set_Default_Handler  $Handler_Name
192$Handler_Name   PROC
193                EXPORT   $Handler_Name             [WEAK]
194                B        .
195                ENDP
196                MEND
197
198
199; Default exception/interrupt handler
200
201                Set_Default_Handler  NMI_Handler
202                Set_Default_Handler  SVC_Handler
203                Set_Default_Handler  PendSV_Handler
204                Set_Default_Handler  SysTick_Handler
205
206                Set_Default_Handler  Default_Intr_Handler
207
208
209                ALIGN
210
211
212                END
213
214