1/******************************************************************************* 2* \file cyw20829_ns_flash_cbus.icf 3* \version 1.1.0 4* 5* Linker file for the IAR compiler. 6* 7* The main purpose of the linker script is to describe how the sections in the 8* input files should be mapped into the output file, and to control the memory 9* layout of the output file. 10* 11* \note The entry point starts at 0x0401c600. The valid application 12* image should be placed there. 13* 14* \note The linker files included with the PDL template projects must be generic 15* and handle all common use cases. Your project may not use every section 16* defined in the linker files. In that case you may see warnings during the 17* build process. In your project, you can simply comment out or remove the 18* relevant code in the linker file. 19* 20******************************************************************************** 21* \copyright 22* Copyright (c) (2020-2022), Cypress Semiconductor Corporation (an Infineon company) or 23* an affiliate of Cypress Semiconductor Corporation. 24* SPDX-License-Identifier: Apache-2.0 25* 26* Licensed under the Apache License, Version 2.0 (the "License"); 27* you may not use this file except in compliance with the License. 28* You may obtain a copy of the License at 29* 30* http://www.apache.org/licenses/LICENSE-2.0 31* 32* Unless required by applicable law or agreed to in writing, software 33* distributed under the License is distributed on an "AS IS" BASIS, 34* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 35* See the License for the specific language governing permissions and 36* limitations under the License. 37*******************************************************************************/ 38 39 40/* The size of the stack section at the end of CM33 SRAM */ 41define symbol STACK_SIZE = 0x800; 42define symbol HEAP_SIZE = 0x0400; 43 44/* Memory reserved for Bootstrap code and data */ 45if (!isdefinedsymbol(APP_BOOTSTRAP_SIZE)) { 46 define symbol APP_BOOTSTRAP_SIZE = 0x00003A00; 47} 48 49if (!isdefinedsymbol(BOOTSTRAP_SIZE)) { 50 define symbol BOOTSTRAP_SIZE = APP_BOOTSTRAP_SIZE; 51} 52 53define symbol FLASH_START_ADDR_SAHB = 0x60000000; 54define symbol FLASH_START_ADDR_CBUS = 0x08000000; 55define symbol RAM_START_ADDR_SAHB = 0x20000000; 56define symbol RAM_START_ADDR_CBUS = 0x04000000; 57define symbol RAM_END_ADDR_SAHB = 0x20040000; /* 256K */ 58define symbol RAM_END_ADDR_CBUS = 0x04040000; /* 256K */ 59define symbol FLASH_END_ADDR_SAHB = 0x60080000; /* 512K */ 60 61define symbol BOOTSTRAP_OFFSET_FLASH = 0x00000050; /* toc2=0x10, l1_desc=0x1C, sign_header=0x20 */ 62define symbol RAMVECTORS_ALIGNMENT = 512; 63define symbol FLASH_ALIGNMENT_SIZE = 0x00000200; 64 65/* vma for bootstrap code region */ 66define symbol CODE_VMA = RAM_END_ADDR_SAHB - BOOTSTRAP_SIZE; /* 0x2003c600 */ 67/* lma for bootstrap code region */ 68define symbol CODE_LMA = FLASH_START_ADDR_SAHB + BOOTSTRAP_OFFSET_FLASH; /* 0x60000050 */ 69/* Size of Bootstrap data */ 70define symbol DATA_BS_SIZE = 0x00000400; /* 1KB */ 71/* Maximum bootstrap code + data size */ 72define symbol CODE_BS_SIZE = BOOTSTRAP_SIZE - DATA_BS_SIZE; /* 8KB */ 73/* vma for bootstrap data region */ 74define symbol DATA_BS_VMA = RAM_END_ADDR_SAHB - BOOTSTRAP_SIZE + CODE_BS_SIZE; /* 0x2001E000 */ 75/* vma for app data region */ 76define symbol DATA_VMA = RAM_START_ADDR_SAHB; /* 0x20000000 */ 77/* app data size */ 78define symbol DATA_SIZE = RAM_END_ADDR_SAHB - DATA_VMA - BOOTSTRAP_SIZE; /* 0x3DC00 */ 79/* vma for application XIP region */ 80define symbol XIP_VMA = FLASH_START_ADDR_SAHB + BOOTSTRAP_SIZE + FLASH_ALIGNMENT_SIZE; /* 0x08002600 */ 81/* lma for application XIP region */ 82define symbol XIP_LMA = FLASH_START_ADDR_SAHB + BOOTSTRAP_SIZE + FLASH_ALIGNMENT_SIZE; /* 0x60002600 */ 83/* size of XIP region */ 84define symbol XIP_SIZE = FLASH_END_ADDR_SAHB - XIP_LMA; 85/* Total size of SRAM */ 86define symbol RAM_SIZE = RAM_END_ADDR_SAHB - RAM_START_ADDR_SAHB; /* 0x00040000 */ 87 88/* The symbols below define the location and size of blocks of memory in the target. 89 * Use these symbols to specify the memory regions available for allocation. 90 */ 91 92/*-Sizes-*/ 93if (!isdefinedsymbol(__STACK_SIZE)) { 94 define symbol __size_cstack__ = STACK_SIZE; 95} else { 96 define symbol __size_cstack__ = __STACK_SIZE; 97} 98define symbol __size_proc_stack__ = 0x0; 99 100/* Defines the minimum heap size. The actual heap size will be expanded to the end of the stack region */ 101if (!isdefinedsymbol(__HEAP_SIZE)) { 102 define symbol __size_heap__ = HEAP_SIZE; 103} else { 104 define symbol __size_heap__ = __HEAP_SIZE; 105} 106 107define memory mem with size = 4G; 108/* bootstrap code region */ 109define region CODE_region = mem:[from CODE_VMA size CODE_BS_SIZE]; 110/* bootstrap data region */ 111define region DATA_BS_region = mem:[from DATA_BS_VMA size DATA_BS_SIZE]; 112/* app data region */ 113define region DATA_region = mem:[from DATA_VMA size DATA_SIZE]; 114/* app code (xip) region */ 115define region XIP_region = mem:[from XIP_VMA size XIP_SIZE]; 116 117 118define block CSTACK with alignment = 8, size = __size_cstack__ { }; 119define block PROC_STACK with alignment = 8, size = __size_proc_stack__ { }; 120define block HEAP with expanding size, alignment = 8, minimum size = __size_heap__ { }; 121define block HSTACK {first block CSTACK, block PROC_STACK}; 122define block RO {first section .intvec}; 123define block RAMVECTOR with alignment = RAMVECTORS_ALIGNMENT { section .intvec_ram}; 124define block APPTEXTRAM with alignment = 8 125{ 126 section .cy_ramfunc, 127 readwrite code object cy_smif.o, 128 readwrite code object cy_smif_sfdp.o, 129 readwrite code object cy_smif_memslot.o, 130 readwrite code object cy_os_common*.o, 131 readwrite code object cy_btstack_common*.o, 132 readwrite code object cy_btstack_gatt*.o, 133 readwrite code object cy_ipc*.o, 134 readwrite code object cy_btstack_porting*.o 135}; 136 137define block XIP {readonly}; 138 139/*-Initializations-*/ 140initialize by copy { readwrite }; /* copy .data section from flash to ram and initialize by ILINK */ 141initialize by copy { rw, section .cy_ramfunc }; /* copy .data section from flash to ram and initialize by ILINK */ 142initialize by copy { readonly object cy_smif.o }; 143initialize by copy { readonly object cy_smif_sfdp.o }; 144initialize by copy { readonly object cy_smif_memslot.o }; 145initialize by copy { readonly object cy_os_common*.o }; 146initialize by copy { readonly object cy_btstack_common*.o }; 147initialize by copy { readonly object cy_btstack_gatt*.o }; 148initialize by copy { readonly object cy_ipc*.o }; 149initialize by copy { readonly object cy_btstack_porting*.o }; 150do not initialize { section .noinit, section .intvec_ram }; /* exclude .noinit and .intvec_ram sections */ 151 152/*-Placement-*/ 153 154/* RAM */ 155place at start of CODE_region { block RO }; 156place in CODE_region { readonly object *startup_cat1b_cm33.o }; 157place in CODE_region { readonly object *system_cyw20829.o }; 158place in CODE_region { readonly object *cy_device.o }; 159place in CODE_region { readonly object *cy_btss.o }; 160place in CODE_region { readonly object *cy_sysclk_v2.o }; 161place in CODE_region { readonly object *cy_syspm_v2.o }; 162place in CODE_region { readonly object *cy_sysint_v2.o }; 163place in CODE_region { readonly object *cy_syslib*.o }; 164place in CODE_region { readonly object *ppu_v1.o }; 165place in CODE_region { readonly object *cy_mpc.o }; 166place in CODE_region { readonly object *cy_syspm_ppu.o }; 167place in CODE_region { readonly object *ABImemcpy.o }; 168place in CODE_region { readonly object *memcmp.o }; 169place in CODE_region { readonly object *ABImemset.o }; 170place in CODE_region { readonly object *ABImemset48.o }; 171place in CODE_region { readonly object *ABImemclr.o }; 172place in CODE_region { readonly object *ABImemclr4.o }; 173 174 175place in DATA_BS_region { readwrite object *startup_cat1b_cm33.o }; 176place in DATA_BS_region { readwrite object *system_cyw20829.o }; 177place in DATA_BS_region { readwrite object *cy_device.o }; 178place in DATA_BS_region { readwrite object *cy_btss.o }; 179place in DATA_BS_region { readwrite object *cy_sysclk_v2.o }; 180place in DATA_BS_region { readwrite object *cy_syspm_v2.o }; 181place in DATA_BS_region { readwrite object *cy_sysint_v2.o }; 182place in DATA_BS_region { readwrite object *cy_syslib*.o }; 183place in DATA_BS_region { readwrite object *ppu_v1.o }; 184place in DATA_BS_region { readwrite object *cy_mpc.o }; 185place in DATA_BS_region { readwrite object *cy_syspm_ppu.o }; 186 187place at start of DATA_region { block HSTACK }; 188place in DATA_region { block RAMVECTOR }; 189place in DATA_region { block APPTEXTRAM }; 190place in DATA_region { readwrite }; 191place at end of DATA_region { block HEAP }; 192 193 194place in XIP_region { block XIP }; 195 196 197keep { section .intvec }; 198 199 200define exported symbol __bootstrap_code_vma__ = CODE_VMA; 201define exported symbol __bootstrap_code_lma__ = CODE_LMA; 202define exported symbol __app_code_vma__ = XIP_VMA; 203define exported symbol __app_code_lma__ = XIP_LMA; 204define exported symbol __bootstrap_size__ = BOOTSTRAP_SIZE; 205define exported symbol __bootstrapzero_table_start__ = DATA_BS_VMA; 206define exported symbol __bootstrapzero_table_end__ = DATA_BS_VMA; 207define exported symbol __bootstrap_start_addr__ = RAM_END_ADDR_SAHB - BOOTSTRAP_SIZE; 208/* EOF */ 209
