1#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m33
2; The first line specifies a preprocessor command that the linker invokes
3; to pass a scatter file through a C preprocessor.
4
5;*******************************************************************************
6;* \file cyw20829_ns.sct
7;* \version 1.1.0
8;*
9;* Linker file for the ARMCC.
10;*
11;* The main purpose of the linker script is to describe how the sections in the
12;* input files should be mapped into the output file, and to control the memory
13;* layout of the output file.
14;*
15;* \note The entry point location is fixed and starts at 0x10000000. The valid
16;* application image should be placed there.
17;*
18;* \note The linker files included with the PDL template projects must be
19;* generic and handle all common use cases. Your project may not use every
20;* section defined in the linker files. In that case you may see the warnings
21;* during the build process: L6314W (no section matches pattern) and/or L6329W
22;* (pattern only matches removed unused sections). In your project, you can
23;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
24;* the linker, simply comment out or remove the relevant code in the linker
25;* file.
26;*
27;*******************************************************************************
28;* \copyright
29;* Copyright 2016-2020 Cypress Semiconductor Corporation
30;* SPDX-License-Identifier: Apache-2.0
31;*
32;* Licensed under the Apache License, Version 2.0 (the "License");
33;* you may not use this file except in compliance with the License.
34;* You may obtain a copy of the License at
35;*
36;*     http://www.apache.org/licenses/LICENSE-2.0
37;*
38;* Unless required by applicable law or agreed to in writing, software
39;* distributed under the License is distributed on an "AS IS" BASIS,
40;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
41;* See the License for the specific language governing permissions and
42;* limitations under the License.
43;******************************************************************************/
44
45; The defines below describe the location and size of blocks of memory in the target.
46; Use these defines to specify the memory regions available for allocation.
47
48; The following defines control RAM and flash memory allocation for the CM33 core.
49; RAM
50
51#define CODE_ROM_NS_CBUS_START 0x00000000
52#define CODE_ROM_NS_CBUS_SIZE 0x00010000
53#define CODE_SRAM0_NS_CBUS_START 0x04004200
54#define CODE_SRAM0_NS_CBUS_SIZE 0x0001E000
55#define CODE_XIP_NS_CBUS_START 0x08000000
56#define CODE_XIP_NS_CBUS_SIZE 0x08000000
57
58#define DATA_ROM_NS_SAHB_START 0x00000000
59#define DATA_ROM_NS_SAHB_SIZE  0x00000000
60#define BSS_ROM_NS_SAHB_START 0x00000000
61#define BSS_ROM_NS_SAHB_SIZE 0x00000000
62#define DATA_SRAM0_NS_SAHB_START 0x20022200
63#define DATA_SRAM0_NS_SAHB_SIZE  0x0001DE00
64#define BSS_SRAM0_NS_SAHB_START 0x20000000
65#define BSS_SRAM0_NS_SAHB_SIZE 0x00000000
66#define DATA_XIP_NS_SAHB_START 0x60000000
67#define DATA_XIP_NS_SAHB_SIZE  0x00000000
68#define BSS_XIP_NS_SAHB_START 0x60000000
69#define BSS_XIP_NS_SAHB_SIZE 0x00000000
70
71
72/*
73#define RAM_START               0x20004200
74#define RAM_SIZE                0x0001BE00
75*/
76#define RAM_START               DATA_SRAM0_NS_SAHB_START
77#define RAM_SIZE                DATA_SRAM0_NS_SAHB_SIZE
78
79; Flash
80/*
81#define FLASH_START             0x60000000
82#define FLASH_SIZE              0x00010000
83*/
84
85#define FLASH_START             CODE_SRAM0_NS_CBUS_START
86#define FLASH_SIZE              CODE_SRAM0_NS_CBUS_SIZE
87
88; The size of the stack section at the end of CM33 SRAM
89#define STACK_SIZE              0x00001000
90
91; The size of the MCU boot header area at the start of FLASH
92#define BOOT_HEADER_SIZE        0x00000000
93
94; The following defines describe device specific memory regions and must not be changed.
95
96; External memory
97#define XIP_START               CODE_XIP_NS_CBUS_START
98#define XIP_SIZE                CODE_XIP_NS_CBUS_SIZE
99
100
101; Cortex-M33 application flash area
102LR_IROM1 (FLASH_START + BOOT_HEADER_SIZE) (FLASH_SIZE - BOOT_HEADER_SIZE)
103{
104    ER_FLASH_VECTORS +0
105    {
106        * (RESET, +FIRST)
107    }
108
109    ER_FLASH_CODE +0 FIXED
110    {
111        * (InRoot$$Sections)
112        * (+RO)
113    }
114
115    ER_RAM_VECTORS RAM_START UNINIT
116    {
117        * (.bss.noinit.RESET_RAM, +FIRST)
118    }
119
120    RW_RAM_DATA +0
121    {
122        * (.cy_ramfunc)
123        * (+RW, +ZI)
124    }
125
126    ; Place variables in the section that should not be initialized during the
127    ; device startup.
128    RW_IRAM1 +0 UNINIT
129    {
130        * (.noinit)
131        * (.bss.noinit)
132    }
133
134    ; Application heap area (HEAP)
135    ARM_LIB_HEAP  +0 ALIGN 8 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE)
136    {
137    }
138
139    ; Stack region growing down
140    ARM_LIB_STACK (RAM_START+RAM_SIZE) ALIGN 32 EMPTY -STACK_SIZE
141    {
142    }
143
144    ; Used for the digital signature of the secure application and the
145    ; Bootloader SDK application. The size of the section depends on the required
146    ; data size.
147    .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256
148    {
149        * (.cy_app_signature)
150    }
151}
152
153
154; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
155LR_EROM XIP_START XIP_SIZE
156{
157    cy_xip +0
158    {
159        * (.cy_xip)
160    }
161}
162
163
164/* [] END OF FILE */
165