1/*******************************************************************************
2* \file cyb06xx5_cm4_dual.icf
3* \version 2.95.1
4*
5* Linker file for the IAR compiler.
6*
7* The main purpose of the linker script is to describe how the sections in the
8* input files should be mapped into the output file, and to control the memory
9* layout of the output file.
10*
11* \note The entry point is fixed and starts at 0x10000000. The valid application
12* image should be placed there.
13*
14* \note The linker files included with the PDL template projects must be generic
15* and handle all common use cases. Your project may not use every section
16* defined in the linker files. In that case you may see warnings during the
17* build process. In your project, you can simply comment out or remove the
18* relevant code in the linker file.
19*
20********************************************************************************
21* \copyright
22* Copyright 2016-2021 Cypress Semiconductor Corporation
23* SPDX-License-Identifier: Apache-2.0
24*
25* Licensed under the Apache License, Version 2.0 (the "License");
26* you may not use this file except in compliance with the License.
27* You may obtain a copy of the License at
28*
29*     http://www.apache.org/licenses/LICENSE-2.0
30*
31* Unless required by applicable law or agreed to in writing, software
32* distributed under the License is distributed on an "AS IS" BASIS,
33* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
34* See the License for the specific language governing permissions and
35* limitations under the License.
36*******************************************************************************/
37
38/*###ICF### Section handled by ICF editor, don't touch! ****/
39/*-Editor annotation file-*/
40/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */
41/*-Specials-*/
42define symbol __ICFEDIT_intvec_start__ = 0x00000000;
43
44/* The symbols below define the location and size of blocks of memory in the target.
45 * Use these symbols to specify the memory regions available for allocation.
46 */
47
48/* The following symbols control RAM and flash memory allocation for the CM4 core.
49 * You can change the memory allocation by editing RAM and Flash symbols.
50 * Your changes must be aligned with the corresponding symbols for CM0+ core in 'xx_cm0plus.icf',
51 * where 'xx' is the device group; for example, 'cyb06xx7_cm0plus.icf'.
52 */
53/* RAM */
54define symbol __ICFEDIT_region_IRAM1_start__ = 0x08000800;
55define symbol __ICFEDIT_region_IRAM1_end__   = 0x0801FFFF;
56
57/* Flash */
58define symbol __ICFEDIT_region_IROM1_start__ = 0x10000000;
59define symbol __ICFEDIT_region_IROM1_end__   = 0x1002FFFF;
60
61/* The following symbols define a 32K flash region used for EEPROM emulation.
62 * This region can also be used as the general purpose flash.
63 * You can assign sections to this memory region for only one of the cores.
64 * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
65 * Therefore, repurposing this memory region will prevent such middleware from operation.
66 */
67define symbol __ICFEDIT_region_IROM2_start__ = 0x14000000;
68define symbol __ICFEDIT_region_IROM2_end__   = 0x14007FFF;
69
70/* The following symbols define device specific memory regions and must not be changed. */
71/* XIP */
72define symbol __ICFEDIT_region_EROM1_start__ = 0x18000000;
73define symbol __ICFEDIT_region_EROM1_end__   = 0x1FFFFFFF;
74
75define symbol __ICFEDIT_region_EROM2_start__ = 0x0;
76define symbol __ICFEDIT_region_EROM2_end__   = 0x0;
77define symbol __ICFEDIT_region_EROM3_start__ = 0x0;
78define symbol __ICFEDIT_region_EROM3_end__   = 0x0;
79
80
81define symbol __ICFEDIT_region_IRAM2_start__ = 0x0;
82define symbol __ICFEDIT_region_IRAM2_end__   = 0x0;
83define symbol __ICFEDIT_region_ERAM1_start__ = 0x0;
84define symbol __ICFEDIT_region_ERAM1_end__   = 0x0;
85define symbol __ICFEDIT_region_ERAM2_start__ = 0x0;
86define symbol __ICFEDIT_region_ERAM2_end__   = 0x0;
87define symbol __ICFEDIT_region_ERAM3_start__ = 0x0;
88define symbol __ICFEDIT_region_ERAM3_end__   = 0x0;
89/*-Sizes-*/
90if (!isdefinedsymbol(__STACK_SIZE)) {
91  define symbol __ICFEDIT_size_cstack__ = 0x1000;
92} else {
93  define symbol __ICFEDIT_size_cstack__ = __STACK_SIZE;
94}
95define symbol __ICFEDIT_size_proc_stack__ = 0x0;
96
97/* Defines the minimum heap size. The actual heap size will be expanded to the end of the stack region */
98if (!isdefinedsymbol(__HEAP_SIZE)) {
99    define symbol __ICFEDIT_size_heap__ = 0x0400;
100} else {
101  define symbol __ICFEDIT_size_heap__ = __HEAP_SIZE;
102}
103/**** End of ICF editor section. ###ICF###*/
104
105/* The size of the MCU boot header area at the start of FLASH */
106define symbol BOOT_HEADER_SIZE  = 0x400;
107
108/* The size of the Cortex-M0+ application image (including MCU boot header area) */
109define symbol FLASH_CM0P_SIZE  = 0x10000;
110
111define memory mem with size = 4G;
112define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__];
113define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__];
114define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__];
115define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__];
116
117define block CSTACK     with alignment = 8, size = __ICFEDIT_size_cstack__     { };
118define block PROC_STACK with alignment = 8, size = __ICFEDIT_size_proc_stack__ { };
119define block HEAP       with expanding size, alignment = 8, minimum size = __ICFEDIT_size_heap__ { };
120define block HSTACK {block HEAP, block PROC_STACK, last block CSTACK};
121define block CM0P_RO with size = (FLASH_CM0P_SIZE - BOOT_HEADER_SIZE)  { readonly section .cy_m0p_image };
122define block RO     {first section .intvec, readonly};
123
124define block cy_xip { section .cy_xip };
125
126/*-Initializations-*/
127initialize by copy { readwrite };
128do not initialize  { section .noinit, section .intvec_ram };
129
130/*-Placement-*/
131
132/* Flash - Cortex-M0+ application image */
133place at address (__ICFEDIT_region_IROM1_start__ + BOOT_HEADER_SIZE)  { block CM0P_RO };
134
135/* Flash - Cortex-M4 application */
136place at address (__ICFEDIT_region_IROM1_start__ + FLASH_CM0P_SIZE) { block RO };
137
138/* Used for the digital signature of the secure application and the Bootloader SDK application. */
139".cy_app_signature" : place at address (__ICFEDIT_region_IROM1_end__ - 0x200) { section .cy_app_signature };
140
141
142/* Execute in Place (XIP). See the smif driver documentation for details. */
143"cy_xip" : place at start of EROM1_region  { block cy_xip };
144
145/* RAM */
146place at start of IRAM1_region  { readwrite section .intvec_ram};
147place in          IRAM1_region  { readwrite };
148place at end   of IRAM1_region  { block HSTACK };
149
150keep {  section .cy_m0p_image,
151        section .cy_app_signature,
152        section .cy_xip,
153         };
154
155
156
157/* EOF */
158