1/*******************************************************************************
2* \file cy8c6xx4_cm4_dual.icf
3* \version 2.95.1
4*
5* Linker file for the IAR compiler.
6*
7* The main purpose of the linker script is to describe how the sections in the
8* input files should be mapped into the output file, and to control the memory
9* layout of the output file.
10*
11* \note The entry point is fixed and starts at 0x10000000. The valid application
12* image should be placed there.
13*
14* \note The linker files included with the PDL template projects must be generic
15* and handle all common use cases. Your project may not use every section
16* defined in the linker files. In that case you may see warnings during the
17* build process. In your project, you can simply comment out or remove the
18* relevant code in the linker file.
19*
20********************************************************************************
21* \copyright
22* Copyright 2016-2021 Cypress Semiconductor Corporation
23* SPDX-License-Identifier: Apache-2.0
24*
25* Licensed under the Apache License, Version 2.0 (the "License");
26* you may not use this file except in compliance with the License.
27* You may obtain a copy of the License at
28*
29*     http://www.apache.org/licenses/LICENSE-2.0
30*
31* Unless required by applicable law or agreed to in writing, software
32* distributed under the License is distributed on an "AS IS" BASIS,
33* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
34* See the License for the specific language governing permissions and
35* limitations under the License.
36*******************************************************************************/
37
38/*###ICF### Section handled by ICF editor, don't touch! ****/
39/*-Editor annotation file-*/
40/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */
41/*-Specials-*/
42define symbol __ICFEDIT_intvec_start__ = 0x00000000;
43
44/* The symbols below define the location and size of blocks of memory in the target.
45 * Use these symbols to specify the memory regions available for allocation.
46 */
47
48/* The following symbols control RAM and flash memory allocation for the CM4 core.
49 * You can change the memory allocation by editing RAM and Flash symbols.
50 * Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
51 * Using this memory region for other purposes will lead to unexpected behavior.
52 * Your changes must be aligned with the corresponding symbols for CM0+ core in 'xx_cm0plus.icf',
53 * where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.icf'.
54 */
55/* RAM */
56define symbol __ICFEDIT_region_IRAM1_start__ = 0x08002000;
57define symbol __ICFEDIT_region_IRAM1_end__   = 0x0801F7FF;
58
59/* Flash */
60define symbol __ICFEDIT_region_IROM1_start__ = 0x10000000;
61define symbol __ICFEDIT_region_IROM1_end__   = 0x1003FFFF;
62
63/* The following symbols define a 32K flash region used for EEPROM emulation.
64 * This region can also be used as the general purpose flash.
65 * You can assign sections to this memory region for only one of the cores.
66 * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
67 * Therefore, repurposing this memory region will prevent such middleware from operation.
68 */
69define symbol __ICFEDIT_region_IROM2_start__ = 0x14000000;
70define symbol __ICFEDIT_region_IROM2_end__   = 0x14007FFF;
71
72/* The following symbols define device specific memory regions and must not be changed. */
73/* Supervisory FLASH - User Data */
74define symbol __ICFEDIT_region_IROM3_start__ = 0x16000800;
75define symbol __ICFEDIT_region_IROM3_end__   = 0x16000FFF;
76
77/* Supervisory FLASH - Normal Access Restrictions (NAR) */
78define symbol __ICFEDIT_region_IROM4_start__ = 0x16001A00;
79define symbol __ICFEDIT_region_IROM4_end__   = 0x16001BFF;
80
81/* Supervisory FLASH - Public Key */
82define symbol __ICFEDIT_region_IROM5_start__ = 0x16005A00;
83define symbol __ICFEDIT_region_IROM5_end__   = 0x160065FF;
84
85/* Supervisory FLASH - Table of Content # 2 */
86define symbol __ICFEDIT_region_IROM6_start__ = 0x16007C00;
87define symbol __ICFEDIT_region_IROM6_end__   = 0x16007DFF;
88
89/* Supervisory FLASH - Table of Content # 2 Copy */
90define symbol __ICFEDIT_region_IROM7_start__ = 0x16007E00;
91define symbol __ICFEDIT_region_IROM7_end__   = 0x16007FFF;
92
93/* eFuse */
94define symbol __ICFEDIT_region_IROM8_start__ = 0x90700000;
95define symbol __ICFEDIT_region_IROM8_end__   = 0x907FFFFF;
96
97/* XIP */
98define symbol __ICFEDIT_region_EROM1_start__ = 0x18000000;
99define symbol __ICFEDIT_region_EROM1_end__   = 0x1FFFFFFF;
100
101define symbol __ICFEDIT_region_EROM2_start__ = 0x0;
102define symbol __ICFEDIT_region_EROM2_end__   = 0x0;
103define symbol __ICFEDIT_region_EROM3_start__ = 0x0;
104define symbol __ICFEDIT_region_EROM3_end__   = 0x0;
105
106
107define symbol __ICFEDIT_region_IRAM2_start__ = 0x0;
108define symbol __ICFEDIT_region_IRAM2_end__   = 0x0;
109define symbol __ICFEDIT_region_ERAM1_start__ = 0x0;
110define symbol __ICFEDIT_region_ERAM1_end__   = 0x0;
111define symbol __ICFEDIT_region_ERAM2_start__ = 0x0;
112define symbol __ICFEDIT_region_ERAM2_end__   = 0x0;
113define symbol __ICFEDIT_region_ERAM3_start__ = 0x0;
114define symbol __ICFEDIT_region_ERAM3_end__   = 0x0;
115/*-Sizes-*/
116if (!isdefinedsymbol(__STACK_SIZE)) {
117  define symbol __ICFEDIT_size_cstack__ = 0x1000;
118} else {
119  define symbol __ICFEDIT_size_cstack__ = __STACK_SIZE;
120}
121define symbol __ICFEDIT_size_proc_stack__ = 0x0;
122
123/* Defines the minimum heap size. The actual heap size will be expanded to the end of the stack region */
124if (!isdefinedsymbol(__HEAP_SIZE)) {
125    define symbol __ICFEDIT_size_heap__ = 0x0400;
126} else {
127  define symbol __ICFEDIT_size_heap__ = __HEAP_SIZE;
128}
129/**** End of ICF editor section. ###ICF###*/
130
131/* By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core.
132 * More about CM0+ prebuilt images, see here:
133 * https://github.com/Infineon/psoc6cm0p
134 */
135/* The size of the Cortex-M0+ application image */
136define symbol FLASH_CM0P_SIZE  = 0x2000;
137
138define memory mem with size = 4G;
139define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__];
140define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__];
141define region IROM3_region = mem:[from __ICFEDIT_region_IROM3_start__ to __ICFEDIT_region_IROM3_end__];
142define region IROM4_region = mem:[from __ICFEDIT_region_IROM4_start__ to __ICFEDIT_region_IROM4_end__];
143define region IROM5_region = mem:[from __ICFEDIT_region_IROM5_start__ to __ICFEDIT_region_IROM5_end__];
144define region IROM6_region = mem:[from __ICFEDIT_region_IROM6_start__ to __ICFEDIT_region_IROM6_end__];
145define region IROM7_region = mem:[from __ICFEDIT_region_IROM7_start__ to __ICFEDIT_region_IROM7_end__];
146define region IROM8_region = mem:[from __ICFEDIT_region_IROM8_start__ to __ICFEDIT_region_IROM8_end__];
147define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__];
148define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__];
149
150define block CSTACK     with alignment = 8, size = __ICFEDIT_size_cstack__     { };
151define block PROC_STACK with alignment = 8, size = __ICFEDIT_size_proc_stack__ { };
152define block HEAP       with expanding size, alignment = 8, minimum size = __ICFEDIT_size_heap__ { };
153define block HSTACK {block HEAP, block PROC_STACK, last block CSTACK};
154define block CM0P_RO with size = FLASH_CM0P_SIZE  { readonly section .cy_m0p_image };
155define block RO     {first section .intvec, readonly};
156
157define block cy_xip { section .cy_xip };
158
159/*-Initializations-*/
160initialize by copy { readwrite };
161do not initialize  { section .noinit, section .intvec_ram };
162
163/*-Placement-*/
164
165/* Flash - Cortex-M0+ application image */
166place at start of IROM1_region  { block CM0P_RO };
167
168/* Flash - Cortex-M4 application */
169place at address (__ICFEDIT_region_IROM1_start__ + FLASH_CM0P_SIZE) { block RO };
170
171/* Used for the digital signature of the secure application and the Bootloader SDK application. */
172".cy_app_signature" : place at address (__ICFEDIT_region_IROM1_end__ - 0x200) { section .cy_app_signature };
173
174
175/* Supervisory Flash - User Data */
176".cy_sflash_user_data" : place at start of IROM3_region  { section .cy_sflash_user_data };
177
178/* Supervisory Flash - NAR */
179".cy_sflash_nar" : place at start of IROM4_region  { section .cy_sflash_nar };
180
181/* Supervisory Flash - Public Key */
182".cy_sflash_public_key" : place at start of IROM5_region  { section .cy_sflash_public_key };
183
184/* Supervisory Flash - TOC2 */
185".cy_toc_part2" : place at start of IROM6_region  { section .cy_toc_part2 };
186
187/* Supervisory Flash - RTOC2 */
188".cy_rtoc_part2" : place at start of IROM7_region  { section .cy_rtoc_part2 };
189
190/* eFuse */
191".cy_efuse" : place at start of IROM8_region  { section .cy_efuse };
192
193/* Execute in Place (XIP). See the smif driver documentation for details. */
194"cy_xip" : place at start of EROM1_region  { block cy_xip };
195
196/* RAM */
197place at start of IRAM1_region  { readwrite section .intvec_ram};
198place in          IRAM1_region  { readwrite };
199place at end   of IRAM1_region  { block HSTACK };
200
201/* These sections are used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. */
202".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta };
203
204
205keep {  section .cy_m0p_image,
206        section .cy_app_signature,
207        section .cy_sflash_user_data,
208        section .cy_sflash_nar,
209        section .cy_sflash_public_key,
210        section .cy_toc_part2,
211        section .cy_rtoc_part2,
212        section .cy_efuse,
213        section .cy_xip,
214        section .cymeta,
215         };
216
217
218/* The following symbols used by the cymcuelftool. */
219/* Flash */
220define exported symbol __cy_memory_0_start    = 0x10000000;
221define exported symbol __cy_memory_0_length   = 0x00040000;
222define exported symbol __cy_memory_0_row_size = 0x200;
223
224
225/* Supervisory Flash */
226define exported symbol __cy_memory_2_start    = 0x16000000;
227define exported symbol __cy_memory_2_length   = 0x8000;
228define exported symbol __cy_memory_2_row_size = 0x200;
229
230/* XIP */
231define exported symbol __cy_memory_3_start    = 0x18000000;
232define exported symbol __cy_memory_3_length   = 0x08000000;
233define exported symbol __cy_memory_3_row_size = 0x200;
234
235/* eFuse */
236define exported symbol __cy_memory_4_start    = 0x90700000;
237define exported symbol __cy_memory_4_length   = 0x100000;
238define exported symbol __cy_memory_4_row_size = 1;
239
240/* EOF */
241