1#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
2; The first line specifies a preprocessor command that the linker invokes
3; to pass a scatter file through a C preprocessor.
4
5;*******************************************************************************
6;* \file cyb06xxa_cm4_dual.sct
7;* \version 2.95.1
8;*
9;* Linker file for the ARMCC.
10;*
11;* The main purpose of the linker script is to describe how the sections in the
12;* input files should be mapped into the output file, and to control the memory
13;* layout of the output file.
14;*
15;* \note The entry point location is fixed and starts at 0x10000000. The valid
16;* application image should be placed there.
17;*
18;* \note The linker files included with the PDL template projects must be
19;* generic and handle all common use cases. Your project may not use every
20;* section defined in the linker files. In that case you may see the warnings
21;* during the build process: L6314W (no section matches pattern) and/or L6329W
22;* (pattern only matches removed unused sections). In your project, you can
23;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
24;* the linker, simply comment out or remove the relevant code in the linker
25;* file.
26;*
27;*******************************************************************************
28;* \copyright
29;* Copyright 2016-2021 Cypress Semiconductor Corporation
30;* SPDX-License-Identifier: Apache-2.0
31;*
32;* Licensed under the Apache License, Version 2.0 (the "License");
33;* you may not use this file except in compliance with the License.
34;* You may obtain a copy of the License at
35;*
36;*     http://www.apache.org/licenses/LICENSE-2.0
37;*
38;* Unless required by applicable law or agreed to in writing, software
39;* distributed under the License is distributed on an "AS IS" BASIS,
40;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
41;* See the License for the specific language governing permissions and
42;* limitations under the License.
43;******************************************************************************/
44
45; The defines below describe the location and size of blocks of memory in the target.
46; Use these defines to specify the memory regions available for allocation.
47
48; The following defines control RAM and flash memory allocation for the CM4 core.
49; You can change the memory allocation by editing RAM and Flash defines.
50; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat',
51; where 'xx' is the device group; for example, 'cyb06xx7_cm0plus.scat'.
52; RAM
53#define RAM_START               0x08000800
54#define RAM_SIZE                0x000DF800
55; Flash
56#define FLASH_START             0x10000000
57#define FLASH_SIZE              0x000E0000
58
59; The size of the stack section at the end of CM4 SRAM
60#define STACK_SIZE              0x00001000
61
62; The size of the MCU boot header area at the start of FLASH
63#define BOOT_HEADER_SIZE        0x00000400
64
65; The size of the Cortex-M0+ application image (including MCU boot header area)
66#define FLASH_CM0P_SIZE         0x10000
67
68; The following defines describe a 32K flash region used for EEPROM emulation.
69; This region can also be used as the general purpose flash.
70; You can assign sections to this memory region for only one of the cores.
71; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
72; Therefore, repurposing this memory region will prevent such middleware from operation.
73#define EM_EEPROM_START         0x14000000
74#define EM_EEPROM_SIZE          0x8000
75
76; The following defines describe device specific memory regions and must not be changed.
77; External memory
78#define XIP_START               0x18000000
79#define XIP_SIZE                0x08000000
80
81
82; Cortex-M0+ application flash image area
83LR_IROM (FLASH_START + BOOT_HEADER_SIZE) (FLASH_CM0P_SIZE - BOOT_HEADER_SIZE)
84{
85    .cy_m0p_image +0
86    {
87        * (.cy_m0p_image)
88    }
89}
90
91; Cortex-M4 application flash area
92LR_IROM1 (FLASH_START + FLASH_CM0P_SIZE) (FLASH_SIZE - FLASH_CM0P_SIZE)
93{
94    ER_FLASH_VECTORS +0
95    {
96        * (RESET, +FIRST)
97    }
98
99    ER_FLASH_CODE +0 FIXED
100    {
101        * (InRoot$$Sections)
102        * (+RO)
103    }
104
105    ER_RAM_VECTORS RAM_START UNINIT
106    {
107        * (RESET_RAM, +FIRST)
108    }
109
110    RW_RAM_DATA +0
111    {
112        * (.cy_ramfunc)
113        * (+RW, +ZI)
114    }
115
116    ; Place variables in the section that should not be initialized during the
117    ; device startup.
118    RW_IRAM1 +0 UNINIT
119    {
120        * (.noinit)
121        * (.bss.noinit)
122    }
123
124    ; Application heap area (HEAP)
125    ARM_LIB_HEAP  +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE)
126    {
127    }
128
129    ; Stack region growing down
130    ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
131    {
132    }
133
134    ; Used for the digital signature of the secure application and the
135    ; Bootloader SDK application. The size of the section depends on the required
136    ; data size.
137    .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256
138    {
139        * (.cy_app_signature)
140    }
141}
142
143
144; Emulated EEPROM Flash area
145LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
146{
147    .cy_em_eeprom +0
148    {
149        * (.cy_em_eeprom)
150    }
151}
152
153; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
154LR_EROM XIP_START XIP_SIZE
155{
156    cy_xip +0
157    {
158        * (.cy_xip)
159    }
160}
161
162
163/* [] END OF FILE */
164