1#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
2; The first line specifies a preprocessor command that the linker invokes
3; to pass a scatter file through a C preprocessor.
4
5;*******************************************************************************
6;* \file cy8c6xx4_cm4_dual.sct
7;* \version 2.95.1
8;*
9;* Linker file for the ARMCC.
10;*
11;* The main purpose of the linker script is to describe how the sections in the
12;* input files should be mapped into the output file, and to control the memory
13;* layout of the output file.
14;*
15;* \note The entry point location is fixed and starts at 0x10000000. The valid
16;* application image should be placed there.
17;*
18;* \note The linker files included with the PDL template projects must be
19;* generic and handle all common use cases. Your project may not use every
20;* section defined in the linker files. In that case you may see the warnings
21;* during the build process: L6314W (no section matches pattern) and/or L6329W
22;* (pattern only matches removed unused sections). In your project, you can
23;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
24;* the linker, simply comment out or remove the relevant code in the linker
25;* file.
26;*
27;*******************************************************************************
28;* \copyright
29;* Copyright 2016-2021 Cypress Semiconductor Corporation
30;* SPDX-License-Identifier: Apache-2.0
31;*
32;* Licensed under the Apache License, Version 2.0 (the "License");
33;* you may not use this file except in compliance with the License.
34;* You may obtain a copy of the License at
35;*
36;*     http://www.apache.org/licenses/LICENSE-2.0
37;*
38;* Unless required by applicable law or agreed to in writing, software
39;* distributed under the License is distributed on an "AS IS" BASIS,
40;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
41;* See the License for the specific language governing permissions and
42;* limitations under the License.
43;******************************************************************************/
44
45; The defines below describe the location and size of blocks of memory in the target.
46; Use these defines to specify the memory regions available for allocation.
47
48; The following defines control RAM and flash memory allocation for the CM4 core.
49; You can change the memory allocation by editing RAM and Flash defines.
50; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
51; Using this memory region for other purposes will lead to unexpected behavior.
52; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat',
53; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'.
54; RAM
55#define RAM_START               0x08002000
56#define RAM_SIZE                0x0001D800
57; Flash
58#define FLASH_START             0x10000000
59#define FLASH_SIZE              0x00040000
60
61; The size of the stack section at the end of CM4 SRAM
62#define STACK_SIZE              0x00001000
63
64; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core.
65; More about CM0+ prebuilt images, see here:
66; https://github.com/Infineon/psoc6cm0p
67; The size of the Cortex-M0+ application flash image
68#define FLASH_CM0P_SIZE         0x2000
69
70
71; The following defines describe device specific memory regions and must not be changed.
72; Supervisory flash: User data
73#define SFLASH_USER_DATA_START  0x16000800
74#define SFLASH_USER_DATA_SIZE   0x00000800
75
76; Supervisory flash: Normal Access Restrictions (NAR)
77#define SFLASH_NAR_START        0x16001A00
78#define SFLASH_NAR_SIZE         0x00000200
79
80; Supervisory flash: Public Key
81#define SFLASH_PUBLIC_KEY_START 0x16005A00
82#define SFLASH_PUBLIC_KEY_SIZE  0x00000C00
83
84; Supervisory flash: Table of Content # 2
85#define SFLASH_TOC_2_START      0x16007C00
86#define SFLASH_TOC_2_SIZE       0x00000200
87
88; Supervisory flash: Table of Content # 2 Copy
89#define SFLASH_RTOC_2_START     0x16007E00
90#define SFLASH_RTOC_2_SIZE      0x00000200
91
92; External memory
93#define XIP_START               0x18000000
94#define XIP_SIZE                0x08000000
95
96; eFuse
97#define EFUSE_START             0x90700000
98#define EFUSE_SIZE              0x100000
99
100
101; Cortex-M0+ application flash image area
102LR_IROM FLASH_START FLASH_CM0P_SIZE
103{
104    .cy_m0p_image +0 FLASH_CM0P_SIZE
105    {
106        * (.cy_m0p_image)
107    }
108}
109
110; Cortex-M4 application flash area
111LR_IROM1 (FLASH_START + FLASH_CM0P_SIZE) (FLASH_SIZE - FLASH_CM0P_SIZE)
112{
113    ER_FLASH_VECTORS +0
114    {
115        * (RESET, +FIRST)
116    }
117
118    ER_FLASH_CODE +0 FIXED
119    {
120        * (InRoot$$Sections)
121        * (+RO)
122    }
123
124    ER_RAM_VECTORS RAM_START UNINIT
125    {
126        * (RESET_RAM, +FIRST)
127    }
128
129    RW_RAM_DATA +0
130    {
131        * (.cy_ramfunc)
132        * (+RW, +ZI)
133    }
134
135    ; Place variables in the section that should not be initialized during the
136    ; device startup.
137    RW_IRAM1 +0 UNINIT
138    {
139        * (.noinit)
140        * (.bss.noinit)
141    }
142
143    ; Application heap area (HEAP)
144    ARM_LIB_HEAP  +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE)
145    {
146    }
147
148    ; Stack region growing down
149    ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
150    {
151    }
152
153    ; Used for the digital signature of the secure application and the
154    ; Bootloader SDK application. The size of the section depends on the required
155    ; data size.
156    .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256
157    {
158        * (.cy_app_signature)
159    }
160}
161
162
163
164; Supervisory flash: User data
165LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
166{
167    .cy_sflash_user_data +0
168    {
169        * (.cy_sflash_user_data)
170    }
171}
172
173; Supervisory flash: Normal Access Restrictions (NAR)
174LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
175{
176    .cy_sflash_nar +0
177    {
178        * (.cy_sflash_nar)
179    }
180}
181
182; Supervisory flash: Public Key
183LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
184{
185    .cy_sflash_public_key +0
186    {
187        * (.cy_sflash_public_key)
188    }
189}
190
191; Supervisory flash: Table of Content # 2
192LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
193{
194    .cy_toc_part2 +0
195    {
196        * (.cy_toc_part2)
197    }
198}
199
200; Supervisory flash: Table of Content # 2 Copy
201LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
202{
203    .cy_rtoc_part2 +0
204    {
205        * (.cy_rtoc_part2)
206    }
207}
208
209
210; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
211LR_EROM XIP_START XIP_SIZE
212{
213    cy_xip +0
214    {
215        * (.cy_xip)
216    }
217}
218
219
220; eFuse
221LR_EFUSE EFUSE_START EFUSE_SIZE
222{
223    .cy_efuse +0
224    {
225        * (.cy_efuse)
226    }
227}
228
229
230; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
231CYMETA 0x90500000
232{
233    .cymeta +0 { * (.cymeta) }
234}
235
236/* The following symbols used by the cymcuelftool. */
237/* Flash */
238#define __cy_memory_0_start 0x10000000
239#define __cy_memory_0_length  0x00040000
240#define __cy_memory_0_row_size 0x200
241
242
243/* Supervisory Flash */
244#define __cy_memory_2_start    0x16000000
245#define __cy_memory_2_length   0x8000
246#define __cy_memory_2_row_size 0x200
247
248/* XIP */
249#define __cy_memory_3_start    0x18000000
250#define __cy_memory_3_length   0x08000000
251#define __cy_memory_3_row_size 0x200
252
253/* eFuse */
254#define __cy_memory_4_start    0x90700000
255#define __cy_memory_4_length   0x100000
256#define __cy_memory_4_row_size 1
257
258
259/* [] END OF FILE */
260