1#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
2; The first line specifies a preprocessor command that the linker invokes
3; to pass a scatter file through a C preprocessor.
4
5;*******************************************************************************
6;* \file cy8c6xx4_cm4.sct
7;* \version 2.95.1
8;*
9;* Linker file for the ARMCC.
10;*
11;* The main purpose of the linker script is to describe how the sections in the
12;* input files should be mapped into the output file, and to control the memory
13;* layout of the output file.
14;*
15;* \note The entry point location is fixed and starts at 0x10000000. The valid
16;* application image should be placed there.
17;*
18;* \note The linker files included with the PDL template projects must be
19;* generic and handle all common use cases. Your project may not use every
20;* section defined in the linker files. In that case you may see the warnings
21;* during the build process: L6314W (no section matches pattern) and/or L6329W
22;* (pattern only matches removed unused sections). In your project, you can
23;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
24;* the linker, simply comment out or remove the relevant code in the linker
25;* file.
26;*
27;*******************************************************************************
28;* \copyright
29;* Copyright 2016-2021 Cypress Semiconductor Corporation
30;* SPDX-License-Identifier: Apache-2.0
31;*
32;* Licensed under the Apache License, Version 2.0 (the "License");
33;* you may not use this file except in compliance with the License.
34;* You may obtain a copy of the License at
35;*
36;*     http://www.apache.org/licenses/LICENSE-2.0
37;*
38;* Unless required by applicable law or agreed to in writing, software
39;* distributed under the License is distributed on an "AS IS" BASIS,
40;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
41;* See the License for the specific language governing permissions and
42;* limitations under the License.
43;******************************************************************************/
44
45; The defines below describe the location and size of blocks of memory in the target.
46; Use these defines to specify the memory regions available for allocation.
47
48; The following defines control RAM and flash memory allocation for the CM4 core.
49; Note that 2176 bytes of RAM (at the end of the SRAM) are reserved for system use.
50; Using this memory region for other purposes will lead to unexpected behavior.
51; RAM
52#define RAM_START               0x08000000
53#define RAM_SIZE                0x0001F780
54; Flash
55#define FLASH_START             0x10000000
56#define FLASH_SIZE              0x00040000
57
58; The size of the stack section at the end of CM4 SRAM
59#define STACK_SIZE              0x00001000
60
61
62; The following defines describe device specific memory regions and must not be changed.
63; Supervisory flash: User data
64#define SFLASH_USER_DATA_START  0x16000800
65#define SFLASH_USER_DATA_SIZE   0x00000800
66
67; Supervisory flash: Normal Access Restrictions (NAR)
68#define SFLASH_NAR_START        0x16001A00
69#define SFLASH_NAR_SIZE         0x00000200
70
71; Supervisory flash: Public Key
72#define SFLASH_PUBLIC_KEY_START 0x16005A00
73#define SFLASH_PUBLIC_KEY_SIZE  0x00000C00
74
75; Supervisory flash: Table of Content # 2
76#define SFLASH_TOC_2_START      0x16007C00
77#define SFLASH_TOC_2_SIZE       0x00000200
78
79; Supervisory flash: Table of Content # 2 Copy
80#define SFLASH_RTOC_2_START     0x16007E00
81#define SFLASH_RTOC_2_SIZE      0x00000200
82
83; External memory
84#define XIP_START               0x18000000
85#define XIP_SIZE                0x08000000
86
87; eFuse
88#define EFUSE_START             0x90700000
89#define EFUSE_SIZE              0x100000
90
91
92; Cortex-M4 application flash area
93LR_IROM1 FLASH_START FLASH_SIZE
94{
95    ER_FLASH_VECTORS +0
96    {
97        * (RESET, +FIRST)
98    }
99
100    ER_FLASH_CODE +0 FIXED
101    {
102        * (InRoot$$Sections)
103        * (+RO)
104    }
105
106    ER_RAM_VECTORS RAM_START UNINIT
107    {
108        * (RESET_RAM, +FIRST)
109    }
110
111    RW_RAM_DATA +0
112    {
113        * (.cy_ramfunc)
114        * (+RW, +ZI)
115    }
116
117    ; Place variables in the section that should not be initialized during the
118    ; device startup.
119    RW_IRAM1 +0 UNINIT
120    {
121        * (.noinit)
122        * (.bss.noinit)
123    }
124
125    ; Application heap area (HEAP)
126    ARM_LIB_HEAP  +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE)
127    {
128    }
129
130    ; Stack region growing down
131    ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
132    {
133    }
134
135    ; Used for the digital signature of the secure application and the
136    ; Bootloader SDK application. The size of the section depends on the required
137    ; data size.
138    .cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256
139    {
140        * (.cy_app_signature)
141    }
142}
143
144
145
146; Supervisory flash: User data
147LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
148{
149    .cy_sflash_user_data +0
150    {
151        * (.cy_sflash_user_data)
152    }
153}
154
155; Supervisory flash: Normal Access Restrictions (NAR)
156LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
157{
158    .cy_sflash_nar +0
159    {
160        * (.cy_sflash_nar)
161    }
162}
163
164; Supervisory flash: Public Key
165LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
166{
167    .cy_sflash_public_key +0
168    {
169        * (.cy_sflash_public_key)
170    }
171}
172
173; Supervisory flash: Table of Content # 2
174LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
175{
176    .cy_toc_part2 +0
177    {
178        * (.cy_toc_part2)
179    }
180}
181
182; Supervisory flash: Table of Content # 2 Copy
183LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
184{
185    .cy_rtoc_part2 +0
186    {
187        * (.cy_rtoc_part2)
188    }
189}
190
191
192; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
193LR_EROM XIP_START XIP_SIZE
194{
195    cy_xip +0
196    {
197        * (.cy_xip)
198    }
199}
200
201
202; eFuse
203LR_EFUSE EFUSE_START EFUSE_SIZE
204{
205    .cy_efuse +0
206    {
207        * (.cy_efuse)
208    }
209}
210
211
212; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
213CYMETA 0x90500000
214{
215    .cymeta +0 { * (.cymeta) }
216}
217
218/* The following symbols used by the cymcuelftool. */
219/* Flash */
220#define __cy_memory_0_start 0x10000000
221#define __cy_memory_0_length  0x00040000
222#define __cy_memory_0_row_size 0x200
223
224
225/* Supervisory Flash */
226#define __cy_memory_2_start    0x16000000
227#define __cy_memory_2_length   0x8000
228#define __cy_memory_2_row_size 0x200
229
230/* XIP */
231#define __cy_memory_3_start    0x18000000
232#define __cy_memory_3_length   0x08000000
233#define __cy_memory_3_row_size 0x200
234
235/* eFuse */
236#define __cy_memory_4_start    0x90700000
237#define __cy_memory_4_length   0x100000
238#define __cy_memory_4_row_size 1
239
240
241/* [] END OF FILE */
242