1/*******************************************************************************
2* \file cyb06xxa_cm0plus.icf
3* \version 2.95.1
4*
5* Linker file for the IAR compiler.
6*
7* The main purpose of the linker script is to describe how the sections in the
8* input files should be mapped into the output file, and to control the memory
9* layout of the output file.
10*
11* \note The entry point is fixed and starts at 0x10000000. The valid application
12* image should be placed there.
13*
14* \note The linker files included with the PDL template projects must be generic
15* and handle all common use cases. Your project may not use every section
16* defined in the linker files. In that case you may see warnings during the
17* build process. In your project, you can simply comment out or remove the
18* relevant code in the linker file.
19*
20********************************************************************************
21* \copyright
22* Copyright 2016-2021 Cypress Semiconductor Corporation
23* SPDX-License-Identifier: Apache-2.0
24*
25* Licensed under the Apache License, Version 2.0 (the "License");
26* you may not use this file except in compliance with the License.
27* You may obtain a copy of the License at
28*
29*     http://www.apache.org/licenses/LICENSE-2.0
30*
31* Unless required by applicable law or agreed to in writing, software
32* distributed under the License is distributed on an "AS IS" BASIS,
33* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
34* See the License for the specific language governing permissions and
35* limitations under the License.
36*******************************************************************************/
37
38/*###ICF### Section handled by ICF editor, don't touch! ****/
39/*-Editor annotation file-*/
40/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */
41/*-Specials-*/
42define symbol __ICFEDIT_intvec_start__ = 0x00000000;
43
44/*-Sizes-*/
45if (!isdefinedsymbol(__STACK_SIZE)) {
46  define symbol __ICFEDIT_size_cstack__ = 0x1000;
47} else {
48  define symbol __ICFEDIT_size_cstack__ = __STACK_SIZE;
49}
50define symbol __ICFEDIT_size_proc_stack__ = 0x0;
51
52/* Defines the minimum heap size. The actual heap size will be expanded to the end of the stack region */
53if (!isdefinedsymbol(__HEAP_SIZE)) {
54    define symbol __ICFEDIT_size_heap__ = 0x0400;
55} else {
56  define symbol __ICFEDIT_size_heap__ = __HEAP_SIZE;
57}
58
59/* The symbols below define the location and size of blocks of memory in the target.
60 * Use these symbols to specify the memory regions available for allocation.
61 */
62
63/* The following symbols control RAM and flash memory allocation for the CM0+ core.
64 * You can change the memory allocation by editing RAM and Flash symbols.
65 * Your changes must be aligned with the corresponding symbols for CM4 core in 'xx_cm4_dual.icf',
66 * where 'xx' is the device group; for example, 'cyb06xx7_cm4_dual.icf'.
67 */
68/* RAM */
69define symbol __ICFEDIT_region_IRAM1_start__ = 0x080E0000;
70define symbol __ICFEDIT_region_IRAM1_end__   = 0x080EBFFF;
71
72/* Flash */
73define symbol __ICFEDIT_region_IROM1_start__ = 0x10000000;
74define symbol __ICFEDIT_region_IROM1_end__   = 0x1000FFFF;
75
76/* The following symbols define a 32K flash region used for EEPROM emulation.
77 * This region can also be used as the general purpose flash.
78 * You can assign sections to this memory region for only one of the cores.
79 * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
80 * Therefore, repurposing this memory region will prevent such middleware from operation.
81 */
82define symbol __ICFEDIT_region_IROM2_start__ = 0x14000000;
83define symbol __ICFEDIT_region_IROM2_end__   = 0x14007FFF;
84
85/* The following symbols define device specific memory regions and must not be changed. */
86/* Supervisory FLASH - User Data */
87define symbol __ICFEDIT_region_IROM3_start__ = 0x16000800;
88define symbol __ICFEDIT_region_IROM3_end__   = 0x16000FFF;
89
90/* Supervisory FLASH - Normal Access Restrictions (NAR) */
91define symbol __ICFEDIT_region_IROM4_start__ = 0x16001A00;
92define symbol __ICFEDIT_region_IROM4_end__   = 0x16001BFF;
93
94/* Supervisory FLASH - Public Key */
95define symbol __ICFEDIT_region_IROM5_start__ = 0x16005A00;
96define symbol __ICFEDIT_region_IROM5_end__   = 0x160065FF;
97
98/* Supervisory FLASH - Table of Content # 2 */
99define symbol __ICFEDIT_region_IROM6_start__ = 0x16007C00;
100define symbol __ICFEDIT_region_IROM6_end__   = 0x16007DFF;
101
102/* Supervisory FLASH - Table of Content # 2 Copy */
103define symbol __ICFEDIT_region_IROM7_start__ = 0x16007E00;
104define symbol __ICFEDIT_region_IROM7_end__   = 0x16007FFF;
105
106/* eFuse */
107define symbol __ICFEDIT_region_IROM8_start__ = 0x90700000;
108define symbol __ICFEDIT_region_IROM8_end__   = 0x907FFFFF;
109
110/* XIP */
111define symbol __ICFEDIT_region_EROM1_start__ = 0x18000000;
112define symbol __ICFEDIT_region_EROM1_end__   = 0x1FFFFFFF;
113
114define symbol __ICFEDIT_region_EROM2_start__ = 0x0;
115define symbol __ICFEDIT_region_EROM2_end__   = 0x0;
116define symbol __ICFEDIT_region_EROM3_start__ = 0x0;
117define symbol __ICFEDIT_region_EROM3_end__   = 0x0;
118
119
120define symbol __ICFEDIT_region_IRAM2_start__ = 0x08000000;
121define symbol __ICFEDIT_region_IRAM2_end__   = 0x080007FF;
122define symbol __ICFEDIT_region_ERAM1_start__ = 0x0;
123define symbol __ICFEDIT_region_ERAM1_end__   = 0x0;
124define symbol __ICFEDIT_region_ERAM2_start__ = 0x0;
125define symbol __ICFEDIT_region_ERAM2_end__   = 0x0;
126define symbol __ICFEDIT_region_ERAM3_start__ = 0x0;
127define symbol __ICFEDIT_region_ERAM3_end__   = 0x0;
128/**** End of ICF editor section. ###ICF###*/
129
130/* The size of the MCU boot header area at the start of FLASH */
131define symbol BOOT_HEADER_SIZE  = 0x400;
132
133
134define memory mem with size = 4G;
135define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__];
136define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__];
137define region IROM3_region = mem:[from __ICFEDIT_region_IROM3_start__ to __ICFEDIT_region_IROM3_end__];
138define region IROM4_region = mem:[from __ICFEDIT_region_IROM4_start__ to __ICFEDIT_region_IROM4_end__];
139define region IROM5_region = mem:[from __ICFEDIT_region_IROM5_start__ to __ICFEDIT_region_IROM5_end__];
140define region IROM6_region = mem:[from __ICFEDIT_region_IROM6_start__ to __ICFEDIT_region_IROM6_end__];
141define region IROM7_region = mem:[from __ICFEDIT_region_IROM7_start__ to __ICFEDIT_region_IROM7_end__];
142define region IROM8_region = mem:[from __ICFEDIT_region_IROM8_start__ to __ICFEDIT_region_IROM8_end__];
143define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__];
144define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__];
145define region IRAM2_region = mem:[from __ICFEDIT_region_IRAM2_start__ to __ICFEDIT_region_IRAM2_end__];
146
147define block CSTACK     with alignment = 8, size = __ICFEDIT_size_cstack__     { };
148define block PROC_STACK with alignment = 8, size = __ICFEDIT_size_proc_stack__ { };
149define block HEAP       with expanding size, alignment = 8, minimum size = __ICFEDIT_size_heap__ { };
150define block HSTACK {block HEAP, block PROC_STACK, last block CSTACK};
151define block RO     {first section .intvec, readonly};
152
153define block cy_xip { section .cy_xip };
154
155/*-Initializations-*/
156initialize by copy { readwrite };
157do not initialize  { section .noinit, section .intvec_ram };
158
159/*-Placement-*/
160
161/* Flash - Cortex-M0+ application */
162".cy_app_header" : place at start of IROM1_region  { section .cy_app_header };
163place at address (__ICFEDIT_region_IROM1_start__ + BOOT_HEADER_SIZE) { block RO };
164
165/* Emulated EEPROM Flash area */
166".cy_em_eeprom" : place at start of IROM2_region  { section .cy_em_eeprom };
167
168/* Supervisory Flash - User Data */
169".cy_sflash_user_data" : place at start of IROM3_region  { section .cy_sflash_user_data };
170
171/* Supervisory Flash - NAR */
172".cy_sflash_nar" : place at start of IROM4_region  { section .cy_sflash_nar };
173
174/* Supervisory Flash - Public Key */
175".cy_sflash_public_key" : place at start of IROM5_region  { section .cy_sflash_public_key };
176
177/* Supervisory Flash - TOC2 */
178".cy_toc_part2" : place at start of IROM6_region  { section .cy_toc_part2 };
179
180/* Supervisory Flash - RTOC2 */
181".cy_rtoc_part2" : place at start of IROM7_region  { section .cy_rtoc_part2 };
182
183/* eFuse */
184".cy_efuse" : place at start of IROM8_region  { section .cy_efuse };
185
186/* Execute in Place (XIP). See the smif driver documentation for details. */
187"cy_xip" : place at start of EROM1_region  { block cy_xip };
188
189/* RAM */
190place at start of IRAM1_region  { readwrite section .intvec_ram};
191place in          IRAM1_region  { readwrite };
192place at end   of IRAM1_region  { block HSTACK };
193
194/* Public RAM */
195place at start of IRAM2_region  { section .cy_sharedmem };
196
197/* These sections are used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. */
198".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta };
199
200
201keep {  section .cy_app_header,
202        section .cy_em_eeprom,
203        section .cy_sflash_user_data,
204        section .cy_sflash_nar,
205        section .cy_sflash_public_key,
206        section .cy_toc_part2,
207        section .cy_rtoc_part2,
208        section .cy_efuse,
209        section .cy_xip,
210        section .cymeta,
211         };
212
213
214/* The following symbols used by the cymcuelftool. */
215/* Flash */
216define exported symbol __cy_memory_0_start    = 0x10000000;
217define exported symbol __cy_memory_0_length   = 0x001D0000;
218define exported symbol __cy_memory_0_row_size = 0x200;
219
220/* Emulated EEPROM Flash area */
221define exported symbol __cy_memory_1_start    = 0x14000000;
222define exported symbol __cy_memory_1_length   = 0x8000;
223define exported symbol __cy_memory_1_row_size = 0x200;
224
225/* Supervisory Flash */
226define exported symbol __cy_memory_2_start    = 0x16000000;
227define exported symbol __cy_memory_2_length   = 0x8000;
228define exported symbol __cy_memory_2_row_size = 0x200;
229
230/* XIP */
231define exported symbol __cy_memory_3_start    = 0x18000000;
232define exported symbol __cy_memory_3_length   = 0x08000000;
233define exported symbol __cy_memory_3_row_size = 0x200;
234
235/* eFuse */
236define exported symbol __cy_memory_4_start    = 0x90700000;
237define exported symbol __cy_memory_4_length   = 0x100000;
238define exported symbol __cy_memory_4_row_size = 1;
239
240/* EOF */
241