1/*******************************************************************************
2* \file cy8c6xx4_cm0plus.icf
3* \version 2.95.1
4*
5* Linker file for the IAR compiler.
6*
7* The main purpose of the linker script is to describe how the sections in the
8* input files should be mapped into the output file, and to control the memory
9* layout of the output file.
10*
11* \note The entry point is fixed and starts at 0x10000000. The valid application
12* image should be placed there.
13*
14* \note The linker files included with the PDL template projects must be generic
15* and handle all common use cases. Your project may not use every section
16* defined in the linker files. In that case you may see warnings during the
17* build process. In your project, you can simply comment out or remove the
18* relevant code in the linker file.
19*
20********************************************************************************
21* \copyright
22* Copyright 2016-2021 Cypress Semiconductor Corporation
23* SPDX-License-Identifier: Apache-2.0
24*
25* Licensed under the Apache License, Version 2.0 (the "License");
26* you may not use this file except in compliance with the License.
27* You may obtain a copy of the License at
28*
29*     http://www.apache.org/licenses/LICENSE-2.0
30*
31* Unless required by applicable law or agreed to in writing, software
32* distributed under the License is distributed on an "AS IS" BASIS,
33* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
34* See the License for the specific language governing permissions and
35* limitations under the License.
36*******************************************************************************/
37
38/*###ICF### Section handled by ICF editor, don't touch! ****/
39/*-Editor annotation file-*/
40/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */
41/*-Specials-*/
42define symbol __ICFEDIT_intvec_start__ = 0x00000000;
43
44/*-Sizes-*/
45if (!isdefinedsymbol(__STACK_SIZE)) {
46  define symbol __ICFEDIT_size_cstack__ = 0x1000;
47} else {
48  define symbol __ICFEDIT_size_cstack__ = __STACK_SIZE;
49}
50define symbol __ICFEDIT_size_proc_stack__ = 0x0;
51
52/* Defines the minimum heap size. The actual heap size will be expanded to the end of the stack region */
53if (!isdefinedsymbol(__HEAP_SIZE)) {
54    define symbol __ICFEDIT_size_heap__ = 0x0400;
55} else {
56  define symbol __ICFEDIT_size_heap__ = __HEAP_SIZE;
57}
58
59/* The symbols below define the location and size of blocks of memory in the target.
60 * Use these symbols to specify the memory regions available for allocation.
61 */
62
63/* The following symbols control RAM and flash memory allocation for the CM0+ core.
64 * You can change the memory allocation by editing RAM and Flash symbols.
65 * Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
66 * Using this memory region for other purposes will lead to unexpected behavior.
67 * Your changes must be aligned with the corresponding symbols for CM4 core in 'xx_cm4_dual.icf',
68 * where 'xx' is the device group; for example, 'cy8c6xx7_cm4_dual.icf'.
69 */
70/* RAM */
71define symbol __ICFEDIT_region_IRAM1_start__ = 0x08000000;
72define symbol __ICFEDIT_region_IRAM1_end__   = 0x08001FFF;
73
74/* Flash */
75define symbol __ICFEDIT_region_IROM1_start__ = 0x10000000;
76define symbol __ICFEDIT_region_IROM1_end__   = 0x10001FFF;
77
78/* The following symbols define a 32K flash region used for EEPROM emulation.
79 * This region can also be used as the general purpose flash.
80 * You can assign sections to this memory region for only one of the cores.
81 * Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
82 * Therefore, repurposing this memory region will prevent such middleware from operation.
83 */
84define symbol __ICFEDIT_region_IROM2_start__ = 0x14000000;
85define symbol __ICFEDIT_region_IROM2_end__   = 0x14007FFF;
86
87/* The following symbols define device specific memory regions and must not be changed. */
88/* Supervisory FLASH - User Data */
89define symbol __ICFEDIT_region_IROM3_start__ = 0x16000800;
90define symbol __ICFEDIT_region_IROM3_end__   = 0x16000FFF;
91
92/* Supervisory FLASH - Normal Access Restrictions (NAR) */
93define symbol __ICFEDIT_region_IROM4_start__ = 0x16001A00;
94define symbol __ICFEDIT_region_IROM4_end__   = 0x16001BFF;
95
96/* Supervisory FLASH - Public Key */
97define symbol __ICFEDIT_region_IROM5_start__ = 0x16005A00;
98define symbol __ICFEDIT_region_IROM5_end__   = 0x160065FF;
99
100/* Supervisory FLASH - Table of Content # 2 */
101define symbol __ICFEDIT_region_IROM6_start__ = 0x16007C00;
102define symbol __ICFEDIT_region_IROM6_end__   = 0x16007DFF;
103
104/* Supervisory FLASH - Table of Content # 2 Copy */
105define symbol __ICFEDIT_region_IROM7_start__ = 0x16007E00;
106define symbol __ICFEDIT_region_IROM7_end__   = 0x16007FFF;
107
108/* eFuse */
109define symbol __ICFEDIT_region_IROM8_start__ = 0x90700000;
110define symbol __ICFEDIT_region_IROM8_end__   = 0x907FFFFF;
111
112/* XIP */
113define symbol __ICFEDIT_region_EROM1_start__ = 0x18000000;
114define symbol __ICFEDIT_region_EROM1_end__   = 0x1FFFFFFF;
115
116define symbol __ICFEDIT_region_EROM2_start__ = 0x0;
117define symbol __ICFEDIT_region_EROM2_end__   = 0x0;
118define symbol __ICFEDIT_region_EROM3_start__ = 0x0;
119define symbol __ICFEDIT_region_EROM3_end__   = 0x0;
120
121
122define symbol __ICFEDIT_region_IRAM2_start__ = 0x0;
123define symbol __ICFEDIT_region_IRAM2_end__   = 0x0;
124define symbol __ICFEDIT_region_ERAM1_start__ = 0x0;
125define symbol __ICFEDIT_region_ERAM1_end__   = 0x0;
126define symbol __ICFEDIT_region_ERAM2_start__ = 0x0;
127define symbol __ICFEDIT_region_ERAM2_end__   = 0x0;
128define symbol __ICFEDIT_region_ERAM3_start__ = 0x0;
129define symbol __ICFEDIT_region_ERAM3_end__   = 0x0;
130/**** End of ICF editor section. ###ICF###*/
131
132
133define memory mem with size = 4G;
134define region IROM1_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__];
135define region IROM2_region = mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__];
136define region IROM3_region = mem:[from __ICFEDIT_region_IROM3_start__ to __ICFEDIT_region_IROM3_end__];
137define region IROM4_region = mem:[from __ICFEDIT_region_IROM4_start__ to __ICFEDIT_region_IROM4_end__];
138define region IROM5_region = mem:[from __ICFEDIT_region_IROM5_start__ to __ICFEDIT_region_IROM5_end__];
139define region IROM6_region = mem:[from __ICFEDIT_region_IROM6_start__ to __ICFEDIT_region_IROM6_end__];
140define region IROM7_region = mem:[from __ICFEDIT_region_IROM7_start__ to __ICFEDIT_region_IROM7_end__];
141define region IROM8_region = mem:[from __ICFEDIT_region_IROM8_start__ to __ICFEDIT_region_IROM8_end__];
142define region EROM1_region = mem:[from __ICFEDIT_region_EROM1_start__ to __ICFEDIT_region_EROM1_end__];
143define region IRAM1_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__];
144
145/* Public RAM
146 * This is an unprotected public RAM region, with the placed .cy_sharedmem section.
147 * This region is used to place objects that require full access from both cores.
148 * Uncomment the following lines, define region size, and uncomment the placement of
149 * .cy_sharedmem section below in the IRAM2_region. Also define the __ICFEDIT_region_IRAM2_start__
150 *  and __ICFEDIT_region_IRAM2_end__ to place the IRAM2_region.
151 */
152/*
153define region IRAM2_region = mem:[from __ICFEDIT_region_IRAM2_start__ to __ICFEDIT_region_IRAM2_end__];
154*/
155
156define block CSTACK     with alignment = 8, size = __ICFEDIT_size_cstack__     { };
157define block PROC_STACK with alignment = 8, size = __ICFEDIT_size_proc_stack__ { };
158define block HEAP       with expanding size, alignment = 8, minimum size = __ICFEDIT_size_heap__ { };
159define block HSTACK {block HEAP, block PROC_STACK, last block CSTACK};
160define block RO     {first section .intvec, readonly};
161
162define block cy_xip { section .cy_xip };
163
164/*-Initializations-*/
165initialize by copy { readwrite };
166do not initialize  { section .noinit, section .intvec_ram };
167
168/*-Placement-*/
169
170/* Flash - Cortex-M0+ application */
171".cy_app_header" : place at start of IROM1_region  { section .cy_app_header };
172place in          IROM1_region  { block RO };
173
174
175/* Supervisory Flash - User Data */
176".cy_sflash_user_data" : place at start of IROM3_region  { section .cy_sflash_user_data };
177
178/* Supervisory Flash - NAR */
179".cy_sflash_nar" : place at start of IROM4_region  { section .cy_sflash_nar };
180
181/* Supervisory Flash - Public Key */
182".cy_sflash_public_key" : place at start of IROM5_region  { section .cy_sflash_public_key };
183
184/* Supervisory Flash - TOC2 */
185".cy_toc_part2" : place at start of IROM6_region  { section .cy_toc_part2 };
186
187/* Supervisory Flash - RTOC2 */
188".cy_rtoc_part2" : place at start of IROM7_region  { section .cy_rtoc_part2 };
189
190/* eFuse */
191".cy_efuse" : place at start of IROM8_region  { section .cy_efuse };
192
193/* Execute in Place (XIP). See the smif driver documentation for details. */
194"cy_xip" : place at start of EROM1_region  { block cy_xip };
195
196/* RAM */
197place at start of IRAM1_region  { readwrite section .intvec_ram};
198place in          IRAM1_region  { readwrite };
199place at end   of IRAM1_region  { block HSTACK };
200
201/* Public RAM
202 *To use unprotected public RAM, uncomment the following .cy_sharedmem section placement.
203 */
204/*
205place at start of IRAM2_region  { section .cy_sharedmem };
206*/
207
208/* These sections are used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage. */
209".cymeta" : place at address mem : 0x90500000 { readonly section .cymeta };
210
211
212keep {  section .cy_app_header,
213        section .cy_sflash_user_data,
214        section .cy_sflash_nar,
215        section .cy_sflash_public_key,
216        section .cy_toc_part2,
217        section .cy_rtoc_part2,
218        section .cy_efuse,
219        section .cy_xip,
220        section .cymeta,
221         };
222
223
224/* The following symbols used by the cymcuelftool. */
225/* Flash */
226define exported symbol __cy_memory_0_start    = 0x10000000;
227define exported symbol __cy_memory_0_length   = 0x00040000;
228define exported symbol __cy_memory_0_row_size = 0x200;
229
230
231/* Supervisory Flash */
232define exported symbol __cy_memory_2_start    = 0x16000000;
233define exported symbol __cy_memory_2_length   = 0x8000;
234define exported symbol __cy_memory_2_row_size = 0x200;
235
236/* XIP */
237define exported symbol __cy_memory_3_start    = 0x18000000;
238define exported symbol __cy_memory_3_length   = 0x08000000;
239define exported symbol __cy_memory_3_row_size = 0x200;
240
241/* eFuse */
242define exported symbol __cy_memory_4_start    = 0x90700000;
243define exported symbol __cy_memory_4_length   = 0x100000;
244define exported symbol __cy_memory_4_row_size = 1;
245
246/* EOF */
247