1#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m0
2; The first line specifies a preprocessor command that the linker invokes
3; to pass a scatter file through a C preprocessor.
4
5;*******************************************************************************
6;* \file cyb06xx5_cm0plus.sct
7;* \version 2.95.1
8;*
9;* Linker file for the ARMCC.
10;*
11;* The main purpose of the linker script is to describe how the sections in the
12;* input files should be mapped into the output file, and to control the memory
13;* layout of the output file.
14;*
15;* \note The entry point location is fixed and starts at 0x10000000. The valid
16;* application image should be placed there.
17;*
18;* \note The linker files included with the PDL template projects must be
19;* generic and handle all common use cases. Your project may not use every
20;* section defined in the linker files. In that case you may see the warnings
21;* during the build process: L6314W (no section matches pattern) and/or L6329W
22;* (pattern only matches removed unused sections). In your project, you can
23;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
24;* the linker, simply comment out or remove the relevant code in the linker
25;* file.
26;*
27;*******************************************************************************
28;* \copyright
29;* Copyright 2016-2021 Cypress Semiconductor Corporation
30;* SPDX-License-Identifier: Apache-2.0
31;*
32;* Licensed under the Apache License, Version 2.0 (the "License");
33;* you may not use this file except in compliance with the License.
34;* You may obtain a copy of the License at
35;*
36;*     http://www.apache.org/licenses/LICENSE-2.0
37;*
38;* Unless required by applicable law or agreed to in writing, software
39;* distributed under the License is distributed on an "AS IS" BASIS,
40;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
41;* See the License for the specific language governing permissions and
42;* limitations under the License.
43;******************************************************************************/
44
45; The defines below describe the location and size of blocks of memory in the target.
46; Use these defines to specify the memory regions available for allocation.
47
48; The following defines control RAM and flash memory allocation for the CM0+ core.
49; You can change the memory allocation by editing the RAM and Flash defines.
50; Your changes must be aligned with the corresponding defines for the CM4 core in 'xx_cm4_dual.scat',
51; where 'xx' is the device group; for example, 'cyb06xx7_cm4_dual.scat'.
52; RAM
53#define RAM_START               0x08020000
54#define RAM_SIZE                0x0000C000
55; Flash
56#define FLASH_START             0x10000000
57#define FLASH_SIZE              0x00010000
58
59; The size of the stack section at the end of CM0+ SRAM
60#define STACK_SIZE              0x00001000
61
62; The size of the MCU boot header area at the start of FLASH
63#define BOOT_HEADER_SIZE        0x00000400
64
65
66; The following defines describe device specific memory regions and must not be changed.
67; Supervisory flash: User data
68#define SFLASH_USER_DATA_START  0x16000800
69#define SFLASH_USER_DATA_SIZE   0x00000800
70
71; Supervisory flash: Normal Access Restrictions (NAR)
72#define SFLASH_NAR_START        0x16001A00
73#define SFLASH_NAR_SIZE         0x00000200
74
75; Supervisory flash: Public Key
76#define SFLASH_PUBLIC_KEY_START 0x16005A00
77#define SFLASH_PUBLIC_KEY_SIZE  0x00000C00
78
79; Supervisory flash: Table of Content # 2
80#define SFLASH_TOC_2_START      0x16007C00
81#define SFLASH_TOC_2_SIZE       0x00000200
82
83; Supervisory flash: Table of Content # 2 Copy
84#define SFLASH_RTOC_2_START     0x16007E00
85#define SFLASH_RTOC_2_SIZE      0x00000200
86
87; External memory
88#define XIP_START               0x18000000
89#define XIP_SIZE                0x08000000
90
91; eFuse
92#define EFUSE_START             0x90700000
93#define EFUSE_SIZE              0x100000
94
95; Public RAM
96#define PUBLIC_RAM_SIZE         0x800
97#define PUBLIC_RAM_START        0x08000000
98
99; Cortex-M0+ application flash area
100LR_IROM1 (FLASH_START + BOOT_HEADER_SIZE) (FLASH_SIZE - BOOT_HEADER_SIZE)
101{
102    ER_FLASH_VECTORS +0
103    {
104        * (RESET, +FIRST)
105    }
106
107    ER_FLASH_CODE +0 FIXED
108    {
109        * (InRoot$$Sections)
110        * (+RO)
111    }
112
113    ER_RAM_VECTORS RAM_START UNINIT
114    {
115        * (RESET_RAM, +FIRST)
116    }
117
118    RW_RAM_DATA +0
119    {
120        * (.cy_ramfunc)
121        * (+RW, +ZI)
122    }
123
124    ; Place variables in the section that should not be initialized during the
125    ; device startup.
126    RW_IRAM1 +0 UNINIT
127    {
128        * (.noinit)
129        * (.bss.noinit)
130    }
131
132    RW_IRAM2 PUBLIC_RAM_START UNINIT
133    {
134        * (.cy_sharedmem)
135    }
136
137    ; Application heap area (HEAP)
138    ARM_LIB_HEAP  +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-AlignExpr(ImageLimit(RW_IRAM1), 8)
139    {
140    }
141
142    ; Stack region growing down
143    ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
144    {
145    }
146}
147
148
149
150; Supervisory flash: User data
151LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
152{
153    .cy_sflash_user_data +0
154    {
155        * (.cy_sflash_user_data)
156    }
157}
158
159; Supervisory flash: Normal Access Restrictions (NAR)
160LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
161{
162    .cy_sflash_nar +0
163    {
164        * (.cy_sflash_nar)
165    }
166}
167
168; Supervisory flash: Public Key
169LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
170{
171    .cy_sflash_public_key +0
172    {
173        * (.cy_sflash_public_key)
174    }
175}
176
177; Supervisory flash: Table of Content # 2
178LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
179{
180    .cy_toc_part2 +0
181    {
182        * (.cy_toc_part2)
183    }
184}
185
186; Supervisory flash: Table of Content # 2 Copy
187LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
188{
189    .cy_rtoc_part2 +0
190    {
191        * (.cy_rtoc_part2)
192    }
193}
194
195
196; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
197LR_EROM XIP_START XIP_SIZE
198{
199    cy_xip +0
200    {
201        * (.cy_xip)
202    }
203}
204
205
206; eFuse
207LR_EFUSE EFUSE_START EFUSE_SIZE
208{
209    .cy_efuse +0
210    {
211        * (.cy_efuse)
212    }
213}
214
215
216; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
217CYMETA 0x90500000
218{
219    .cymeta +0 { * (.cymeta) }
220}
221
222/* The following symbols used by the cymcuelftool. */
223/* Flash */
224#define __cy_memory_0_start 0x10000000
225#define __cy_memory_0_length  0x00070000
226#define __cy_memory_0_row_size 0x200
227
228
229/* Supervisory Flash */
230#define __cy_memory_2_start    0x16000000
231#define __cy_memory_2_length   0x8000
232#define __cy_memory_2_row_size 0x200
233
234/* XIP */
235#define __cy_memory_3_start    0x18000000
236#define __cy_memory_3_length   0x08000000
237#define __cy_memory_3_row_size 0x200
238
239/* eFuse */
240#define __cy_memory_4_start    0x90700000
241#define __cy_memory_4_length   0x100000
242#define __cy_memory_4_row_size 1
243
244
245/* [] END OF FILE */
246