.shstrtab .strtab .symtab A0 A1 A2 .debug_abbrev .debug_aranges .debug_frame .debug_info .debug_line .debug_loc .debug_macinfo .debug_pubnames .debug_ranges .debug_types .iar.debug_frame .iar.debug_line .comment .iar.rtmodel .ARM.attributes
$m $d $t $d.16 $d.32 $d.8 C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\src\algo\algo_base.c ??Cy_GPIO_Port_Backup_0 ??DataTable3 ??DataTable3_1 ??DataTable3_2 ??DataTable3_4 ??DataTable3_5 ??DataTable3_6 ??DataTable3_7 Cy_GPIO_Port_Backup .data8 .text9 .text_5 .text_6 C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\src\algo\algo_common.c ??Count_0 ??Count_1 ??NumToStr_0 ??NumToStr_1 .text8 .text_3 C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\src\algo\algo_smif.c ??DataTable11 ??DataTable12 ??DataTable12_1 ??DataTable12_2 ??DataTable16 ??DataTable16_1 ??DataTable16_2 ??DataTable21 ??DataTable21_1 ??DataTable21_2 ??DataTable21_3 ??DataTable21_4 ??DataTable21_5 ??DataTable4 ??DataTable4_1 ??DataTable4_10 ??DataTable4_11 ??DataTable4_12 ??DataTable4_13 ??DataTable4_14 ??DataTable4_15 ??DataTable4_16 ??DataTable4_17 ??DataTable4_18 ??DataTable4_19 ??DataTable4_2 ??DataTable4_20 ??DataTable4_21 ??DataTable4_22 ??DataTable4_23 ??DataTable4_24 ??DataTable4_25 ??DataTable4_26 ??DataTable4_27 ??DataTable4_28 ??DataTable4_29 ??DataTable4_3 ??DataTable4_30 ??DataTable4_31 ??DataTable4_32 ??DataTable4_33 ??DataTable4_34 ??DataTable4_35 ??DataTable4_36 ??DataTable4_37 ??DataTable4_38 ??DataTable4_39 ??DataTable4_4 ??DataTable4_40 ??DataTable4_41 ??DataTable4_42 ??DataTable4_43 ??DataTable4_44 ??DataTable4_45 ??DataTable4_46 ??DataTable4_47 ??DataTable4_48 ??DataTable4_49 ??DataTable4_5 ??DataTable4_6 ??DataTable4_7 ??DataTable4_8 ??DataTable4_9 ??DataTable5 ??DataTable5_1 ??DataTable5_10 ??DataTable5_11 ??DataTable5_12 ??DataTable5_13 ??DataTable5_14 ??DataTable5_15 ??DataTable5_16 ??DataTable5_17 ??DataTable5_18 ??DataTable5_19 ??DataTable5_2 ??DataTable5_20 ??DataTable5_21 ??DataTable5_22 ??DataTable5_23 ??DataTable5_24 ??DataTable5_25 ??DataTable5_26 ??DataTable5_27 ??DataTable5_28 ??DataTable5_29 ??DataTable5_3 ??DataTable5_30 ??DataTable5_31 ??DataTable5_32 ??DataTable5_4 ??DataTable5_5 ??DataTable5_6 ??DataTable5_7 ??DataTable5_8 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??SMIF_PrepareConfigs_7 ??SMIF_Program_0 ??SMIF_TuneConfigs_0 ??SMIF_TuneConfigs_1 ??SMIF_TuneConfigs_2 ??SMIF_UnInit_0 ??SMIF_UnInit_1 ?_2 SMIF_ConfigMMIO SMIF_ConfigXIP SMIF_State SMIF_context .text11 .text_57 .text_91 .text_109 .text_114 .text_130 .text_133 .text_140 .text_141 .text_148 .text_153 .text_155 C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\src\algo\algo_target_syscall.c C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\src\algo\algo_xflash.c C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\src\pdl\drivers\source\cy_gpio.c ??Cy_GPIO_Pin_Init_0 ??Cy_GPIO_Port_Init_0 ??Cy_GPIO_SetHSIOM_0 ??Cy_GPIO_Write_0 .text_8 .text_12 .text_18 .text_20 .text_42 .text_46 C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\src\pdl\drivers\source\cy_smif.c ??Cy_SMIF_Init_0 ??Cy_SMIF_PackBytesArray_0 ??Cy_SMIF_ReceiveDataBlocking_Ext_0 ??Cy_SMIF_ReceiveDataBlocking_Ext_1 ??Cy_SMIF_ReceiveDataBlocking_Ext_10 ??Cy_SMIF_ReceiveDataBlocking_Ext_11 ??Cy_SMIF_ReceiveDataBlocking_Ext_12 ??Cy_SMIF_ReceiveDataBlocking_Ext_13 ??Cy_SMIF_ReceiveDataBlocking_Ext_14 ??Cy_SMIF_ReceiveDataBlocking_Ext_15 ??Cy_SMIF_ReceiveDataBlocking_Ext_16 ??Cy_SMIF_ReceiveDataBlocking_Ext_17 ??Cy_SMIF_ReceiveDataBlocking_Ext_18 ??Cy_SMIF_ReceiveDataBlocking_Ext_19 ??Cy_SMIF_ReceiveDataBlocking_Ext_2 ??Cy_SMIF_ReceiveDataBlocking_Ext_20 ??Cy_SMIF_ReceiveDataBlocking_Ext_21 ??Cy_SMIF_ReceiveDataBlocking_Ext_22 ??Cy_SMIF_ReceiveDataBlocking_Ext_3 ??Cy_SMIF_ReceiveDataBlocking_Ext_4 ??Cy_SMIF_ReceiveDataBlocking_Ext_5 ??Cy_SMIF_ReceiveDataBlocking_Ext_6 ??Cy_SMIF_ReceiveDataBlocking_Ext_7 ??Cy_SMIF_ReceiveDataBlocking_Ext_8 ??Cy_SMIF_ReceiveDataBlocking_Ext_9 ??Cy_SMIF_SendDummyCycles_Ext_0 ??Cy_SMIF_SetDataSelect_0 ??Cy_SMIF_SetDataSelect_1 ??Cy_SMIF_SetDataSelect_2 ??Cy_SMIF_SetDataSelect_3 ??Cy_SMIF_SetDataSelect_4 ??Cy_SMIF_SetMode_0 ??Cy_SMIF_SetMode_1 ??Cy_SMIF_SetMode_2 ??Cy_SMIF_SetMode_3 ??Cy_SMIF_TimeoutRun_0 ??Cy_SMIF_TimeoutRun_1 ??Cy_SMIF_TransmitCommand_Ext_0 ??Cy_SMIF_TransmitCommand_Ext_1 ??Cy_SMIF_TransmitCommand_Ext_10 ??Cy_SMIF_TransmitCommand_Ext_11 ??Cy_SMIF_TransmitCommand_Ext_12 ??Cy_SMIF_TransmitCommand_Ext_13 ??Cy_SMIF_TransmitCommand_Ext_14 ??Cy_SMIF_TransmitCommand_Ext_15 ??Cy_SMIF_TransmitCommand_Ext_16 ??Cy_SMIF_TransmitCommand_Ext_17 ??Cy_SMIF_TransmitCommand_Ext_18 ??Cy_SMIF_TransmitCommand_Ext_19 ??Cy_SMIF_TransmitCommand_Ext_2 ??Cy_SMIF_TransmitCommand_Ext_3 ??Cy_SMIF_TransmitCommand_Ext_4 ??Cy_SMIF_TransmitCommand_Ext_5 ??Cy_SMIF_TransmitCommand_Ext_6 ??Cy_SMIF_TransmitCommand_Ext_7 ??Cy_SMIF_TransmitCommand_Ext_8 ??Cy_SMIF_TransmitCommand_Ext_9 ??Cy_SMIF_TransmitDataBlocking_Ext_0 ??Cy_SMIF_TransmitDataBlocking_Ext_1 ??Cy_SMIF_TransmitDataBlocking_Ext_10 ??Cy_SMIF_TransmitDataBlocking_Ext_11 ??Cy_SMIF_TransmitDataBlocking_Ext_12 ??Cy_SMIF_TransmitDataBlocking_Ext_13 ??Cy_SMIF_TransmitDataBlocking_Ext_14 ??Cy_SMIF_TransmitDataBlocking_Ext_15 ??Cy_SMIF_TransmitDataBlocking_Ext_16 ??Cy_SMIF_TransmitDataBlocking_Ext_17 ??Cy_SMIF_TransmitDataBlocking_Ext_18 ??Cy_SMIF_TransmitDataBlocking_Ext_19 ??Cy_SMIF_TransmitDataBlocking_Ext_2 ??Cy_SMIF_TransmitDataBlocking_Ext_20 ??Cy_SMIF_TransmitDataBlocking_Ext_21 ??Cy_SMIF_TransmitDataBlocking_Ext_22 ??Cy_SMIF_TransmitDataBlocking_Ext_3 ??Cy_SMIF_TransmitDataBlocking_Ext_4 ??Cy_SMIF_TransmitDataBlocking_Ext_5 ??Cy_SMIF_TransmitDataBlocking_Ext_6 ??Cy_SMIF_TransmitDataBlocking_Ext_7 ??Cy_SMIF_TransmitDataBlocking_Ext_8 ??Cy_SMIF_TransmitDataBlocking_Ext_9 ??Cy_SMIF_UnPackByteArray_0 ??DataTable14 Cy_SMIF_PackBytesArray Cy_SMIF_TimeoutRun Cy_SMIF_UnPackByteArray .text_4 .text_7 .text_9 .text_13 .text_15 .text_17 .text_21 .text_25 .text_30 .text_31 C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\src\pdl\drivers\source\cy_smif_memslot.c ??Cy_SMIF_MemCmdChipErase_0 ??Cy_SMIF_MemCmdReadStatus_0 ??Cy_SMIF_MemCmdSectorErase_0 ??Cy_SMIF_MemCmdSectorErase_1 ??Cy_SMIF_MemCmdSectorErase_2 ??Cy_SMIF_MemCmdSectorErase_3 ??Cy_SMIF_MemCmdSectorErase_4 ??Cy_SMIF_MemCmdSectorErase_5 ??Cy_SMIF_MemCmdSectorErase_6 ??Cy_SMIF_MemCmdWriteStatus_0 ??Cy_SMIF_MemCmdWriteStatus_1 ??Cy_SMIF_MemCmdWriteStatus_2 ??Cy_SMIF_MemEraseChip_0 ??Cy_SMIF_MemEraseSector_0 ??Cy_SMIF_MemEraseSector_1 ??Cy_SMIF_MemEraseSector_10 ??Cy_SMIF_MemEraseSector_11 ??Cy_SMIF_MemEraseSector_12 ??Cy_SMIF_MemEraseSector_13 ??Cy_SMIF_MemEraseSector_2 ??Cy_SMIF_MemEraseSector_3 ??Cy_SMIF_MemEraseSector_4 ??Cy_SMIF_MemEraseSector_5 ??Cy_SMIF_MemEraseSector_6 ??Cy_SMIF_MemEraseSector_7 ??Cy_SMIF_MemEraseSector_8 ??Cy_SMIF_MemEraseSector_9 ??Cy_SMIF_MemInit_0 ??Cy_SMIF_MemInit_1 ??Cy_SMIF_MemInit_10 ??Cy_SMIF_MemInit_11 ??Cy_SMIF_MemInit_12 ??Cy_SMIF_MemInit_13 ??Cy_SMIF_MemInit_14 ??Cy_SMIF_MemInit_15 ??Cy_SMIF_MemInit_16 ??Cy_SMIF_MemInit_17 ??Cy_SMIF_MemInit_18 ??Cy_SMIF_MemInit_19 ??Cy_SMIF_MemInit_2 ??Cy_SMIF_MemInit_20 ??Cy_SMIF_MemInit_21 ??Cy_SMIF_MemInit_22 ??Cy_SMIF_MemInit_23 ??Cy_SMIF_MemInit_24 ??Cy_SMIF_MemInit_25 ??Cy_SMIF_MemInit_26 ??Cy_SMIF_MemInit_27 ??Cy_SMIF_MemInit_28 ??Cy_SMIF_MemInit_29 ??Cy_SMIF_MemInit_3 ??Cy_SMIF_MemInit_30 ??Cy_SMIF_MemInit_31 ??Cy_SMIF_MemInit_32 ??Cy_SMIF_MemInit_33 ??Cy_SMIF_MemInit_34 ??Cy_SMIF_MemInit_35 ??Cy_SMIF_MemInit_36 ??Cy_SMIF_MemInit_37 ??Cy_SMIF_MemInit_38 ??Cy_SMIF_MemInit_39 ??Cy_SMIF_MemInit_4 ??Cy_SMIF_MemInit_40 ??Cy_SMIF_MemInit_41 ??Cy_SMIF_MemInit_5 ??Cy_SMIF_MemInit_6 ??Cy_SMIF_MemInit_7 ??Cy_SMIF_MemInit_8 ??Cy_SMIF_MemInit_9 ??Cy_SMIF_MemIsBusy_0 ??Cy_SMIF_MemIsBusy_1 ??Cy_SMIF_MemIsBusy_2 ??Cy_SMIF_MemIsBusy_3 ??Cy_SMIF_MemIsBusy_4 ??Cy_SMIF_MemIsBusy_5 ??Cy_SMIF_MemIsBusy_6 ??Cy_SMIF_MemIsBusy_7 ??Cy_SMIF_MemIsReady_0 ??Cy_SMIF_MemIsReady_1 ??Cy_SMIF_MemIsReady_10 ??Cy_SMIF_MemIsReady_11 ??Cy_SMIF_MemIsReady_12 ??Cy_SMIF_MemIsReady_13 ??Cy_SMIF_MemIsReady_2 ??Cy_SMIF_MemIsReady_3 ??Cy_SMIF_MemIsReady_4 ??Cy_SMIF_MemIsReady_5 ??Cy_SMIF_MemIsReady_6 ??Cy_SMIF_MemIsReady_7 ??Cy_SMIF_MemIsReady_8 ??Cy_SMIF_MemIsReady_9 ??Cy_SMIF_MemLocateHybridRegion_0 ??Cy_SMIF_MemLocateHybridRegion_1 ??Cy_SMIF_MemLocateHybridRegion_2 ??Cy_SMIF_MemQuadEnable_0 ??Cy_SMIF_MemQuadEnable_1 ??Cy_SMIF_MemQuadEnable_2 ??Cy_SMIF_MemQuadEnable_3 ??Cy_SMIF_MemQuadEnable_4 ??Cy_SMIF_MemQuadEnable_5 ??Cy_SMIF_MemQuadEnable_6 ??Cy_SMIF_MemQuadEnable_7 ??Cy_SMIF_MemWrite_0 ??Cy_SMIF_MemWrite_1 ??Cy_SMIF_MemWrite_10 ??Cy_SMIF_MemWrite_11 ??Cy_SMIF_MemWrite_12 ??Cy_SMIF_MemWrite_2 ??Cy_SMIF_MemWrite_3 ??Cy_SMIF_MemWrite_4 ??Cy_SMIF_MemWrite_5 ??Cy_SMIF_MemWrite_6 ??Cy_SMIF_MemWrite_7 ??Cy_SMIF_MemWrite_8 ??Cy_SMIF_MemWrite_9 ??DataTable10 ??DataTable10_1 ??DataTable13 ??DataTable13_1 ??Subroutine0_0 ??Subroutine0_1 ??Subroutine0_2 ??ValueToByteArray_0 ?Subroutine0 ValueToByteArray .text_16 .text_22 .text_26 .text_35 .text_37 C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\src\pdl\drivers\source\cy_smif_sfdp.c ??Cy_SMIF_MemInitSfdpMode_0 ??Cy_SMIF_MemInitSfdpMode_1 ??Cy_SMIF_MemInitSfdpMode_10 ??Cy_SMIF_MemInitSfdpMode_100 ??Cy_SMIF_MemInitSfdpMode_101 ??Cy_SMIF_MemInitSfdpMode_102 ??Cy_SMIF_MemInitSfdpMode_103 ??Cy_SMIF_MemInitSfdpMode_104 ??Cy_SMIF_MemInitSfdpMode_105 ??Cy_SMIF_MemInitSfdpMode_106 ??Cy_SMIF_MemInitSfdpMode_107 ??Cy_SMIF_MemInitSfdpMode_108 ??Cy_SMIF_MemInitSfdpMode_109 ??Cy_SMIF_MemInitSfdpMode_11 ??Cy_SMIF_MemInitSfdpMode_110 ??Cy_SMIF_MemInitSfdpMode_111 ??Cy_SMIF_MemInitSfdpMode_112 ??Cy_SMIF_MemInitSfdpMode_113 ??Cy_SMIF_MemInitSfdpMode_114 ??Cy_SMIF_MemInitSfdpMode_115 ??Cy_SMIF_MemInitSfdpMode_116 ??Cy_SMIF_MemInitSfdpMode_117 ??Cy_SMIF_MemInitSfdpMode_118 ??Cy_SMIF_MemInitSfdpMode_119 ??Cy_SMIF_MemInitSfdpMode_12 ??Cy_SMIF_MemInitSfdpMode_120 ??Cy_SMIF_MemInitSfdpMode_121 ??Cy_SMIF_MemInitSfdpMode_122 ??Cy_SMIF_MemInitSfdpMode_123 ??Cy_SMIF_MemInitSfdpMode_124 ??Cy_SMIF_MemInitSfdpMode_125 ??Cy_SMIF_MemInitSfdpMode_126 ??Cy_SMIF_MemInitSfdpMode_127 ??Cy_SMIF_MemInitSfdpMode_128 ??Cy_SMIF_MemInitSfdpMode_129 ??Cy_SMIF_MemInitSfdpMode_13 ??Cy_SMIF_MemInitSfdpMode_130 ??Cy_SMIF_MemInitSfdpMode_131 ??Cy_SMIF_MemInitSfdpMode_132 ??Cy_SMIF_MemInitSfdpMode_133 ??Cy_SMIF_MemInitSfdpMode_134 ??Cy_SMIF_MemInitSfdpMode_135 ??Cy_SMIF_MemInitSfdpMode_136 ??Cy_SMIF_MemInitSfdpMode_137 ??Cy_SMIF_MemInitSfdpMode_138 ??Cy_SMIF_MemInitSfdpMode_139 ??Cy_SMIF_MemInitSfdpMode_14 ??Cy_SMIF_MemInitSfdpMode_140 ??Cy_SMIF_MemInitSfdpMode_141 ??Cy_SMIF_MemInitSfdpMode_142 ??Cy_SMIF_MemInitSfdpMode_143 ??Cy_SMIF_MemInitSfdpMode_144 ??Cy_SMIF_MemInitSfdpMode_145 ??Cy_SMIF_MemInitSfdpMode_146 ??Cy_SMIF_MemInitSfdpMode_147 ??Cy_SMIF_MemInitSfdpMode_148 ??Cy_SMIF_MemInitSfdpMode_149 ??Cy_SMIF_MemInitSfdpMode_15 ??Cy_SMIF_MemInitSfdpMode_150 ??Cy_SMIF_MemInitSfdpMode_151 ??Cy_SMIF_MemInitSfdpMode_152 ??Cy_SMIF_MemInitSfdpMode_153 ??Cy_SMIF_MemInitSfdpMode_154 ??Cy_SMIF_MemInitSfdpMode_155 ??Cy_SMIF_MemInitSfdpMode_156 ??Cy_SMIF_MemInitSfdpMode_157 ??Cy_SMIF_MemInitSfdpMode_158 ??Cy_SMIF_MemInitSfdpMode_159 ??Cy_SMIF_MemInitSfdpMode_16 ??Cy_SMIF_MemInitSfdpMode_160 ??Cy_SMIF_MemInitSfdpMode_161 ??Cy_SMIF_MemInitSfdpMode_162 ??Cy_SMIF_MemInitSfdpMode_163 ??Cy_SMIF_MemInitSfdpMode_17 ??Cy_SMIF_MemInitSfdpMode_18 ??Cy_SMIF_MemInitSfdpMode_19 ??Cy_SMIF_MemInitSfdpMode_2 ??Cy_SMIF_MemInitSfdpMode_20 ??Cy_SMIF_MemInitSfdpMode_21 ??Cy_SMIF_MemInitSfdpMode_22 ??Cy_SMIF_MemInitSfdpMode_23 ??Cy_SMIF_MemInitSfdpMode_24 ??Cy_SMIF_MemInitSfdpMode_25 ??Cy_SMIF_MemInitSfdpMode_26 ??Cy_SMIF_MemInitSfdpMode_27 ??Cy_SMIF_MemInitSfdpMode_28 ??Cy_SMIF_MemInitSfdpMode_29 ??Cy_SMIF_MemInitSfdpMode_3 ??Cy_SMIF_MemInitSfdpMode_30 ??Cy_SMIF_MemInitSfdpMode_31 ??Cy_SMIF_MemInitSfdpMode_32 ??Cy_SMIF_MemInitSfdpMode_33 ??Cy_SMIF_MemInitSfdpMode_34 ??Cy_SMIF_MemInitSfdpMode_35 ??Cy_SMIF_MemInitSfdpMode_36 ??Cy_SMIF_MemInitSfdpMode_37 ??Cy_SMIF_MemInitSfdpMode_38 ??Cy_SMIF_MemInitSfdpMode_39 ??Cy_SMIF_MemInitSfdpMode_4 ??Cy_SMIF_MemInitSfdpMode_40 ??Cy_SMIF_MemInitSfdpMode_41 ??Cy_SMIF_MemInitSfdpMode_42 ??Cy_SMIF_MemInitSfdpMode_43 ??Cy_SMIF_MemInitSfdpMode_44 ??Cy_SMIF_MemInitSfdpMode_45 ??Cy_SMIF_MemInitSfdpMode_46 ??Cy_SMIF_MemInitSfdpMode_47 ??Cy_SMIF_MemInitSfdpMode_48 ??Cy_SMIF_MemInitSfdpMode_49 ??Cy_SMIF_MemInitSfdpMode_5 ??Cy_SMIF_MemInitSfdpMode_50 ??Cy_SMIF_MemInitSfdpMode_51 ??Cy_SMIF_MemInitSfdpMode_52 ??Cy_SMIF_MemInitSfdpMode_53 ??Cy_SMIF_MemInitSfdpMode_54 ??Cy_SMIF_MemInitSfdpMode_55 ??Cy_SMIF_MemInitSfdpMode_56 ??Cy_SMIF_MemInitSfdpMode_57 ??Cy_SMIF_MemInitSfdpMode_58 ??Cy_SMIF_MemInitSfdpMode_59 ??Cy_SMIF_MemInitSfdpMode_6 ??Cy_SMIF_MemInitSfdpMode_60 ??Cy_SMIF_MemInitSfdpMode_61 ??Cy_SMIF_MemInitSfdpMode_62 ??Cy_SMIF_MemInitSfdpMode_63 ??Cy_SMIF_MemInitSfdpMode_64 ??Cy_SMIF_MemInitSfdpMode_65 ??Cy_SMIF_MemInitSfdpMode_66 ??Cy_SMIF_MemInitSfdpMode_67 ??Cy_SMIF_MemInitSfdpMode_68 ??Cy_SMIF_MemInitSfdpMode_69 ??Cy_SMIF_MemInitSfdpMode_7 ??Cy_SMIF_MemInitSfdpMode_70 ??Cy_SMIF_MemInitSfdpMode_71 ??Cy_SMIF_MemInitSfdpMode_72 ??Cy_SMIF_MemInitSfdpMode_73 ??Cy_SMIF_MemInitSfdpMode_74 ??Cy_SMIF_MemInitSfdpMode_75 ??Cy_SMIF_MemInitSfdpMode_76 ??Cy_SMIF_MemInitSfdpMode_77 ??Cy_SMIF_MemInitSfdpMode_78 ??Cy_SMIF_MemInitSfdpMode_79 ??Cy_SMIF_MemInitSfdpMode_8 ??Cy_SMIF_MemInitSfdpMode_80 ??Cy_SMIF_MemInitSfdpMode_81 ??Cy_SMIF_MemInitSfdpMode_82 ??Cy_SMIF_MemInitSfdpMode_83 ??Cy_SMIF_MemInitSfdpMode_84 ??Cy_SMIF_MemInitSfdpMode_85 ??Cy_SMIF_MemInitSfdpMode_86 ??Cy_SMIF_MemInitSfdpMode_87 ??Cy_SMIF_MemInitSfdpMode_88 ??Cy_SMIF_MemInitSfdpMode_89 ??Cy_SMIF_MemInitSfdpMode_9 ??Cy_SMIF_MemInitSfdpMode_90 ??Cy_SMIF_MemInitSfdpMode_91 ??Cy_SMIF_MemInitSfdpMode_92 ??Cy_SMIF_MemInitSfdpMode_93 ??Cy_SMIF_MemInitSfdpMode_94 ??Cy_SMIF_MemInitSfdpMode_95 ??Cy_SMIF_MemInitSfdpMode_96 ??Cy_SMIF_MemInitSfdpMode_97 ??Cy_SMIF_MemInitSfdpMode_98 ??Cy_SMIF_MemInitSfdpMode_99 ??DataTable2 ??SfdpFindParameterTableAddress_0 ??SfdpFindParameterTableAddress_1 ??SfdpFindParameterTableAddress_2 ??SfdpFindParameterTableAddress_3 ??SfdpGetQuadEnableParameters_0 ??SfdpGetQuadEnableParameters_1 ??SfdpGetQuadEnableParameters_2 ??SfdpGetQuadEnableParameters_3 ??SfdpGetQuadEnableParameters_4 ??SfdpGetQuadEnableParameters_5 ??SfdpGetQuadEnableParameters_6 ??SfdpGetQuadEnableParameters_7 ??SfdpGetQuadEnableParameters_8 ??SfdpGetQuadEnableParameters_9 ??SfdpGetSectorEraseCommand_0 ??SfdpGetSectorEraseCommand_1 ??SfdpGetSectorEraseCommand_2 ??SfdpGetSectorEraseCommand_3 ??SfdpGetSectorEraseCommand_4 ??SfdpGetSectorEraseCommand_5 ??SfdpGetSectorEraseCommand_6 ??SfdpGetSectorEraseCommand_7 ??SfdpGetSectorEraseCommand_8 ??SfdpReadBuffer_0 ??SfdpReadBuffer_1 ??SfdpReadBuffer_2 ??SfdpReadBuffer_3 ??SfdpReadBuffer_4 ??SfdpReadBuffer_5 SfdpFindParameterTableAddress SfdpGetQuadEnableParameters SfdpGetSectorEraseCommand SfdpReadBuffer SfdpSetProgramCommandFourBytes_1_1_1 SfdpSetProgramCommand_1_1_1 .text_10 __iar_annotation$$branch C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\src\pdl\drivers\source\cy_sysclk_v2.c ??Cy_SysClk_ClkHfGetFrequency_0 ??Cy_SysClk_ClkPathGetFrequency_0 ??Cy_SysClk_ClkPathGetFrequency_1 ??Cy_SysClk_ClkPathGetFrequency_2 ??Cy_SysClk_ClkPathGetFrequency_3 ??Cy_SysClk_ClkPathGetFrequency_4 ??Cy_SysClk_ClkPathGetSource_0 ??Cy_SysClk_ClkPathMuxGetFrequency_0 ??Cy_SysClk_ClkPathMuxGetFrequency_1 ??Cy_SysClk_ClkPathMuxGetFrequency_2 ??Cy_SysClk_IsClkHfDirectSelEnabled_0 ??Cy_SysClk_Pll400MGetConfiguration_0 ??Cy_SysClk_PllGetConfiguration_0 ??Cy_SysClk_PllIsEnabled_0 ??Cy_SysClk_PllIsEnabled_1 ??DataTable66 ??DataTable71_10 ??DataTable71_4 ??DataTable71_7 ??DataTable71_8 ??DataTable71_9 ??DataTable80_5 ??DataTable81_4 ??DataTable89_1 ??DataTable93_1 ??DataTable98_1 ??DataTable99_12 ??DataTable99_13 cySysClkExtFreq .text_86 .text_90 .text_137 .text_138 .text_142 .text_174 .text_201 .text_221 .text_224 .text_239 .text_260 C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\src\pdl\drivers\source\cy_syslib.c ??Cy_SysLib_Delay_0 ??Cy_SysLib_Delay_1 ??Cy_SysLib_Rtos_DelayUs_0 .text12 .text14 cy_syslib_iar Cy_DelayCycles_done Cy_DelayCycles_loop .text6 C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\src\pdl\drivers\source\cy_wdt_b.c C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\src\bsp\platforms\KIT-XMC7200\cycfg.c C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\src\bsp\platforms\KIT-XMC7200\cycfg_peripherals.c C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\src\bsp\platforms\KIT-XMC7200\cycfg_pins.c ??init_cycfg_pins_0 .rodata8 C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\src\cycfg\cycfg_qspi_memslot_SFDP.c .data9 .data10 .data11 .data12 .data13 .data14 .data15 .data16 .data17 .data18 .data19 .data20 .data21 .data22 .data23 .data24 .data25 .data26 .data27 .data28 .data29 .data30 .data31 .data32 .data33 .data34 .data35 .data36 .data37 .data38 .data39 .data40 .data41 .data42 .data43 .data44 .data45 .data46 .data47 .data48 .data49 .data50 .data51 .data52 .data53 .data54 .data55 .data56 .data57 .data58 .data59 .data60 .data61 .data62 .data63 .data64 .data65 .data66 .data67 .data68 .data69 .data70 .data71 .data72 .data73 .data74 .data75 .data76 .data77 .data78 .data79 .data80 .data81 .data82 .data83 .data84 .data85 .data86 .data87 .data88 .data89 .data90 .data91 .data92 .data93 .data94 .data95 .data96 .data97 .data98 .data99 .data100 .data101 .data102 .data103 .data104 .data105 .data106 .data107 .data108 .data109 .data110 .data111 .data112 .data113 .data114 .data115 .data116 .data117 .data118 .data119 .data120 .data121 .data122 .data123 .data124 .data125 C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\src\framework\iar\flash_loader.c ??Crc16_helper_0 ??Crc16_helper_1 ??Crc16_helper_2 ??Crc16_helper_3 ??Crc16_helper_4 ??Fl2FlashEraseWriteEntry_0 ??Fl2FlashEraseWriteEntry_1 ??Fl2FlashEraseWriteEntry_2 ??FlashBreak_0 .noinit9 .noinit10 .text_11 .text_14 flash_loader_asm .text7 .text_2 LOWEND8 HIGHSTART9 .intvec10 C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\src\framework\iar\flash_loader_cat1c.c ??DataTable0 ??DataTable0_1 ??FlashInit_0 ??FlashInit_1 C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\src\pdl\devices\COMPONENT_CAT1C\templates\COMPONENT_MTB\system_cm0plus.c I32DivMod ABImemcpy ABImemset_small .text_1 memcmp D:\j\workspace\ArmReleaseBuild\build\win\lib\arm\src\lib\dlib\character\strcat.c ??strcat_0 ??strcat_1 ??strcat_2 ??strcat_3 strlen D:\j\workspace\ArmReleaseBuild\build\win\lib\arm\src\lib\ND\common\stdc\memset.c I64Mul I64DivMod strncpy_small IntDivZer I64DivZer __iar_systems$$module __vector_table RamTop$$Base Cy_SysLib_DelayCycles Cy_SysLib_EnterCriticalSection Cy_SysLib_ExitCriticalSection frameworkVersion ioss_0_port_6_pin_3_config ioss_0_port_6_pin_5_config ioss_0_port_7_pin_0_config ioss_0_port_7_pin_1_config ioss_0_port_7_pin_2_config ioss_0_port_7_pin_3_config ioss_0_port_7_pin_4_config ioss_0_port_7_pin_5_config ioss_0_port_8_pin_0_config ioss_0_port_8_pin_1_config ioss_0_port_8_pin_2_config Loader_Backup Loader_Restore Cy_GPIO_Pin_Init Cy_GPIO_Port_Init Cy_GPIO_SetHSIOM Cy_GPIO_Write Cy_GPIO_SetDrivemode Cy_GPIO_SetVtrip Cy_GPIO_SetInterruptMask Cy_GPIO_SetInterruptEdge SMIF_InitHardware SMIF_PrepareConfigs SMIF_TuneConfigs SMIF_FindMappedDevice SMIF_FindDualQuadPair SMIF_Init_XIP SMIF_Init SMIF_UnInit SMIF_Erase SMIF_Program SMIF_OverrideLayout SMIF_EnableQuad SMIF_PollBusy SystemInit SystemCoreClockUpdate init_cycfg_all Cy_SMIF_MemInitSfdpMode Cy_SMIF_MemSfdpDetect Cy_SMIF_Init Cy_SMIF_DeInit Cy_SMIF_SetMode Cy_SMIF_SetDataSelect Cy_SMIF_TransmitCommand Cy_SMIF_TransmitDataBlocking Cy_SMIF_ReceiveDataBlocking Cy_SMIF_SendDummyCycles Cy_SMIF_Enable Cy_SMIF_TransmitCommand_Ext Cy_SMIF_TransmitDataBlocking_Ext Cy_SMIF_ReceiveDataBlocking_Ext Cy_SMIF_SendDummyCycles_Ext Cy_SMIF_MemInit Cy_SMIF_MemCmdWriteEnable Cy_SMIF_MemIsBusy Cy_SMIF_MemQuadEnable Cy_SMIF_MemCmdReadStatus Cy_SMIF_MemCmdWriteStatus Cy_SMIF_MemCmdChipErase Cy_SMIF_MemCmdSectorErase Cy_SMIF_MemLocateHybridRegion Cy_SMIF_SetReadyPollingDelay Cy_SMIF_MemIsReady Cy_SMIF_MemWrite Cy_SMIF_MemEraseSector Cy_SMIF_MemEraseChip __iar_small_uidivmod __iar_small_uidiv strcat Count NumToStr Cy_SysLib_Delay Cy_SysLib_DelayUs Cy_WDT_Unlock Cy_SysClk_ClkHfGetDivider Cy_SysClk_IsClkHfDirectSelEnabled Cy_SysClk_ClkPathGetSource Cy_SysClk_ClkPathMuxGetFrequency Cy_SysClk_ClkPathGetFrequency Cy_SysClk_FllGetConfiguration Cy_SysClk_Pll400MGetConfiguration Cy_SysClk_Pll200MGetConfiguration Cy_SysClk_PllIsEnabled Cy_SysClk_PllGetConfiguration Cy_SysClk_ClkHfGetFrequency init_cycfg_peripherals init_cycfg_pins memset __iar_small_memclr __iar_small_memclr4 __iar_small_memclr8 __iar_small_Memset_word __iar_small_Memset4_word __iar_small_memset __iar_small_memset4 __iar_small_memset8 __aeabi_memcpy4 __aeabi_memcpy8 Cy_SysLib_Rtos_DelayUs Cy_SysLib_Rtos_Delay __aeabi_idiv0 __aeabi_lmul __aeabi_uldivmod __aeabi_ldiv0 Fl2FlashInitEntry Fl2FlashWriteEntry Fl2FlashEraseWriteEntry Fl2FlashChecksumEntry Fl2FlashSignoffEntry Crc16 Crc16_helper FlashBreak FlashInit FlashWrite FlashErase FlashChecksum FlashSignoff FlashInitEntry FlashWriteEntry FlashEraseWriteEntry FlashChecksumEntry FlashSignoffEntry Backup CFGSMIF_SlaveSlot_0_readCmd CFGSMIF_SlaveSlot_0_writeEnCmd CFGSMIF_SlaveSlot_0_writeDisCmd CFGSMIF_SlaveSlot_0_eraseCmd CFGSMIF_SlaveSlot_0_chipEraseCmd CFGSMIF_SlaveSlot_0_programCmd CFGSMIF_SlaveSlot_0_readStsRegQeCmd CFGSMIF_SlaveSlot_0_readStsRegWipCmd CFGSMIF_SlaveSlot_0_writeStsRegQeCmd CFGSMIF_SlaveSlot_0_readSfdpCmd CFGSMIF_SlaveSlot_0_region0 CFGSMIF_SlaveSlot_0_region1 CFGSMIF_SlaveSlot_0_region2 CFGSMIF_SlaveSlot_0_region3 CFGSMIF_SlaveSlot_0_region4 CFGSMIF_SlaveSlot_0_region5 CFGSMIF_SlaveSlot_0_region6 CFGSMIF_SlaveSlot_0_region7 CFGSMIF_SlaveSlot_0_region8 CFGSMIF_SlaveSlot_0_region9 CFGSMIF_SlaveSlot_0_region10 CFGSMIF_SlaveSlot_0_region11 CFGSMIF_SlaveSlot_0_region12 CFGSMIF_SlaveSlot_0_region13 CFGSMIF_SlaveSlot_0_region14 CFGSMIF_SlaveSlot_0_region15 CFGSMIF_SlaveSlot_0_regionInfo CFGSMIF_deviceCfg_SlaveSlot_0 CFGSMIF_SlaveSlot_0 CFGSMIF_SlaveSlot_1_readCmd CFGSMIF_SlaveSlot_1_writeEnCmd CFGSMIF_SlaveSlot_1_writeDisCmd CFGSMIF_SlaveSlot_1_eraseCmd CFGSMIF_SlaveSlot_1_chipEraseCmd CFGSMIF_SlaveSlot_1_programCmd CFGSMIF_SlaveSlot_1_readStsRegQeCmd CFGSMIF_SlaveSlot_1_readStsRegWipCmd CFGSMIF_SlaveSlot_1_writeStsRegQeCmd CFGSMIF_SlaveSlot_1_readSfdpCmd CFGSMIF_SlaveSlot_1_region0 CFGSMIF_SlaveSlot_1_region1 CFGSMIF_SlaveSlot_1_region2 CFGSMIF_SlaveSlot_1_region3 CFGSMIF_SlaveSlot_1_region4 CFGSMIF_SlaveSlot_1_region5 CFGSMIF_SlaveSlot_1_region6 CFGSMIF_SlaveSlot_1_region7 CFGSMIF_SlaveSlot_1_region8 CFGSMIF_SlaveSlot_1_region9 CFGSMIF_SlaveSlot_1_region10 CFGSMIF_SlaveSlot_1_region11 CFGSMIF_SlaveSlot_1_region12 CFGSMIF_SlaveSlot_1_region13 CFGSMIF_SlaveSlot_1_region14 CFGSMIF_SlaveSlot_1_region15 CFGSMIF_SlaveSlot_1_regionInfo CFGSMIF_deviceCfg_SlaveSlot_1 CFGSMIF_SlaveSlot_1 CFGSMIF_SlaveSlot_2_readCmd CFGSMIF_SlaveSlot_2_writeEnCmd CFGSMIF_SlaveSlot_2_writeDisCmd CFGSMIF_SlaveSlot_2_eraseCmd CFGSMIF_SlaveSlot_2_chipEraseCmd CFGSMIF_SlaveSlot_2_programCmd CFGSMIF_SlaveSlot_2_readStsRegQeCmd CFGSMIF_SlaveSlot_2_readStsRegWipCmd CFGSMIF_SlaveSlot_2_writeStsRegQeCmd CFGSMIF_SlaveSlot_2_readSfdpCmd CFGSMIF_SlaveSlot_2_region0 CFGSMIF_SlaveSlot_2_region1 CFGSMIF_SlaveSlot_2_region2 CFGSMIF_SlaveSlot_2_region3 CFGSMIF_SlaveSlot_2_region4 CFGSMIF_SlaveSlot_2_region5 CFGSMIF_SlaveSlot_2_region6 CFGSMIF_SlaveSlot_2_region7 CFGSMIF_SlaveSlot_2_region8 CFGSMIF_SlaveSlot_2_region9 CFGSMIF_SlaveSlot_2_region10 CFGSMIF_SlaveSlot_2_region11 CFGSMIF_SlaveSlot_2_region12 CFGSMIF_SlaveSlot_2_region13 CFGSMIF_SlaveSlot_2_region14 CFGSMIF_SlaveSlot_2_region15 CFGSMIF_SlaveSlot_2_regionInfo CFGSMIF_deviceCfg_SlaveSlot_2 CFGSMIF_SlaveSlot_2 CFGSMIF_SlaveSlot_3_readCmd CFGSMIF_SlaveSlot_3_writeEnCmd CFGSMIF_SlaveSlot_3_writeDisCmd CFGSMIF_SlaveSlot_3_eraseCmd CFGSMIF_SlaveSlot_3_chipEraseCmd CFGSMIF_SlaveSlot_3_programCmd CFGSMIF_SlaveSlot_3_readStsRegQeCmd CFGSMIF_SlaveSlot_3_readStsRegWipCmd CFGSMIF_SlaveSlot_3_writeStsRegQeCmd CFGSMIF_SlaveSlot_3_readSfdpCmd CFGSMIF_SlaveSlot_3_region0 CFGSMIF_SlaveSlot_3_region1 CFGSMIF_SlaveSlot_3_region2 CFGSMIF_SlaveSlot_3_region3 CFGSMIF_SlaveSlot_3_region4 CFGSMIF_SlaveSlot_3_region5 CFGSMIF_SlaveSlot_3_region6 CFGSMIF_SlaveSlot_3_region7 CFGSMIF_SlaveSlot_3_region8 CFGSMIF_SlaveSlot_3_region9 CFGSMIF_SlaveSlot_3_region10 CFGSMIF_SlaveSlot_3_region11 CFGSMIF_SlaveSlot_3_region12 CFGSMIF_SlaveSlot_3_region13 CFGSMIF_SlaveSlot_3_region14 CFGSMIF_SlaveSlot_3_region15 CFGSMIF_SlaveSlot_3_regionInfo CFGSMIF_deviceCfg_SlaveSlot_3 CFGSMIF_SlaveSlot_3 CFGSMIF_smifMemConfigs CFGSMIF_smifBlockConfig cy_delayFreqMhz SystemCoreClock cy_Hfclk0FreqHz cy_PeriClkFreqHz cy_delayFreqHz cy_delayFreqKhz cy_delay32kMs NeedClockUpdate FlashBufferStart RamTop$$Limit theFlashParams FlashBufferEnd RamBottom$$Base __argc __argv __argvbuf CSTACK$$Base CSTACK$$Limit RamBottom$$Limit __iar_rom_use_VIQ$hvOsS01
IAR ELF Linker V9.20.2.320/W64 for ARM -f C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\output\objects\iar\CAT1C_SMIF\FlashCAT1C_SMIF.out.rsp (C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\output\objects\iar\CAT1C_SMIF\algo\algo_base.o C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\output\objects\iar\CAT1C_SMIF\algo\algo_common.o C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\output\objects\iar\CAT1C_SMIF\algo\algo_smif.o C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\output\objects\iar\CAT1C_SMIF\algo\algo_target_syscall.o C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\output\objects\iar\CAT1C_SMIF\algo\algo_xflash.o C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\output\objects\iar\CAT1C_SMIF\pdl\cy_gpio.o C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\output\objects\iar\CAT1C_SMIF\pdl\cy_smif.o C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\output\objects\iar\CAT1C_SMIF\pdl\cy_smif_memslot.o C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\output\objects\iar\CAT1C_SMIF\pdl\cy_smif_sfdp.o C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\output\objects\iar\CAT1C_SMIF\pdl\cy_sysclk_v2.o C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\output\objects\iar\CAT1C_SMIF\pdl\cy_syslib.o C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\output\objects\iar\CAT1C_SMIF\pdl\cy_syslib_iar.o C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\output\objects\iar\CAT1C_SMIF\pdl\cy_wdt_b.o C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\output\objects\iar\CAT1C_SMIF\bsp\cycfg.o C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\output\objects\iar\CAT1C_SMIF\bsp\cycfg_peripherals.o C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\output\objects\iar\CAT1C_SMIF\bsp\cycfg_pins.o C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\output\objects\iar\CAT1C_SMIF\cycfg\cycfg_qspi_memslot_SFDP.o C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\output\objects\iar\CAT1C_SMIF\framework\flash_loader.o C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\output\objects\iar\CAT1C_SMIF\framework\flash_loader_asm.o C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\output\objects\iar\CAT1C_SMIF\framework\flash_loader_cat1c.o C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\output\objects\iar\CAT1C_SMIF\pdl\system_cm0plus.o --no_out_extension -o C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\output\objects\iar\CAT1C_SMIF\FlashCAT1C_SMIF.out --map C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\output\objects\iar\CAT1C_SMIF\FlashCAT1C_SMIF.map --log libraries,initialization,modules,redirects,sections,veneers,unused_fragments,call_graph --log_file C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\output\objects\iar\CAT1C_SMIF\FlashCAT1C_SMIF.log --config C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\framework\iar\link_iar_cat1c.icf --entry FlashInitEntry --vfe --text_out locale) Input comments: C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\output\objects\iar\CAT1C_SMIF\algo\algo_base.o: IAR ANSI C/C++ Compiler V9.20.2.320/W64 for ARM -f C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\output\objects\iar\CAT1C_SMIF\algo\algo_base.o.rsp (C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\src\algo\algo_base.c -D CY_NO_ASSERT -D DIE_TVIIBH4M -D BANK_TYPE_SMIF -D BANK_PART_SFDP -o C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\output\objects\iar\CAT1C_SMIF\algo --debug --endian=little --cpu=Cortex-M0+ -e --fpu=None --dlib_config "C:\Program Files\IAR Systems\Embedded Workbench 9.0\arm\inc\c\DLib_Config_Normal.h" -I "C:\Program Files\IAR Systems\Embedded Workbench 9.0\arm\src\flashloader\framework2\\" -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\algo\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\cycfg\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\core_lib\include\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\framework\iar\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\pdl\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\pdl\cmsis\include\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\pdl\drivers\include\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\pdl\drivers\secure\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\pdl\devices\COMPONENT_CAT1C\include\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\pdl\devices\COMPONENT_CAT1C\include\ip\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\pdl\devices\COMPONENT_CAT1C\templates\COMPONENT_MTB\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\bsp\platforms\KIT-XMC7200\ -Ohz) --dependencies=n C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\output\objects\iar\CAT1C_SMIF\algo\algo_base.o.d C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\output\objects\iar\CAT1C_SMIF\algo\algo_common.o: IAR ANSI C/C++ Compiler V9.20.2.320/W64 for ARM -f C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\output\objects\iar\CAT1C_SMIF\algo\algo_common.o.rsp (C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\src\algo\algo_common.c -D CY_NO_ASSERT -D DIE_TVIIBH4M -D BANK_TYPE_SMIF -D BANK_PART_SFDP -o C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\output\objects\iar\CAT1C_SMIF\algo --debug --endian=little --cpu=Cortex-M0+ -e --fpu=None --dlib_config "C:\Program Files\IAR Systems\Embedded Workbench 9.0\arm\inc\c\DLib_Config_Normal.h" -I "C:\Program Files\IAR Systems\Embedded Workbench 9.0\arm\src\flashloader\framework2\\" -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\algo\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\cycfg\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\core_lib\include\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\framework\iar\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\pdl\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\pdl\cmsis\include\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\pdl\drivers\include\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\pdl\drivers\secure\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\pdl\devices\COMPONENT_CAT1C\include\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\pdl\devices\COMPONENT_CAT1C\include\ip\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\pdl\devices\COMPONENT_CAT1C\templates\COMPONENT_MTB\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\bsp\platforms\KIT-XMC7200\ -Ohz) --dependencies=n C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\output\objects\iar\CAT1C_SMIF\algo\algo_common.o.d C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\output\objects\iar\CAT1C_SMIF\algo\algo_smif.o: IAR ANSI C/C++ Compiler V9.20.2.320/W64 for ARM -f C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\output\objects\iar\CAT1C_SMIF\algo\algo_smif.o.rsp (C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\src\algo\algo_smif.c -D CY_NO_ASSERT -D DIE_TVIIBH4M -D BANK_TYPE_SMIF -D BANK_PART_SFDP -o C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\output\objects\iar\CAT1C_SMIF\algo --debug --endian=little --cpu=Cortex-M0+ -e --fpu=None --dlib_config "C:\Program Files\IAR Systems\Embedded Workbench 9.0\arm\inc\c\DLib_Config_Normal.h" -I "C:\Program Files\IAR Systems\Embedded Workbench 9.0\arm\src\flashloader\framework2\\" -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\algo\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\cycfg\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\core_lib\include\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\framework\iar\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\pdl\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\pdl\cmsis\include\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\pdl\drivers\include\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\pdl\drivers\secure\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\pdl\devices\COMPONENT_CAT1C\include\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\pdl\devices\COMPONENT_CAT1C\include\ip\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\pdl\devices\COMPONENT_CAT1C\templates\COMPONENT_MTB\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\bsp\platforms\KIT-XMC7200\ -Ohz) --dependencies=n C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\output\objects\iar\CAT1C_SMIF\algo\algo_smif.o.d C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\output\objects\iar\CAT1C_SMIF\algo\algo_target_syscall.o: IAR ANSI C/C++ Compiler V9.20.2.320/W64 for ARM -f C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\output\objects\iar\CAT1C_SMIF\algo\algo_target_syscall.o.rsp (C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\src\algo\algo_target_syscall.c -D CY_NO_ASSERT -D DIE_TVIIBH4M -D BANK_TYPE_SMIF -D BANK_PART_SFDP -o C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\output\objects\iar\CAT1C_SMIF\algo --debug --endian=little --cpu=Cortex-M0+ -e --fpu=None --dlib_config "C:\Program Files\IAR Systems\Embedded Workbench 9.0\arm\inc\c\DLib_Config_Normal.h" -I "C:\Program Files\IAR Systems\Embedded Workbench 9.0\arm\src\flashloader\framework2\\" -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\algo\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\cycfg\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\core_lib\include\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\framework\iar\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\pdl\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\pdl\cmsis\include\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\pdl\drivers\include\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\pdl\drivers\secure\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\pdl\devices\COMPONENT_CAT1C\include\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\pdl\devices\COMPONENT_CAT1C\include\ip\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\pdl\devices\COMPONENT_CAT1C\templates\COMPONENT_MTB\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\bsp\platforms\KIT-XMC7200\ -Ohz) --dependencies=n C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\output\objects\iar\CAT1C_SMIF\algo\algo_target_syscall.o.d C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\output\objects\iar\CAT1C_SMIF\algo\algo_xflash.o: IAR ANSI C/C++ Compiler V9.20.2.320/W64 for ARM -f C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\output\objects\iar\CAT1C_SMIF\algo\algo_xflash.o.rsp (C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\src\algo\algo_xflash.c -D CY_NO_ASSERT -D DIE_TVIIBH4M -D BANK_TYPE_SMIF -D BANK_PART_SFDP -o C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\output\objects\iar\CAT1C_SMIF\algo --debug --endian=little --cpu=Cortex-M0+ -e --fpu=None --dlib_config "C:\Program Files\IAR Systems\Embedded Workbench 9.0\arm\inc\c\DLib_Config_Normal.h" -I "C:\Program Files\IAR Systems\Embedded Workbench 9.0\arm\src\flashloader\framework2\\" -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\algo\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\cycfg\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\core_lib\include\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\framework\iar\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\pdl\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\pdl\cmsis\include\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\pdl\drivers\include\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\pdl\drivers\secure\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\pdl\devices\COMPONENT_CAT1C\include\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\pdl\devices\COMPONENT_CAT1C\include\ip\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\pdl\devices\COMPONENT_CAT1C\templates\COMPONENT_MTB\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\bsp\platforms\KIT-XMC7200\ -Ohz) --dependencies=n C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\output\objects\iar\CAT1C_SMIF\algo\algo_xflash.o.d C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\output\objects\iar\CAT1C_SMIF\pdl\cy_gpio.o: IAR ANSI C/C++ Compiler V9.20.2.320/W64 for ARM -f C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\output\objects\iar\CAT1C_SMIF\pdl\cy_gpio.o.rsp (C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\src\pdl\drivers\source\cy_gpio.c -D CY_NO_ASSERT -D DIE_TVIIBH4M -D BANK_TYPE_SMIF -D BANK_PART_SFDP -o C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\output\objects\iar\CAT1C_SMIF\pdl --debug --endian=little --cpu=Cortex-M0+ -e --fpu=None --dlib_config "C:\Program Files\IAR Systems\Embedded Workbench 9.0\arm\inc\c\DLib_Config_Normal.h" -I "C:\Program Files\IAR Systems\Embedded Workbench 9.0\arm\src\flashloader\framework2\\" -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\algo\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\cycfg\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\core_lib\include\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\framework\iar\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\pdl\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\pdl\cmsis\include\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\pdl\drivers\include\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\pdl\drivers\secure\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\pdl\devices\COMPONENT_CAT1C\include\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\pdl\devices\COMPONENT_CAT1C\include\ip\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\pdl\devices\COMPONENT_CAT1C\templates\COMPONENT_MTB\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\bsp\platforms\KIT-XMC7200\ -Ohz) --dependencies=n C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\output\objects\iar\CAT1C_SMIF\pdl\cy_gpio.o.d C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\output\objects\iar\CAT1C_SMIF\pdl\cy_smif.o: IAR ANSI C/C++ Compiler V9.20.2.320/W64 for ARM -f C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\output\objects\iar\CAT1C_SMIF\pdl\cy_smif.o.rsp (C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\src\pdl\drivers\source\cy_smif.c -D CY_NO_ASSERT -D DIE_TVIIBH4M -D BANK_TYPE_SMIF -D BANK_PART_SFDP -o C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\output\objects\iar\CAT1C_SMIF\pdl --debug --endian=little --cpu=Cortex-M0+ -e --fpu=None --dlib_config "C:\Program Files\IAR Systems\Embedded Workbench 9.0\arm\inc\c\DLib_Config_Normal.h" -I "C:\Program Files\IAR Systems\Embedded Workbench 9.0\arm\src\flashloader\framework2\\" -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\algo\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\cycfg\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\core_lib\include\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\framework\iar\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\pdl\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\pdl\cmsis\include\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\pdl\drivers\include\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\pdl\drivers\secure\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\pdl\devices\COMPONENT_CAT1C\include\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\pdl\devices\COMPONENT_CAT1C\include\ip\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\pdl\devices\COMPONENT_CAT1C\templates\COMPONENT_MTB\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\bsp\platforms\KIT-XMC7200\ -Ohz) --dependencies=n C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\output\objects\iar\CAT1C_SMIF\pdl\cy_smif.o.d C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\output\objects\iar\CAT1C_SMIF\pdl\cy_smif_memslot.o: IAR ANSI C/C++ Compiler V9.20.2.320/W64 for ARM -f C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\output\objects\iar\CAT1C_SMIF\pdl\cy_smif_memslot.o.rsp (C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\src\pdl\drivers\source\cy_smif_memslot.c -D CY_NO_ASSERT -D DIE_TVIIBH4M -D BANK_TYPE_SMIF -D BANK_PART_SFDP -o C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\output\objects\iar\CAT1C_SMIF\pdl --debug --endian=little --cpu=Cortex-M0+ -e --fpu=None --dlib_config "C:\Program Files\IAR Systems\Embedded Workbench 9.0\arm\inc\c\DLib_Config_Normal.h" -I "C:\Program Files\IAR Systems\Embedded Workbench 9.0\arm\src\flashloader\framework2\\" -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\algo\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\cycfg\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\core_lib\include\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\framework\iar\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\pdl\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\pdl\cmsis\include\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\pdl\drivers\include\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\pdl\drivers\secure\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\pdl\devices\COMPONENT_CAT1C\include\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\pdl\devices\COMPONENT_CAT1C\include\ip\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\pdl\devices\COMPONENT_CAT1C\templates\COMPONENT_MTB\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\bsp\platforms\KIT-XMC7200\ -Ohz) --dependencies=n C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\output\objects\iar\CAT1C_SMIF\pdl\cy_smif_memslot.o.d C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\output\objects\iar\CAT1C_SMIF\pdl\cy_smif_sfdp.o: IAR ANSI C/C++ Compiler V9.20.2.320/W64 for ARM -f C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\output\objects\iar\CAT1C_SMIF\pdl\cy_smif_sfdp.o.rsp (C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\src\pdl\drivers\source\cy_smif_sfdp.c -D CY_NO_ASSERT -D DIE_TVIIBH4M -D BANK_TYPE_SMIF -D BANK_PART_SFDP -o C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\output\objects\iar\CAT1C_SMIF\pdl --debug --endian=little --cpu=Cortex-M0+ -e --fpu=None --dlib_config "C:\Program Files\IAR Systems\Embedded Workbench 9.0\arm\inc\c\DLib_Config_Normal.h" -I "C:\Program Files\IAR Systems\Embedded Workbench 9.0\arm\src\flashloader\framework2\\" -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\algo\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\cycfg\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\core_lib\include\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\framework\iar\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\pdl\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\pdl\cmsis\include\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\pdl\drivers\include\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\pdl\drivers\secure\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\pdl\devices\COMPONENT_CAT1C\include\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\pdl\devices\COMPONENT_CAT1C\include\ip\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\pdl\devices\COMPONENT_CAT1C\templates\COMPONENT_MTB\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\bsp\platforms\KIT-XMC7200\ -Ohz) --dependencies=n C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\output\objects\iar\CAT1C_SMIF\pdl\cy_smif_sfdp.o.d C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\output\objects\iar\CAT1C_SMIF\pdl\cy_sysclk_v2.o: IAR ANSI C/C++ Compiler V9.20.2.320/W64 for ARM -f C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\output\objects\iar\CAT1C_SMIF\pdl\cy_sysclk_v2.o.rsp (C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\src\pdl\drivers\source\cy_sysclk_v2.c -D CY_NO_ASSERT -D DIE_TVIIBH4M -D BANK_TYPE_SMIF -D BANK_PART_SFDP -o C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\output\objects\iar\CAT1C_SMIF\pdl --debug --endian=little --cpu=Cortex-M0+ -e --fpu=None --dlib_config "C:\Program Files\IAR Systems\Embedded Workbench 9.0\arm\inc\c\DLib_Config_Normal.h" -I "C:\Program Files\IAR Systems\Embedded Workbench 9.0\arm\src\flashloader\framework2\\" -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\algo\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\cycfg\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\core_lib\include\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\framework\iar\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\pdl\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\pdl\cmsis\include\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\pdl\drivers\include\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\pdl\drivers\secure\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\pdl\devices\COMPONENT_CAT1C\include\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\pdl\devices\COMPONENT_CAT1C\include\ip\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\pdl\devices\COMPONENT_CAT1C\templates\COMPONENT_MTB\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\bsp\platforms\KIT-XMC7200\ -Ohz) --dependencies=n C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\output\objects\iar\CAT1C_SMIF\pdl\cy_sysclk_v2.o.d C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\output\objects\iar\CAT1C_SMIF\pdl\cy_syslib.o: IAR ANSI C/C++ Compiler V9.20.2.320/W64 for ARM -f C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\output\objects\iar\CAT1C_SMIF\pdl\cy_syslib.o.rsp (C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\src\pdl\drivers\source\cy_syslib.c -D CY_NO_ASSERT -D DIE_TVIIBH4M -D BANK_TYPE_SMIF -D BANK_PART_SFDP -o C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\output\objects\iar\CAT1C_SMIF\pdl --debug --endian=little --cpu=Cortex-M0+ -e --fpu=None --dlib_config "C:\Program Files\IAR Systems\Embedded Workbench 9.0\arm\inc\c\DLib_Config_Normal.h" -I "C:\Program Files\IAR Systems\Embedded Workbench 9.0\arm\src\flashloader\framework2\\" -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\algo\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\cycfg\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\core_lib\include\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\framework\iar\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\pdl\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\pdl\cmsis\include\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\pdl\drivers\include\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\pdl\drivers\secure\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\pdl\devices\COMPONENT_CAT1C\include\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\pdl\devices\COMPONENT_CAT1C\include\ip\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\pdl\devices\COMPONENT_CAT1C\templates\COMPONENT_MTB\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\bsp\platforms\KIT-XMC7200\ -Ohz) --dependencies=n C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\output\objects\iar\CAT1C_SMIF\pdl\cy_syslib.o.d C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\output\objects\iar\CAT1C_SMIF\pdl\cy_syslib_iar.o: IAR Assembler V9.20.2.320/W64 for ARM -f C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\output\objects\iar\CAT1C_SMIF\pdl\cy_syslib_iar.o.rsp (C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\src\pdl\drivers\source\TOOLCHAIN_IAR\cy_syslib_iar.s -OC:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\output\objects\iar\CAT1C_SMIF\pdl -s+ -M<> -w+ -r --cpu Cortex-M0+ --fpu None) C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\output\objects\iar\CAT1C_SMIF\pdl\cy_wdt_b.o: IAR ANSI C/C++ Compiler V9.20.2.320/W64 for ARM -f C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\output\objects\iar\CAT1C_SMIF\pdl\cy_wdt_b.o.rsp (C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\src\pdl\drivers\source\cy_wdt_b.c -D CY_NO_ASSERT -D DIE_TVIIBH4M -D BANK_TYPE_SMIF -D BANK_PART_SFDP -o C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\output\objects\iar\CAT1C_SMIF\pdl --debug --endian=little --cpu=Cortex-M0+ -e --fpu=None --dlib_config "C:\Program Files\IAR Systems\Embedded Workbench 9.0\arm\inc\c\DLib_Config_Normal.h" -I "C:\Program Files\IAR Systems\Embedded Workbench 9.0\arm\src\flashloader\framework2\\" -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\algo\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\cycfg\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\core_lib\include\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\framework\iar\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\pdl\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\pdl\cmsis\include\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\pdl\drivers\include\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\pdl\drivers\secure\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\pdl\devices\COMPONENT_CAT1C\include\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\pdl\devices\COMPONENT_CAT1C\include\ip\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\pdl\devices\COMPONENT_CAT1C\templates\COMPONENT_MTB\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\bsp\platforms\KIT-XMC7200\ -Ohz) --dependencies=n C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\output\objects\iar\CAT1C_SMIF\pdl\cy_wdt_b.o.d C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\output\objects\iar\CAT1C_SMIF\bsp\cycfg.o: IAR ANSI C/C++ Compiler V9.20.2.320/W64 for ARM -f C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\output\objects\iar\CAT1C_SMIF\bsp\cycfg.o.rsp (C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\src\bsp\platforms\KIT-XMC7200\cycfg.c -D CY_NO_ASSERT -D DIE_TVIIBH4M -D BANK_TYPE_SMIF -D BANK_PART_SFDP -o C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\output\objects\iar\CAT1C_SMIF\bsp --debug --endian=little --cpu=Cortex-M0+ -e --fpu=None --dlib_config "C:\Program Files\IAR Systems\Embedded Workbench 9.0\arm\inc\c\DLib_Config_Normal.h" -I "C:\Program Files\IAR Systems\Embedded Workbench 9.0\arm\src\flashloader\framework2\\" -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\algo\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\cycfg\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\core_lib\include\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\framework\iar\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\pdl\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\pdl\cmsis\include\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\pdl\drivers\include\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\pdl\drivers\secure\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\pdl\devices\COMPONENT_CAT1C\include\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\pdl\devices\COMPONENT_CAT1C\include\ip\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\pdl\devices\COMPONENT_CAT1C\templates\COMPONENT_MTB\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\bsp\platforms\KIT-XMC7200\ -Ohz) --dependencies=n C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\output\objects\iar\CAT1C_SMIF\bsp\cycfg.o.d C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\output\objects\iar\CAT1C_SMIF\bsp\cycfg_peripherals.o: IAR ANSI C/C++ Compiler V9.20.2.320/W64 for ARM -f C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\output\objects\iar\CAT1C_SMIF\bsp\cycfg_peripherals.o.rsp (C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\src\bsp\platforms\KIT-XMC7200\cycfg_peripherals.c -D CY_NO_ASSERT -D DIE_TVIIBH4M -D BANK_TYPE_SMIF -D BANK_PART_SFDP -o C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\output\objects\iar\CAT1C_SMIF\bsp --debug --endian=little --cpu=Cortex-M0+ -e --fpu=None --dlib_config "C:\Program Files\IAR Systems\Embedded Workbench 9.0\arm\inc\c\DLib_Config_Normal.h" -I "C:\Program Files\IAR Systems\Embedded Workbench 9.0\arm\src\flashloader\framework2\\" -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\algo\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\cycfg\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\core_lib\include\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\framework\iar\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\pdl\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\pdl\cmsis\include\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\pdl\drivers\include\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\pdl\drivers\secure\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\pdl\devices\COMPONENT_CAT1C\include\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\pdl\devices\COMPONENT_CAT1C\include\ip\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\pdl\devices\COMPONENT_CAT1C\templates\COMPONENT_MTB\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\bsp\platforms\KIT-XMC7200\ -Ohz) --dependencies=n C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\output\objects\iar\CAT1C_SMIF\bsp\cycfg_peripherals.o.d C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\output\objects\iar\CAT1C_SMIF\bsp\cycfg_pins.o: IAR ANSI C/C++ Compiler V9.20.2.320/W64 for ARM -f C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\output\objects\iar\CAT1C_SMIF\bsp\cycfg_pins.o.rsp (C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\src\bsp\platforms\KIT-XMC7200\cycfg_pins.c -D CY_NO_ASSERT -D DIE_TVIIBH4M -D BANK_TYPE_SMIF -D BANK_PART_SFDP -o C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\output\objects\iar\CAT1C_SMIF\bsp --debug --endian=little --cpu=Cortex-M0+ -e --fpu=None --dlib_config "C:\Program Files\IAR Systems\Embedded Workbench 9.0\arm\inc\c\DLib_Config_Normal.h" -I "C:\Program Files\IAR Systems\Embedded Workbench 9.0\arm\src\flashloader\framework2\\" -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\algo\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\cycfg\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\core_lib\include\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\framework\iar\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\pdl\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\pdl\cmsis\include\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\pdl\drivers\include\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\pdl\drivers\secure\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\pdl\devices\COMPONENT_CAT1C\include\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\pdl\devices\COMPONENT_CAT1C\include\ip\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\pdl\devices\COMPONENT_CAT1C\templates\COMPONENT_MTB\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\bsp\platforms\KIT-XMC7200\ -Ohz) --dependencies=n C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\output\objects\iar\CAT1C_SMIF\bsp\cycfg_pins.o.d C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\output\objects\iar\CAT1C_SMIF\cycfg\cycfg_qspi_memslot_SFDP.o: IAR ANSI C/C++ Compiler V9.20.2.320/W64 for ARM -f C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\output\objects\iar\CAT1C_SMIF\cycfg\cycfg_qspi_memslot_SFDP.o.rsp (C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\src\cycfg\cycfg_qspi_memslot_SFDP.c -D CY_NO_ASSERT -D DIE_TVIIBH4M -D BANK_TYPE_SMIF -D BANK_PART_SFDP -o C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\output\objects\iar\CAT1C_SMIF\cycfg --debug --endian=little --cpu=Cortex-M0+ -e --fpu=None --dlib_config "C:\Program Files\IAR Systems\Embedded Workbench 9.0\arm\inc\c\DLib_Config_Normal.h" -I "C:\Program Files\IAR Systems\Embedded Workbench 9.0\arm\src\flashloader\framework2\\" -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\algo\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\cycfg\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\core_lib\include\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\framework\iar\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\pdl\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\pdl\cmsis\include\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\pdl\drivers\include\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\pdl\drivers\secure\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\pdl\devices\COMPONENT_CAT1C\include\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\pdl\devices\COMPONENT_CAT1C\include\ip\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\pdl\devices\COMPONENT_CAT1C\templates\COMPONENT_MTB\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\bsp\platforms\KIT-XMC7200\ -Ohz) --dependencies=n C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\output\objects\iar\CAT1C_SMIF\cycfg\cycfg_qspi_memslot_SFDP.o.d C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\output\objects\iar\CAT1C_SMIF\framework\flash_loader.o: IAR ANSI C/C++ Compiler V9.20.2.320/W64 for ARM -f C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\output\objects\iar\CAT1C_SMIF\framework\flash_loader.o.rsp (C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\src\framework\iar\flash_loader.c -D CY_NO_ASSERT -D DIE_TVIIBH4M -D BANK_TYPE_SMIF -D BANK_PART_SFDP -o C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\output\objects\iar\CAT1C_SMIF\framework --debug --endian=little --cpu=Cortex-M0+ -e --fpu=None --dlib_config "C:\Program Files\IAR Systems\Embedded Workbench 9.0\arm\inc\c\DLib_Config_Normal.h" -I "C:\Program Files\IAR Systems\Embedded Workbench 9.0\arm\src\flashloader\framework2\\" -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\algo\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\cycfg\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\core_lib\include\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\framework\iar\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\pdl\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\pdl\cmsis\include\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\pdl\drivers\include\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\pdl\drivers\secure\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\pdl\devices\COMPONENT_CAT1C\include\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\pdl\devices\COMPONENT_CAT1C\include\ip\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\pdl\devices\COMPONENT_CAT1C\templates\COMPONENT_MTB\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\bsp\platforms\KIT-XMC7200\ -Ohz) --dependencies=n C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\output\objects\iar\CAT1C_SMIF\framework\flash_loader.o.d C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\output\objects\iar\CAT1C_SMIF\framework\flash_loader_asm.o: IAR Assembler V9.20.2.320/W64 for ARM -f C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\output\objects\iar\CAT1C_SMIF\framework\flash_loader_asm.o.rsp (C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\src\framework\iar\flash_loader_asm.s -OC:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\output\objects\iar\CAT1C_SMIF\framework -s+ -M<> -w+ -r --cpu Cortex-M0+ --fpu None) C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\output\objects\iar\CAT1C_SMIF\framework\flash_loader_cat1c.o: IAR ANSI C/C++ Compiler V9.20.2.320/W64 for ARM -f C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\output\objects\iar\CAT1C_SMIF\framework\flash_loader_cat1c.o.rsp (C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\src\framework\iar\flash_loader_cat1c.c -D CY_NO_ASSERT -D DIE_TVIIBH4M -D BANK_TYPE_SMIF -D BANK_PART_SFDP -o C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\output\objects\iar\CAT1C_SMIF\framework --debug --endian=little --cpu=Cortex-M0+ -e --fpu=None --dlib_config "C:\Program Files\IAR Systems\Embedded Workbench 9.0\arm\inc\c\DLib_Config_Normal.h" -I "C:\Program Files\IAR Systems\Embedded Workbench 9.0\arm\src\flashloader\framework2\\" -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\algo\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\cycfg\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\core_lib\include\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\framework\iar\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\pdl\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\pdl\cmsis\include\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\pdl\drivers\include\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\pdl\drivers\secure\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\pdl\devices\COMPONENT_CAT1C\include\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\pdl\devices\COMPONENT_CAT1C\include\ip\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\pdl\devices\COMPONENT_CAT1C\templates\COMPONENT_MTB\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\bsp\platforms\KIT-XMC7200\ -Ohz) --dependencies=n C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\output\objects\iar\CAT1C_SMIF\framework\flash_loader_cat1c.o.d C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\output\objects\iar\CAT1C_SMIF\pdl\system_cm0plus.o: IAR ANSI C/C++ Compiler V9.20.2.320/W64 for ARM -f C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\output\objects\iar\CAT1C_SMIF\pdl\system_cm0plus.o.rsp (C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\src\pdl\devices\COMPONENT_CAT1C\templates\COMPONENT_MTB\system_cm0plus.c -D CY_NO_ASSERT -D DIE_TVIIBH4M -D BANK_TYPE_SMIF -D BANK_PART_SFDP -o C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\output\objects\iar\CAT1C_SMIF\pdl --debug --endian=little --cpu=Cortex-M0+ -e --fpu=None --dlib_config "C:\Program Files\IAR Systems\Embedded Workbench 9.0\arm\inc\c\DLib_Config_Normal.h" -I "C:\Program Files\IAR Systems\Embedded Workbench 9.0\arm\src\flashloader\framework2\\" -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\algo\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\cycfg\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\core_lib\include\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\framework\iar\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\pdl\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\pdl\cmsis\include\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\pdl\drivers\include\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\pdl\drivers\secure\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\pdl\devices\COMPONENT_CAT1C\include\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\pdl\devices\COMPONENT_CAT1C\include\ip\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\pdl\devices\COMPONENT_CAT1C\templates\COMPONENT_MTB\ -I C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_iar\..\src\bsp\platforms\KIT-XMC7200\ -Ohz) --dependencies=n C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\output\objects\iar\CAT1C_SMIF\pdl\system_cm0plus.o.d I32DivMod.o(rt6M_tl.a): IAR Assembler X9.20.2.320/W64 [Nov 12 2021:debug] for ARM --cpu Cortex-M0 -D_SYSTEM_BUILD -D__NO_INEXACT__ -D__OPT_MEDIUM__ -D__THUMB_LIBRARY__ -I../../arm/src/lib/include -S -ws ../../arm/src/lib/ND/T16/int/I32DivMod.s -o rt6M_tl/I32DivMod.o ABImemcpy.o(rt6M_tl.a): IAR Assembler X9.20.2.320/W64 [Nov 12 2021:debug] for ARM --cpu Cortex-M0 -D_SYSTEM_BUILD -D__NO_INEXACT__ -D__OPT_MEDIUM__ -D__THUMB_LIBRARY__ -I../../arm/src/lib/include -S -ws ../../arm/src/lib/ND/T16/stdc/ABImemcpy.s -o rt6M_tl/ABImemcpy.o ABImemset_small.o(rt6M_tl.a): IAR Assembler X9.20.2.320/W64 [Nov 12 2021:debug] for ARM --cpu Cortex-M0 -D_SYSTEM_BUILD -D__NO_INEXACT__ -D__OPT_MEDIUM__ -D__THUMB_LIBRARY__ -I../../arm/src/lib/include -S -ws ../../arm/src/lib/ND/T16/stdc/ABImemset_small.s -o rt6M_tl/ABImemset_small.o memcmp.o(rt6M_tl.a): IAR Assembler X9.20.2.320/W64 [Nov 12 2021:debug] for ARM --cpu Cortex-M0 -D_SYSTEM_BUILD -D__NO_INEXACT__ -D__OPT_MEDIUM__ -D__THUMB_LIBRARY__ -I../../arm/src/lib/include -S -ws ../../arm/src/lib/ND/T16/stdc/memcmp.s -o rt6M_tl/memcmp.o strcat.o(dl6M_tln.a): IAR ANSI C/C++ Compiler V9.20.2.320/W64 [jenkins-ArmReleaseBuild-38 ** NOT FOR DISTRIBUTION **] (UNPROTECTED) for ARM --cpu Cortex-M0 --dlib_config=normal --require_prototypes --ropi --silent --strict_ansi --vfpcc_compatible --warnings_are_errors -D_SYSTEM_BUILD -I../../arm/src/lib/character -Oh ../../arm/src/lib/dlib/character/strcat.c -o dl6M_tln/strcat.o strlen.o(rt6M_tl.a): IAR Assembler X9.20.2.320/W64 [Nov 12 2021:debug] for ARM --cpu Cortex-M0 -D_SYSTEM_BUILD -D__NO_INEXACT__ -D__OPT_MEDIUM__ -D__THUMB_LIBRARY__ -I../../arm/src/lib/include -S -ws ../../arm/src/lib/ND/T16/stdc/strlen.s -o rt6M_tl/strlen.o memset.o(rt6M_tl.a): IAR ANSI C/C++ Compiler V9.20.2.320/W64 [jenkins-ArmReleaseBuild-38 ** NOT FOR DISTRIBUTION **] (UNPROTECTED) for ARM --cpu Cortex-M0 --dlib_config=DLib_Config_Agnostic.h --require_prototypes --ropi --rwpi_compatible --silent --strict_ansi --warnings_are_errors -D_SYSTEM_BUILD -I../../arm/src/lib/dlib -Oh ../../arm/src/lib/ND/common/stdc/memset.c -o rt6M_tl/memset.o I64Mul.o(rt6M_tl.a): IAR Assembler X9.20.2.320/W64 [Nov 12 2021:debug] for ARM --cpu Cortex-M0 -D_SYSTEM_BUILD -D__NO_INEXACT__ -D__OPT_MEDIUM__ -D__THUMB_LIBRARY__ -I../../arm/src/lib/include -S -ws ../../arm/src/lib/ND/T16/int/I64Mul.s -o rt6M_tl/I64Mul.o I64DivMod.o(rt6M_tl.a): IAR Assembler X9.20.2.320/W64 [Nov 12 2021:debug] for ARM --cpu Cortex-M0 -D_SYSTEM_BUILD -D__NO_INEXACT__ -D__OPT_MEDIUM__ -D__THUMB_LIBRARY__ -I../../arm/src/lib/include -S -ws ../../arm/src/lib/ND/T16/int/I64DivMod.s -o rt6M_tl/I64DivMod.o strncpy_small.o(rt6M_tl.a): IAR Assembler X9.20.2.320/W64 [Nov 12 2021:debug] for ARM --cpu Cortex-M0 -D_SYSTEM_BUILD -D__NO_INEXACT__ -D__OPT_MEDIUM__ -D__THUMB_LIBRARY__ -I../../arm/src/lib/include -S -ws ../../arm/src/lib/ND/T16/stdc/strncpy_small.s -o rt6M_tl/strncpy_small.o IntDivZer.o(rt6M_tl.a): IAR Assembler X9.20.2.320/W64 [Nov 12 2021:debug] for ARM --cpu Cortex-M0 -D_SYSTEM_BUILD -D__NO_INEXACT__ -D__OPT_MEDIUM__ -D__THUMB_LIBRARY__ -I../../arm/src/lib/include -S -ws ../../arm/src/lib/ND/T16/system/IntDivZer.s -o rt6M_tl/IntDivZer.o I64DivZer.o(rt6M_tl.a): IAR Assembler X9.20.2.320/W64 [Nov 12 2021:debug] for ARM --cpu Cortex-M0 -D_SYSTEM_BUILD -D__NO_INEXACT__ -D__OPT_MEDIUM__ -D__THUMB_LIBRARY__ -I../../arm/src/lib/include -S -ws ../../arm/src/lib/ND/T16/system/I64DivZer.s -o rt6M_tl/I64DivZer.o