Component: ARM Compiler 6.16 Tool: armclang [5dfeb700] ../src/bsp/platforms/KIT-XMC7200\cycfg_system.c C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_cmsis_uv srss_0_clock_0_pll400m_0_pllConfig inputFreq unsigned int uint32_t outputFreq lfMode _Bool outputMode unsigned char CY_SYSCLK_FLLPLL_OUTPUT_AUTO CY_SYSCLK_FLLPLL_OUTPUT_AUTO1 CY_SYSCLK_FLLPLL_OUTPUT_INPUT CY_SYSCLK_FLLPLL_OUTPUT_OUTPUT cy_en_fll_pll_output_mode_t cy_stc_pll_config_t srss_0_clock_0_pll400m_1_pllConfig srss_0_clock_0_pll_0_pllConfig feedbackDiv uint8_t referenceDiv outputDiv fracDiv fracDitherEn fracEn sscgDepth sscgRate sscgEn cy_stc_pll_manual_config_t srss_0_clock_0_pll_1_pllConfig srss_0_clock_0_fll_0_fllConfig fllMult refDiv unsigned short uint16_t ccoRange CY_SYSCLK_FLL_CCO_RANGE0 CY_SYSCLK_FLL_CCO_RANGE1 CY_SYSCLK_FLL_CCO_RANGE2 CY_SYSCLK_FLL_CCO_RANGE3 CY_SYSCLK_FLL_CCO_RANGE4 cy_en_fll_cco_ranges_t enableOutputDiv lockTolerance igain pgain settlingCount cco_Freq cy_stc_fll_manual_config_t CY_SYSCLK_SUCCESS CY_SYSCLK_BAD_PARAM CY_SYSCLK_TIMEOUT CY_SYSCLK_INVALID_STATE CY_SYSCLK_UNSUPPORTED_STATE CY_SYSCLK_CLKPATH_IN_IMO CY_SYSCLK_CLKPATH_IN_EXT CY_SYSCLK_CLKPATH_IN_ECO CY_SYSCLK_CLKPATH_IN_ALTHF CY_SYSCLK_CLKPATH_IN_DSIMUX CY_SYSCLK_CLKPATH_IN_LPECO CY_SYSCLK_CLKPATH_IN_IHO CY_SYSCLK_CLKPATH_IN_DSI CY_SYSCLK_CLKPATH_IN_ILO CY_SYSCLK_CLKPATH_IN_WCO CY_SYSCLK_CLKPATH_IN_ALTLF CY_SYSCLK_CLKPATH_IN_PILO CY_SYSCLK_CLKPATH_IN_ILO1 CY_SYSCLK_CLKHF_IN_CLKPATH0 CY_SYSCLK_CLKHF_IN_CLKPATH1 CY_SYSCLK_CLKHF_IN_CLKPATH2 CY_SYSCLK_CLKHF_IN_CLKPATH3 CY_SYSCLK_CLKHF_IN_CLKPATH4 CY_SYSCLK_CLKHF_IN_CLKPATH5 CY_SYSCLK_CLKHF_IN_CLKPATH6 CY_SYSCLK_CLKHF_IN_CLKPATH7 CY_SYSCLK_CLKHF_IN_CLKPATH8 CY_SYSCLK_CLKHF_IN_CLKPATH9 CY_SYSCLK_CLKHF_IN_CLKPATH10 CY_SYSCLK_CLKHF_IN_CLKPATH11 CY_SYSCLK_CLKHF_IN_CLKPATH12 CY_SYSCLK_CLKHF_IN_CLKPATH13 CY_SYSCLK_CLKHF_IN_CLKPATH14 CY_SYSCLK_CLKHF_IN_CLKPATH15 CY_SYSCLK_CLKHF_NO_DIVIDE CY_SYSCLK_CLKHF_DIVIDE_BY_2 CY_SYSCLK_CLKHF_DIVIDE_BY_4 CY_SYSCLK_CLKHF_DIVIDE_BY_8 cycfg_ClockStartupError init_cycfg_system Cy_SysClk_FllDeInit Cy_SysClk_ClkPath1Init Cy_SysClk_ClkPath2Init Cy_SysClk_ClkPath3Init Cy_SysClk_ClkPath4Init Cy_SysClk_ClkPath5Init Cy_SysClk_ClkPath6Init Cy_SysClk_Pll0Init Cy_SysClk_Pll1Init Cy_SysClk_Pll2Init Cy_SysClk_Pll3Init Cy_SysClk_ClkHf1Init Cy_SysClk_ClkHf2Init Cy_SysClk_ClkHf3Init Cy_SysClk_ClkHf4Init Cy_SysClk_ClkHf5Init Cy_SysClk_ClkHf6Init Cy_SysClk_ClkHf7Init Cy_SysClk_FllInit Cy_SysClk_ClkPath0Init Cy_SysClk_ClkHf0Init Cy_SysClk_ClkFast_0_Init error Component: ARM Compiler 6.16 Tool: armclang [5dfeb700] ../src/bsp/platforms/KIT-XMC7200\cycfg_pins.c C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_cmsis_uv ioss_0_port_6_pin_3_config outVal unsigned int uint32_t driveMode hsiom unsigned char HSIOM_SEL_GPIO HSIOM_SEL_GPIO_DSI HSIOM_SEL_DSI_DSI HSIOM_SEL_DSI_GPIO HSIOM_SEL_AMUXA HSIOM_SEL_AMUXB HSIOM_SEL_AMUXA_DSI HSIOM_SEL_AMUXB_DSI HSIOM_SEL_ACT_0 HSIOM_SEL_ACT_1 HSIOM_SEL_ACT_2 HSIOM_SEL_ACT_3 HSIOM_SEL_DS_0 HSIOM_SEL_DS_1 HSIOM_SEL_DS_2 HSIOM_SEL_DS_3 HSIOM_SEL_ACT_4 HSIOM_SEL_ACT_5 HSIOM_SEL_ACT_6 HSIOM_SEL_ACT_7 HSIOM_SEL_ACT_8 HSIOM_SEL_ACT_9 HSIOM_SEL_ACT_10 HSIOM_SEL_ACT_11 HSIOM_SEL_ACT_12 HSIOM_SEL_ACT_13 HSIOM_SEL_ACT_14 HSIOM_SEL_ACT_15 HSIOM_SEL_DS_4 HSIOM_SEL_DS_5 HSIOM_SEL_DS_6 HSIOM_SEL_DS_7 P6_3_SMIF0_SPIHB_CLK P6_5_SMIF0_SPIHB_SELECT0 P7_0_SMIF0_SPIHB_SELECT1 P7_1_SMIF0_SPIHB_DATA0 P7_2_SMIF0_SPIHB_DATA1 P7_3_SMIF0_SPIHB_DATA2 P7_4_SMIF0_SPIHB_DATA3 P7_5_SMIF0_SPIHB_DATA4 P8_0_SMIF0_SPIHB_DATA5 P8_1_SMIF0_SPIHB_DATA6 P8_2_SMIF0_SPIHB_DATA7 en_hsiom_sel_t intEdge intMask vtrip slewRate driveSel vregEn ibufMode vtripSel vrefSel vohSel cy_stc_gpio_pin_config_t ioss_0_port_6_pin_5_config ioss_0_port_7_pin_0_config ioss_0_port_7_pin_1_config ioss_0_port_7_pin_2_config ioss_0_port_7_pin_3_config ioss_0_port_7_pin_4_config ioss_0_port_7_pin_5_config ioss_0_port_8_pin_0_config ioss_0_port_8_pin_1_config ioss_0_port_8_pin_2_config CY_GPIO_SUCCESS CY_GPIO_BAD_PARAM OUT OUT_CLR OUT_SET OUT_INV IN INTR INTR_MASK INTR_MASKED INTR_SET RESERVED __ARRAY_SIZE_TYPE__ INTR_CFG CFG CFG_IN CFG_OUT CFG_SIO RESERVED1 CFG_IN_AUTOLVL RESERVED2 GPIO_PRT_Type PRT INTR_CAUSE0 INTR_CAUSE1 INTR_CAUSE2 INTR_CAUSE3 VDD_ACTIVE VDD_INTR VDD_INTR_MASK VDD_INTR_MASKED VDD_INTR_SET GPIO_Type init_cycfg_pins Component: ARM Compiler 6.16 Tool: armclang [5dfeb700] ../src/bsp/platforms/KIT-XMC7200\cycfg_peripherals.c C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_cmsis_uv SMIF_config mode unsigned int uint32_t deselectDelay rxClockSel blockEvent cy_stc_smif_config_t init_cycfg_peripherals Component: ARM Compiler 6.16 Tool: armclang [5dfeb700] ../src/bsp/platforms/KIT-XMC7200\cycfg_clocks.c C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_cmsis_uv unsigned short PCLK_CPUSS_CLOCK_TRACE_IN PCLK_SMARTIO12_CLOCK PCLK_SMARTIO13_CLOCK PCLK_SMARTIO14_CLOCK PCLK_SMARTIO15_CLOCK PCLK_SMARTIO17_CLOCK PCLK_CANFD0_CLOCK_CAN0 PCLK_CANFD0_CLOCK_CAN1 PCLK_CANFD0_CLOCK_CAN2 PCLK_CANFD0_CLOCK_CAN3 PCLK_CANFD1_CLOCK_CAN0 PCLK_CANFD1_CLOCK_CAN1 PCLK_CANFD1_CLOCK_CAN2 PCLK_CANFD1_CLOCK_CAN3 PCLK_LIN0_CLOCK_CH_EN0 PCLK_LIN0_CLOCK_CH_EN1 PCLK_LIN0_CLOCK_CH_EN2 PCLK_LIN0_CLOCK_CH_EN3 PCLK_LIN0_CLOCK_CH_EN4 PCLK_LIN0_CLOCK_CH_EN5 PCLK_LIN0_CLOCK_CH_EN6 PCLK_LIN0_CLOCK_CH_EN7 PCLK_LIN0_CLOCK_CH_EN8 PCLK_LIN0_CLOCK_CH_EN9 PCLK_LIN0_CLOCK_CH_EN10 PCLK_LIN0_CLOCK_CH_EN11 PCLK_LIN0_CLOCK_CH_EN12 PCLK_LIN0_CLOCK_CH_EN13 PCLK_LIN0_CLOCK_CH_EN14 PCLK_LIN0_CLOCK_CH_EN15 PCLK_SCB0_CLOCK PCLK_SCB1_CLOCK PCLK_SCB2_CLOCK PCLK_SCB3_CLOCK PCLK_SCB4_CLOCK PCLK_SCB5_CLOCK PCLK_SCB6_CLOCK PCLK_SCB7_CLOCK PCLK_SCB8_CLOCK PCLK_SCB9_CLOCK PCLK_SCB10_CLOCK PCLK_PASS0_CLOCK_SAR0 PCLK_PASS0_CLOCK_SAR1 PCLK_PASS0_CLOCK_SAR2 PCLK_TCPWM0_CLOCKS0 PCLK_TCPWM0_CLOCKS1 PCLK_TCPWM0_CLOCKS2 PCLK_TCPWM0_CLOCKS3 PCLK_TCPWM0_CLOCKS4 PCLK_TCPWM0_CLOCKS5 PCLK_TCPWM0_CLOCKS6 PCLK_TCPWM0_CLOCKS7 PCLK_TCPWM0_CLOCKS8 PCLK_TCPWM0_CLOCKS9 PCLK_TCPWM0_CLOCKS10 PCLK_TCPWM0_CLOCKS11 PCLK_TCPWM0_CLOCKS12 PCLK_TCPWM0_CLOCKS13 PCLK_TCPWM0_CLOCKS14 PCLK_TCPWM0_CLOCKS15 PCLK_TCPWM0_CLOCKS16 PCLK_TCPWM0_CLOCKS17 PCLK_TCPWM0_CLOCKS18 PCLK_TCPWM0_CLOCKS19 PCLK_TCPWM0_CLOCKS20 PCLK_TCPWM0_CLOCKS21 PCLK_TCPWM0_CLOCKS22 PCLK_TCPWM0_CLOCKS23 PCLK_TCPWM0_CLOCKS24 PCLK_TCPWM0_CLOCKS25 PCLK_TCPWM0_CLOCKS26 PCLK_TCPWM0_CLOCKS27 PCLK_TCPWM0_CLOCKS28 PCLK_TCPWM0_CLOCKS29 PCLK_TCPWM0_CLOCKS30 PCLK_TCPWM0_CLOCKS31 PCLK_TCPWM0_CLOCKS32 PCLK_TCPWM0_CLOCKS33 PCLK_TCPWM0_CLOCKS34 PCLK_TCPWM0_CLOCKS35 PCLK_TCPWM0_CLOCKS36 PCLK_TCPWM0_CLOCKS37 PCLK_TCPWM0_CLOCKS38 PCLK_TCPWM0_CLOCKS39 PCLK_TCPWM0_CLOCKS40 PCLK_TCPWM0_CLOCKS41 PCLK_TCPWM0_CLOCKS42 PCLK_TCPWM0_CLOCKS43 PCLK_TCPWM0_CLOCKS44 PCLK_TCPWM0_CLOCKS45 PCLK_TCPWM0_CLOCKS46 PCLK_TCPWM0_CLOCKS47 PCLK_TCPWM0_CLOCKS48 PCLK_TCPWM0_CLOCKS49 PCLK_TCPWM0_CLOCKS50 PCLK_TCPWM0_CLOCKS51 PCLK_TCPWM0_CLOCKS52 PCLK_TCPWM0_CLOCKS53 PCLK_TCPWM0_CLOCKS54 PCLK_TCPWM0_CLOCKS55 PCLK_TCPWM0_CLOCKS56 PCLK_TCPWM0_CLOCKS57 PCLK_TCPWM0_CLOCKS58 PCLK_TCPWM0_CLOCKS59 PCLK_TCPWM0_CLOCKS60 PCLK_TCPWM0_CLOCKS61 PCLK_TCPWM0_CLOCKS62 PCLK_TCPWM0_CLOCKS256 PCLK_TCPWM0_CLOCKS257 PCLK_TCPWM0_CLOCKS258 PCLK_TCPWM0_CLOCKS259 PCLK_TCPWM0_CLOCKS260 PCLK_TCPWM0_CLOCKS261 PCLK_TCPWM0_CLOCKS262 PCLK_TCPWM0_CLOCKS263 PCLK_TCPWM0_CLOCKS264 PCLK_TCPWM0_CLOCKS265 PCLK_TCPWM0_CLOCKS266 PCLK_TCPWM0_CLOCKS267 PCLK_TCPWM0_CLOCKS512 PCLK_TCPWM0_CLOCKS513 PCLK_TCPWM0_CLOCKS514 PCLK_TCPWM0_CLOCKS515 PCLK_TCPWM0_CLOCKS516 PCLK_TCPWM0_CLOCKS517 PCLK_TCPWM0_CLOCKS518 PCLK_TCPWM0_CLOCKS519 unsigned char CY_SYSCLK_DIV_8_BIT CY_SYSCLK_DIV_16_BIT CY_SYSCLK_DIV_16_5_BIT CY_SYSCLK_DIV_24_5_BIT unsigned int CY_SYSCLK_SUCCESS CY_SYSCLK_BAD_PARAM CY_SYSCLK_TIMEOUT CY_SYSCLK_INVALID_STATE CY_SYSCLK_UNSUPPORTED_STATE en_clk_dst_t init_cycfg_clocks Component: ARM Compiler 6.16 Tool: armclang [5dfeb700] ../src/bsp/platforms/KIT-XMC7200\cycfg.c C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_cmsis_uv init_cycfg_all Component: ARM Compiler 6.16 Tool: armclang [5dfeb700] ../src/pdl/devices/COMPONENT_CAT1C/templates/COMPONENT_MTB\system_cm0plus.c C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_cmsis_uv SystemCoreClock unsigned int uint32_t cy_Hfclk0FreqHz cy_PeriClkFreqHz cy_delayFreqHz cy_delayFreqKhz cy_delayFreqMhz unsigned char uint8_t cy_delay32kMs IDENTITY CM7_0_STATUS FAST_0_CLOCK_CTL CM7_0_CTL RESERVED __ARRAY_SIZE_TYPE__ CM7_0_INT_STATUS RESERVED1 CM7_0_VECTOR_TABLE_BASE RESERVED2 CM7_0_NMI_CTL RESERVED3 UDB_PWR_CTL UDB_PWR_DELAY_CTL RESERVED4 TRC_DBG_CLOCK_CTL RESERVED5 CM7_1_STATUS FAST_1_CLOCK_CTL CM7_1_CTL RESERVED6 CM7_1_INT_STATUS RESERVED7 CM7_1_VECTOR_TABLE_BASE RESERVED8 CM7_1_NMI_CTL RESERVED9 CM0_CTL CM0_STATUS SLOW_CLOCK_CTL PERI_CLOCK_CTL MEM_CLOCK_CTL RESERVED10 CM0_INT0_STATUS CM0_INT1_STATUS CM0_INT2_STATUS CM0_INT3_STATUS CM0_INT4_STATUS CM0_INT5_STATUS CM0_INT6_STATUS CM0_INT7_STATUS CM0_VECTOR_TABLE_BASE RESERVED11 CM0_NMI_CTL RESERVED12 CM7_0_PWR_CTL CM7_0_PWR_DELAY_CTL RESERVED13 CM7_1_PWR_CTL CM7_1_PWR_DELAY_CTL RESERVED14 RAM0_CTL0 RAM0_STATUS RESERVED15 RAM0_PWR_MACRO_CTL RAM1_CTL0 RAM1_STATUS RAM1_PWR_CTL RESERVED16 RAM2_CTL0 RAM2_STATUS RAM2_PWR_CTL RESERVED17 RAM_PWR_DELAY_CTL ROM_CTL ECC_CTL RESERVED18 PRODUCT_ID RESERVED19 DP_STATUS AP_CTL RESERVED20 BUFF_CTL RESERVED21 SYSTICK_CTL RESERVED22 MBIST_STAT RESERVED23 CAL_SUP_SET CAL_SUP_CLR RESERVED24 CM0_PC_CTL RESERVED25 CM0_PC0_HANDLER CM0_PC1_HANDLER CM0_PC2_HANDLER CM0_PC3_HANDLER RESERVED26 PROTECTION RESERVED27 TRIM_ROM_CTL TRIM_RAM_CTL TRIM_RAM200_CTL TRIM_RAM350_CTL RESERVED28 CM0_SYSTEM_INT_CTL RESERVED29 CM7_0_SYSTEM_INT_CTL RESERVED30 CM7_1_SYSTEM_INT_CTL CPUSS_Type PWR_LVD_STATUS PWR_LVD_STATUS2 CLK_DSI_SELECT CLK_OUTPUT_FAST CLK_OUTPUT_SLOW CLK_CAL_CNT1 CLK_CAL_CNT2 SRSS_INTR SRSS_INTR_SET SRSS_INTR_MASK SRSS_INTR_MASKED PWR_CTL PWR_CTL2 PWR_HIBERNATE PWR_BUCK_CTL PWR_BUCK_CTL2 PWR_SSV_CTL PWR_SSV_STATUS PWR_LVD_CTL PWR_LVD_CTL2 PWR_REGHC_CTL PWR_REGHC_STATUS PWR_REGHC_CTL2 PWR_REGHC_CTL4 PWR_HIB_DATA PWR_PMIC_CTL PWR_PMIC_STATUS PWR_PMIC_CTL2 PWR_PMIC_CTL4 CLK_PATH_SELECT CLK_ROOT_SELECT CSV_HF CSV REF_CTL REF_LIMIT MON_CTL CSV_HF_CSV_Type CSV_HF_Type CLK_SELECT CLK_TIMER_CTL CLK_ILO0_CONFIG CLK_ILO1_CONFIG CLK_IMO_CONFIG CLK_ECO_CONFIG CLK_ECO_PRESCALE CLK_ECO_STATUS CLK_PILO_CONFIG CLK_FLL_CONFIG CLK_FLL_CONFIG2 CLK_FLL_CONFIG3 CLK_FLL_CONFIG4 CLK_FLL_STATUS CLK_ECO_CONFIG2 CLK_PLL_CONFIG CLK_PLL_STATUS CSV_REF_SEL CSV_REF CSV_REF_CSV_Type CSV_REF_Type CSV_LF CSV_LF_CSV_Type CSV_LF_Type CSV_ILO CSV_ILO_CSV_Type CSV_ILO_Type RES_CAUSE RES_CAUSE2 CLK_PLL400M CONFIG CONFIG2 CONFIG3 STATUS CLK_PLL400M_Type CLK_TRIM_ILO0_CTL PWR_TRIM_PWRSYS_CTL CLK_TRIM_PILO_CTL CLK_TRIM_PILO_CTL2 CLK_TRIM_PILO_CTL3 CLK_TRIM_ILO1_CTL MCWDT CTR CTL LOWER_LIMIT UPPER_LIMIT WARN_LIMIT CNT MCWDT_CTR_Type CPU_SELECT CTR2_CTL CTR2_CONFIG CTR2_CNT LOCK SERVICE INTR INTR_SET INTR_MASK INTR_MASKED MCWDT_Type WDT WDT_Type SRSS_Type SystemInit Cy_WDT_Disable Cy_SystemInit SystemCoreClockUpdate Cy_SysGetCM7Status Cy_SysEnableCM7 Cy_SysResetCM7 Cy_SysDisableCM7 Cy_SysRetainCM7 Cy_DefaultUserHandler clkHfPath pathFreqHz core regValue vectorTableOffset interruptState cmStatus Component: ARM Compiler 6.16 Tool: armclang [5dfeb700] ../src/pdl/drivers/source\cy_wdt_b.c C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_cmsis_uv unsigned char CY_WDT_LOW_UPPER_LIMIT_ACTION_NONE CY_WDT_LOW_UPPER_LIMIT_ACTION_RESET CY_WDT_WARN_ACTION_NONE CY_WDT_WARN_ACTION_INT unsigned int uint32_t CTL LOWER_LIMIT UPPER_LIMIT WARN_LIMIT CONFIG CNT RESERVED __ARRAY_SIZE_TYPE__ LOCK SERVICE RESERVED1 INTR INTR_SET INTR_MASK INTR_MASKED RESERVED2 WDT_Type PWR_LVD_STATUS PWR_LVD_STATUS2 CLK_DSI_SELECT CLK_OUTPUT_FAST CLK_OUTPUT_SLOW CLK_CAL_CNT1 CLK_CAL_CNT2 SRSS_INTR SRSS_INTR_SET SRSS_INTR_MASK SRSS_INTR_MASKED RESERVED3 PWR_CTL PWR_CTL2 PWR_HIBERNATE RESERVED4 PWR_BUCK_CTL PWR_BUCK_CTL2 PWR_SSV_CTL PWR_SSV_STATUS PWR_LVD_CTL PWR_LVD_CTL2 PWR_REGHC_CTL PWR_REGHC_STATUS PWR_REGHC_CTL2 RESERVED5 PWR_REGHC_CTL4 RESERVED6 PWR_HIB_DATA RESERVED7 PWR_PMIC_CTL PWR_PMIC_STATUS PWR_PMIC_CTL2 RESERVED8 PWR_PMIC_CTL4 RESERVED9 CLK_PATH_SELECT CLK_ROOT_SELECT RESERVED10 CSV_HF CSV REF_CTL REF_LIMIT MON_CTL CSV_HF_CSV_Type CSV_HF_Type CLK_SELECT CLK_TIMER_CTL CLK_ILO0_CONFIG CLK_ILO1_CONFIG RESERVED11 CLK_IMO_CONFIG CLK_ECO_CONFIG CLK_ECO_PRESCALE CLK_ECO_STATUS CLK_PILO_CONFIG RESERVED12 CLK_FLL_CONFIG CLK_FLL_CONFIG2 CLK_FLL_CONFIG3 CLK_FLL_CONFIG4 CLK_FLL_STATUS CLK_ECO_CONFIG2 RESERVED13 CLK_PLL_CONFIG RESERVED14 CLK_PLL_STATUS RESERVED15 CSV_REF_SEL RESERVED16 CSV_REF CSV_REF_CSV_Type CSV_REF_Type CSV_LF CSV_LF_CSV_Type CSV_LF_Type CSV_ILO CSV_ILO_CSV_Type CSV_ILO_Type RESERVED17 RES_CAUSE RES_CAUSE2 RESERVED18 CLK_PLL400M CONFIG2 CONFIG3 STATUS CLK_PLL400M_Type RESERVED19 CLK_TRIM_ILO0_CTL RESERVED20 PWR_TRIM_PWRSYS_CTL RESERVED21 CLK_TRIM_PILO_CTL CLK_TRIM_PILO_CTL2 CLK_TRIM_PILO_CTL3 RESERVED22 CLK_TRIM_ILO1_CTL RESERVED23 MCWDT CTR MCWDT_CTR_Type CPU_SELECT CTR2_CTL CTR2_CONFIG CTR2_CNT MCWDT_Type RESERVED24 WDT SRSS_Type Cy_WDT_Init Cy_WDT_Unlock Cy_WDT_Disable Cy_WDT_SetLowerLimit Cy_WDT_SetUpperLimit Cy_WDT_SetWarnLimit Cy_WDT_SetLowerAction Cy_WDT_SetUpperAction Cy_WDT_SetWarnAction Cy_WDT_Lock Cy_WDT_Locked _Bool Cy_WDT_ClearInterrupt Cy_WDT_ClearWatchdog Cy_WDT_SetService match action cy_en_wdt_lower_upper_action_t cy_en_wdt_warn_action_t Component: ARM Compiler 6.16 Tool: armclang [5dfeb700] ../src/pdl/drivers/source\cy_sysclk_v2.c C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_cmsis_uv cySysClkExtFreq unsigned int uint32_t clkCounting _Bool preventCounting clk1Count1 CY_SYSCLK_SUCCESS CY_SYSCLK_BAD_PARAM CY_SYSCLK_TIMEOUT CY_SYSCLK_INVALID_STATE CY_SYSCLK_UNSUPPORTED_STATE unsigned short PCLK_CPUSS_CLOCK_TRACE_IN PCLK_SMARTIO12_CLOCK PCLK_SMARTIO13_CLOCK PCLK_SMARTIO14_CLOCK PCLK_SMARTIO15_CLOCK PCLK_SMARTIO17_CLOCK PCLK_CANFD0_CLOCK_CAN0 PCLK_CANFD0_CLOCK_CAN1 PCLK_CANFD0_CLOCK_CAN2 PCLK_CANFD0_CLOCK_CAN3 PCLK_CANFD1_CLOCK_CAN0 PCLK_CANFD1_CLOCK_CAN1 PCLK_CANFD1_CLOCK_CAN2 PCLK_CANFD1_CLOCK_CAN3 PCLK_LIN0_CLOCK_CH_EN0 PCLK_LIN0_CLOCK_CH_EN1 PCLK_LIN0_CLOCK_CH_EN2 PCLK_LIN0_CLOCK_CH_EN3 PCLK_LIN0_CLOCK_CH_EN4 PCLK_LIN0_CLOCK_CH_EN5 PCLK_LIN0_CLOCK_CH_EN6 PCLK_LIN0_CLOCK_CH_EN7 PCLK_LIN0_CLOCK_CH_EN8 PCLK_LIN0_CLOCK_CH_EN9 PCLK_LIN0_CLOCK_CH_EN10 PCLK_LIN0_CLOCK_CH_EN11 PCLK_LIN0_CLOCK_CH_EN12 PCLK_LIN0_CLOCK_CH_EN13 PCLK_LIN0_CLOCK_CH_EN14 PCLK_LIN0_CLOCK_CH_EN15 PCLK_SCB0_CLOCK PCLK_SCB1_CLOCK PCLK_SCB2_CLOCK PCLK_SCB3_CLOCK PCLK_SCB4_CLOCK PCLK_SCB5_CLOCK PCLK_SCB6_CLOCK PCLK_SCB7_CLOCK PCLK_SCB8_CLOCK PCLK_SCB9_CLOCK PCLK_SCB10_CLOCK PCLK_PASS0_CLOCK_SAR0 PCLK_PASS0_CLOCK_SAR1 PCLK_PASS0_CLOCK_SAR2 PCLK_TCPWM0_CLOCKS0 PCLK_TCPWM0_CLOCKS1 PCLK_TCPWM0_CLOCKS2 PCLK_TCPWM0_CLOCKS3 PCLK_TCPWM0_CLOCKS4 PCLK_TCPWM0_CLOCKS5 PCLK_TCPWM0_CLOCKS6 PCLK_TCPWM0_CLOCKS7 PCLK_TCPWM0_CLOCKS8 PCLK_TCPWM0_CLOCKS9 PCLK_TCPWM0_CLOCKS10 PCLK_TCPWM0_CLOCKS11 PCLK_TCPWM0_CLOCKS12 PCLK_TCPWM0_CLOCKS13 PCLK_TCPWM0_CLOCKS14 PCLK_TCPWM0_CLOCKS15 PCLK_TCPWM0_CLOCKS16 PCLK_TCPWM0_CLOCKS17 PCLK_TCPWM0_CLOCKS18 PCLK_TCPWM0_CLOCKS19 PCLK_TCPWM0_CLOCKS20 PCLK_TCPWM0_CLOCKS21 PCLK_TCPWM0_CLOCKS22 PCLK_TCPWM0_CLOCKS23 PCLK_TCPWM0_CLOCKS24 PCLK_TCPWM0_CLOCKS25 PCLK_TCPWM0_CLOCKS26 PCLK_TCPWM0_CLOCKS27 PCLK_TCPWM0_CLOCKS28 PCLK_TCPWM0_CLOCKS29 PCLK_TCPWM0_CLOCKS30 PCLK_TCPWM0_CLOCKS31 PCLK_TCPWM0_CLOCKS32 PCLK_TCPWM0_CLOCKS33 PCLK_TCPWM0_CLOCKS34 PCLK_TCPWM0_CLOCKS35 PCLK_TCPWM0_CLOCKS36 PCLK_TCPWM0_CLOCKS37 PCLK_TCPWM0_CLOCKS38 PCLK_TCPWM0_CLOCKS39 PCLK_TCPWM0_CLOCKS40 PCLK_TCPWM0_CLOCKS41 PCLK_TCPWM0_CLOCKS42 PCLK_TCPWM0_CLOCKS43 PCLK_TCPWM0_CLOCKS44 PCLK_TCPWM0_CLOCKS45 PCLK_TCPWM0_CLOCKS46 PCLK_TCPWM0_CLOCKS47 PCLK_TCPWM0_CLOCKS48 PCLK_TCPWM0_CLOCKS49 PCLK_TCPWM0_CLOCKS50 PCLK_TCPWM0_CLOCKS51 PCLK_TCPWM0_CLOCKS52 PCLK_TCPWM0_CLOCKS53 PCLK_TCPWM0_CLOCKS54 PCLK_TCPWM0_CLOCKS55 PCLK_TCPWM0_CLOCKS56 PCLK_TCPWM0_CLOCKS57 PCLK_TCPWM0_CLOCKS58 PCLK_TCPWM0_CLOCKS59 PCLK_TCPWM0_CLOCKS60 PCLK_TCPWM0_CLOCKS61 PCLK_TCPWM0_CLOCKS62 PCLK_TCPWM0_CLOCKS256 PCLK_TCPWM0_CLOCKS257 PCLK_TCPWM0_CLOCKS258 PCLK_TCPWM0_CLOCKS259 PCLK_TCPWM0_CLOCKS260 PCLK_TCPWM0_CLOCKS261 PCLK_TCPWM0_CLOCKS262 PCLK_TCPWM0_CLOCKS263 PCLK_TCPWM0_CLOCKS264 PCLK_TCPWM0_CLOCKS265 PCLK_TCPWM0_CLOCKS266 PCLK_TCPWM0_CLOCKS267 PCLK_TCPWM0_CLOCKS512 PCLK_TCPWM0_CLOCKS513 PCLK_TCPWM0_CLOCKS514 PCLK_TCPWM0_CLOCKS515 PCLK_TCPWM0_CLOCKS516 PCLK_TCPWM0_CLOCKS517 PCLK_TCPWM0_CLOCKS518 PCLK_TCPWM0_CLOCKS519 unsigned char CY_SYSCLK_DIV_8_BIT CY_SYSCLK_DIV_16_BIT CY_SYSCLK_DIV_16_5_BIT CY_SYSCLK_DIV_24_5_BIT CY_SYSCLK_PUMP_IN_CLKPATH0 CY_SYSCLK_PUMP_IN_CLKPATH1 CY_SYSCLK_PUMP_IN_CLKPATH2 CY_SYSCLK_PUMP_IN_CLKPATH3 CY_SYSCLK_PUMP_IN_CLKPATH4 CY_SYSCLK_PUMP_IN_CLKPATH5 CY_SYSCLK_PUMP_IN_CLKPATH6 CY_SYSCLK_PUMP_IN_CLKPATH7 CY_SYSCLK_PUMP_IN_CLKPATH8 CY_SYSCLK_PUMP_IN_CLKPATH9 CY_SYSCLK_PUMP_IN_CLKPATH10 CY_SYSCLK_PUMP_IN_CLKPATH11 CY_SYSCLK_PUMP_IN_CLKPATH12 CY_SYSCLK_PUMP_IN_CLKPATH13 CY_SYSCLK_PUMP_IN_CLKPATH14 CY_SYSCLK_PUMP_IN_CLKPATH15 CY_SYSCLK_PUMP_NO_DIV CY_SYSCLK_PUMP_DIV_2 CY_SYSCLK_PUMP_DIV_4 CY_SYSCLK_PUMP_DIV_8 CY_SYSCLK_PUMP_DIV_16 CY_SYSCLK_BAK_IN_WCO CY_SYSCLK_BAK_IN_CLKLF CY_SYSCLK_BAK_IN_ILO CY_SYSCLK_BAK_IN_LPECO_PRESCALER CY_SYSCLK_BAK_IN_PILO CY_SYSCLK_CLKTIMER_IN_IMO CY_SYSCLK_CLKTIMER_IN_HF0_NODIV CY_SYSCLK_CLKTIMER_IN_HF0_DIV2 CY_SYSCLK_CLKTIMER_IN_HF0_DIV4 CY_SYSCLK_CLKTIMER_IN_HF0_DIV8 CY_SYSCLK_CLKLF_IN_ILO CY_SYSCLK_CLKLF_IN_WCO CY_SYSCLK_CLKLF_IN_ALTLF CY_SYSCLK_CLKLF_IN_PILO CY_SYSCLK_PERI_GROUP_SL_CTL CY_SYSCLK_CLKHF_IN_CLKPATH0 CY_SYSCLK_CLKHF_IN_CLKPATH1 CY_SYSCLK_CLKHF_IN_CLKPATH2 CY_SYSCLK_CLKHF_IN_CLKPATH3 CY_SYSCLK_CLKHF_IN_CLKPATH4 CY_SYSCLK_CLKHF_IN_CLKPATH5 CY_SYSCLK_CLKHF_IN_CLKPATH6 CY_SYSCLK_CLKHF_IN_CLKPATH7 CY_SYSCLK_CLKHF_IN_CLKPATH8 CY_SYSCLK_CLKHF_IN_CLKPATH9 CY_SYSCLK_CLKHF_IN_CLKPATH10 CY_SYSCLK_CLKHF_IN_CLKPATH11 CY_SYSCLK_CLKHF_IN_CLKPATH12 CY_SYSCLK_CLKHF_IN_CLKPATH13 CY_SYSCLK_CLKHF_IN_CLKPATH14 CY_SYSCLK_CLKHF_IN_CLKPATH15 CY_SYSCLK_CLKHF_NO_DIVIDE CY_SYSCLK_CLKHF_DIVIDE_BY_2 CY_SYSCLK_CLKHF_DIVIDE_BY_4 CY_SYSCLK_CLKHF_DIVIDE_BY_8 CY_SYSCLK_WCO_NOT_BYPASSED CY_SYSCLK_WCO_BYPASSED CY_SYSCLK_CLKPATH_IN_IMO CY_SYSCLK_CLKPATH_IN_EXT CY_SYSCLK_CLKPATH_IN_ECO CY_SYSCLK_CLKPATH_IN_ALTHF CY_SYSCLK_CLKPATH_IN_DSIMUX CY_SYSCLK_CLKPATH_IN_LPECO CY_SYSCLK_CLKPATH_IN_IHO CY_SYSCLK_CLKPATH_IN_DSI CY_SYSCLK_CLKPATH_IN_ILO CY_SYSCLK_CLKPATH_IN_WCO CY_SYSCLK_CLKPATH_IN_ALTLF CY_SYSCLK_CLKPATH_IN_PILO CY_SYSCLK_CLKPATH_IN_ILO1 CY_SYSCLK_FLL_CCO_RANGE0 CY_SYSCLK_FLL_CCO_RANGE1 CY_SYSCLK_FLL_CCO_RANGE2 CY_SYSCLK_FLL_CCO_RANGE3 CY_SYSCLK_FLL_CCO_RANGE4 CY_SYSCLK_FLLPLL_OUTPUT_AUTO CY_SYSCLK_FLLPLL_OUTPUT_AUTO1 CY_SYSCLK_FLLPLL_OUTPUT_INPUT CY_SYSCLK_FLLPLL_OUTPUT_OUTPUT CY_SYSCLK_MEAS_CLK_NC CY_SYSCLK_MEAS_CLK_ILO CY_SYSCLK_MEAS_CLK_WCO CY_SYSCLK_MEAS_CLK_BAK CY_SYSCLK_MEAS_CLK_ALTLF CY_SYSCLK_MEAS_CLK_LFCLK CY_SYSCLK_MEAS_CLK_IMO CY_SYSCLK_MEAS_CLK_SLPCTRL CY_SYSCLK_MEAS_CLK_PILO CY_SYSCLK_MEAS_CLK_ILO1 CY_SYSCLK_MEAS_CLK_ECO_PRESCALER CY_SYSCLK_MEAS_CLK_LPECO CY_SYSCLK_MEAS_CLK_LPECO_PRESCALER CY_SYSCLK_MEAS_CLK_MFO CY_SYSCLK_MEAS_CLK_FAST_CLKS CY_SYSCLK_MEAS_CLK_ECO CY_SYSCLK_MEAS_CLK_EXT CY_SYSCLK_MEAS_CLK_ALTHF CY_SYSCLK_MEAS_CLK_TIMERCLK CY_SYSCLK_MEAS_CLK_IHO CY_SYSCLK_MEAS_CLK_PWR CY_SYSCLK_MEAS_CLK_PATH_CLKS CY_SYSCLK_MEAS_CLK_PATH0 CY_SYSCLK_MEAS_CLK_PATH1 CY_SYSCLK_MEAS_CLK_PATH2 CY_SYSCLK_MEAS_CLK_PATH3 CY_SYSCLK_MEAS_CLK_PATH4 CY_SYSCLK_MEAS_CLK_PATH5 CY_SYSCLK_MEAS_CLK_PATH6 CY_SYSCLK_MEAS_CLK_PATH7 CY_SYSCLK_MEAS_CLK_PATH8 CY_SYSCLK_MEAS_CLK_PATH9 CY_SYSCLK_MEAS_CLK_PATH10 CY_SYSCLK_MEAS_CLK_PATH11 CY_SYSCLK_MEAS_CLK_PATH12 CY_SYSCLK_MEAS_CLK_PATH13 CY_SYSCLK_MEAS_CLK_PATH14 CY_SYSCLK_MEAS_CLK_PATH15 CY_SYSCLK_MEAS_CLK_CLKHFS CY_SYSCLK_MEAS_CLK_CLKHF0 CY_SYSCLK_MEAS_CLK_CLKHF1 CY_SYSCLK_MEAS_CLK_CLKHF2 CY_SYSCLK_MEAS_CLK_CLKHF3 CY_SYSCLK_MEAS_CLK_CLKHF4 CY_SYSCLK_MEAS_CLK_CLKHF5 CY_SYSCLK_MEAS_CLK_CLKHF6 CY_SYSCLK_MEAS_CLK_CLKHF7 CY_SYSCLK_MEAS_CLK_CLKHF8 CY_SYSCLK_MEAS_CLK_CLKHF9 CY_SYSCLK_MEAS_CLK_CLKHF10 CY_SYSCLK_MEAS_CLK_CLKHF11 CY_SYSCLK_MEAS_CLK_CLKHF12 CY_SYSCLK_MEAS_CLK_CLKHF13 CY_SYSCLK_MEAS_CLK_CLKHF14 CY_SYSCLK_MEAS_CLK_CLKHF15 CY_SYSCLK_MEAS_CLK_LAST_CLK CY_SYSPM_SUCCESS CY_SYSPM_BAD_PARAM CY_SYSPM_TIMEOUT CY_SYSPM_INVALID_STATE CY_SYSPM_CANCELED CY_SYSPM_SYSCALL_PENDING CY_SYSPM_FAIL CY_SYSPM_CHECK_READY CY_SYSPM_CHECK_FAIL CY_SYSPM_BEFORE_TRANSITION CY_SYSPM_AFTER_TRANSITION uint8_t DIV_CMD RESERVED __ARRAY_SIZE_TYPE__ CLOCK_CTL DIV_8_CTL DIV_16_CTL DIV_16_5_CTL DIV_24_5_CTL RESERVED1 PERI_PCLK_GR_Type GR PERI_PCLK_Type en_clk_dst_t IDENTITY CM7_0_STATUS FAST_0_CLOCK_CTL CM7_0_CTL CM7_0_INT_STATUS CM7_0_VECTOR_TABLE_BASE RESERVED2 CM7_0_NMI_CTL RESERVED3 UDB_PWR_CTL UDB_PWR_DELAY_CTL RESERVED4 TRC_DBG_CLOCK_CTL RESERVED5 CM7_1_STATUS FAST_1_CLOCK_CTL CM7_1_CTL RESERVED6 CM7_1_INT_STATUS RESERVED7 CM7_1_VECTOR_TABLE_BASE RESERVED8 CM7_1_NMI_CTL RESERVED9 CM0_CTL CM0_STATUS SLOW_CLOCK_CTL PERI_CLOCK_CTL MEM_CLOCK_CTL RESERVED10 CM0_INT0_STATUS CM0_INT1_STATUS CM0_INT2_STATUS CM0_INT3_STATUS CM0_INT4_STATUS CM0_INT5_STATUS CM0_INT6_STATUS CM0_INT7_STATUS CM0_VECTOR_TABLE_BASE RESERVED11 CM0_NMI_CTL RESERVED12 CM7_0_PWR_CTL CM7_0_PWR_DELAY_CTL RESERVED13 CM7_1_PWR_CTL CM7_1_PWR_DELAY_CTL RESERVED14 RAM0_CTL0 RAM0_STATUS RESERVED15 RAM0_PWR_MACRO_CTL RAM1_CTL0 RAM1_STATUS RAM1_PWR_CTL RESERVED16 RAM2_CTL0 RAM2_STATUS RAM2_PWR_CTL RESERVED17 RAM_PWR_DELAY_CTL ROM_CTL ECC_CTL RESERVED18 PRODUCT_ID RESERVED19 DP_STATUS AP_CTL RESERVED20 BUFF_CTL RESERVED21 SYSTICK_CTL RESERVED22 MBIST_STAT RESERVED23 CAL_SUP_SET CAL_SUP_CLR RESERVED24 CM0_PC_CTL RESERVED25 CM0_PC0_HANDLER CM0_PC1_HANDLER CM0_PC2_HANDLER CM0_PC3_HANDLER RESERVED26 PROTECTION RESERVED27 TRIM_ROM_CTL TRIM_RAM_CTL TRIM_RAM200_CTL TRIM_RAM350_CTL RESERVED28 CM0_SYSTEM_INT_CTL RESERVED29 CM7_0_SYSTEM_INT_CTL RESERVED30 CM7_1_SYSTEM_INT_CTL CPUSS_Type PWR_LVD_STATUS PWR_LVD_STATUS2 CLK_DSI_SELECT CLK_OUTPUT_FAST CLK_OUTPUT_SLOW CLK_CAL_CNT1 CLK_CAL_CNT2 SRSS_INTR SRSS_INTR_SET SRSS_INTR_MASK SRSS_INTR_MASKED PWR_CTL PWR_CTL2 PWR_HIBERNATE PWR_BUCK_CTL PWR_BUCK_CTL2 PWR_SSV_CTL PWR_SSV_STATUS PWR_LVD_CTL PWR_LVD_CTL2 PWR_REGHC_CTL PWR_REGHC_STATUS PWR_REGHC_CTL2 PWR_REGHC_CTL4 PWR_HIB_DATA PWR_PMIC_CTL PWR_PMIC_STATUS PWR_PMIC_CTL2 PWR_PMIC_CTL4 CLK_PATH_SELECT CLK_ROOT_SELECT CSV_HF CSV REF_CTL REF_LIMIT MON_CTL CSV_HF_CSV_Type CSV_HF_Type CLK_SELECT CLK_TIMER_CTL CLK_ILO0_CONFIG CLK_ILO1_CONFIG CLK_IMO_CONFIG CLK_ECO_CONFIG CLK_ECO_PRESCALE CLK_ECO_STATUS CLK_PILO_CONFIG CLK_FLL_CONFIG CLK_FLL_CONFIG2 CLK_FLL_CONFIG3 CLK_FLL_CONFIG4 CLK_FLL_STATUS CLK_ECO_CONFIG2 CLK_PLL_CONFIG CLK_PLL_STATUS CSV_REF_SEL CSV_REF CSV_REF_CSV_Type CSV_REF_Type CSV_LF CSV_LF_CSV_Type CSV_LF_Type CSV_ILO CSV_ILO_CSV_Type CSV_ILO_Type RES_CAUSE RES_CAUSE2 CLK_PLL400M CONFIG CONFIG2 CONFIG3 STATUS CLK_PLL400M_Type CLK_TRIM_ILO0_CTL PWR_TRIM_PWRSYS_CTL CLK_TRIM_PILO_CTL CLK_TRIM_PILO_CTL2 CLK_TRIM_PILO_CTL3 CLK_TRIM_ILO1_CTL MCWDT CTR CTL LOWER_LIMIT UPPER_LIMIT WARN_LIMIT CNT MCWDT_CTR_Type CPU_SELECT CTR2_CTL CTR2_CONFIG CTR2_CNT LOCK SERVICE INTR INTR_SET INTR_MASK INTR_MASKED MCWDT_Type WDT WDT_Type SRSS_Type cy_en_clkpump_in_sources_t cy_en_clkpump_divide_t RTC_RW CAL_CTL RTC_TIME RTC_DATE ALM1_TIME ALM1_DATE ALM2_TIME ALM2_DATE PMIC_CTL RESET LPECO_CTL LPECO_PRESCALE LPECO_STATUS BREG BACKUP_Type cy_en_clkbak_in_sources_t cy_en_clktimer_in_sources_t cy_en_clklf_in_sources_t SL_CTL PERI_GR_Type TIMEOUT_CTL TR_CMD TR_GR TR_CTL PERI_TR_GR_Type TR_1TO1_GR PERI_TR_1TO1_GR_Type PERI_Type cy_en_clkhf_in_sources_t cy_en_clkhf_dividers_t cy_en_clkpath_in_sources_t long long unsigned int uint64_t uint16_t cy_en_fll_pll_output_mode_t cy_en_fll_cco_ranges_t int int32_t Cy_SysClk_PeriPclkSetDivider cy_en_sysclk_status_t Cy_SysClk_PeriPclkGetDivider Cy_SysClk_PeriPclkSetFracDivider Cy_SysClk_PeriPclkGetFracDivider Cy_SysClk_PeriPclkAssignDivider Cy_SysClk_PeriPclkGetAssignedDivider Cy_SysClk_PeriPclkEnableDivider Cy_SysClk_PeriPclkDisableDivider Cy_SysClk_PeriPclkEnablePhaseAlignDivider Cy_SysClk_PeriphDisableDivider Cy_SysClk_PeriPclkGetDividerEnabled Cy_SysClk_PeriphSetDivider Cy_SysClk_PeriphGetDivider Cy_SysClk_PeriphSetFracDivider Cy_SysClk_PeriphGetFracDivider Cy_SysClk_PeriphAssignDivider Cy_SysClk_PeriphGetAssignedDivider Cy_SysClk_PeriphEnableDivider Cy_SysClk_PeriphEnablePhaseAlignDivider Cy_SysClk_PeriphGetDividerEnabled Cy_SysClk_ClkSlowGetFrequency Cy_SysClk_ClkPeriGetFrequency Cy_SysClk_ClkSlowGetDivider Cy_SysClk_ClkSlowSetDivider Cy_SysClk_ClkPumpSetSource Cy_SysClk_ClkPumpGetSource Cy_SysClk_ClkPumpSetDivider Cy_SysClk_ClkPumpGetDivider Cy_SysClk_ClkPumpIsEnabled Cy_SysClk_ClkPumpEnable Cy_SysClk_ClkPumpDisable Cy_SysClk_ClkPumpGetFrequency Cy_SysClk_ClkPathGetFrequency Cy_SysClk_ClkBakSetSource Cy_SysClk_ClkBakGetSource Cy_SysClk_ClkTimerSetSource Cy_SysClk_ClkTimerGetSource Cy_SysClk_ClkTimerSetDivider Cy_SysClk_ClkTimerGetDivider Cy_SysClk_ClkTimerEnable Cy_SysClk_ClkTimerDisable Cy_SysClk_ClkLfSetSource Cy_SysClk_ClkLfGetSource Cy_SysClk_ClkHfGetFrequency Cy_SysClk_ClkPeriGetDivider Cy_SysClk_ClkPeriSetDivider Cy_SysClk_PeriGroupSetDivider Cy_SysClk_PeriGroupGetDivider Cy_SysClk_PeriGroupSetSlaveCtl Cy_SysClk_PeriGroupGetSlaveCtl Cy_SysClk_IsPeriGroupSlaveCtlSet Cy_SysClk_ClkFastGetFrequency Cy_SysClk_ClkFastGetDivider Cy_SysClk_ClkFastSetDivider Cy_SysClk_ClkHfEnable Cy_SysClk_ClkHfIsEnabled Cy_SysClk_ClkHfDisable Cy_SysClk_ClkHfSetSource Cy_SysClk_ClkHfGetSource Cy_SysClk_ClkHfSetDivider Cy_SysClk_ClkHfGetDivider Cy_SysClk_ClkHfDirectSel Cy_SysClk_IsClkHfDirectSelEnabled Cy_SysClk_MfoEnable Cy_SysClk_MfoIsEnabled Cy_SysClk_MfoDisable Cy_SysClk_WcoEnable Cy_SysClk_WcoOkay Cy_SysClk_WcoDisable Cy_SysClk_WcoBypass Cy_SysClk_PiloEnable Cy_SysClk_PiloBackupEnable Cy_SysClk_PiloIsEnabled Cy_SysClk_PiloDisable Cy_SysClk_PiloBackupDisable Cy_SysClk_AltHfGetFrequency Cy_SysClk_AltHfEnable Cy_SysClk_IsAltHfEnabled Cy_SysClk_AltLfGetFrequency Cy_SysClk_AltLfIsEnabled Cy_SysClk_IloEnable Cy_SysClk_IloDisable Cy_SysClk_IloIsEnabled Cy_SysClk_IloHibernateOn Cy_SysClk_IloSrcEnable Cy_SysClk_IloSrcDisable Cy_SysClk_IloSrcIsEnabled Cy_SysClk_IloSrcHibernateOn Cy_SysClk_ExtClkSetFrequency Cy_SysClk_ExtClkGetFrequency Cy_SysClk_EcoDisable Cy_SysClk_EcoGetStatus Cy_SysClk_EcoBleGetStatus Cy_SysClk_EcoConfigure Cy_SysClk_EcoEnable Cy_SysClk_EcoGetFrequency Cy_SysClk_EcoPrescaleConfigure Cy_SysClk_IhoIsEnabled Cy_SysClk_IhoDisable Cy_SysClk_IhoEnable Cy_SysClk_ClkPathSetSource Cy_SysClk_ClkPathGetSource Cy_SysClk_ClkPathMuxGetFrequency Cy_SysClk_FllGetConfiguration Cy_SysClk_FllIsEnabled Cy_SysClk_PllGetConfiguration Cy_SysClk_PllIsEnabled Cy_SysClk_FllLocked Cy_SysClk_FllDisable Cy_SysClk_FllOutputDividerEnable Cy_SysClk_FllConfigure Cy_SysClk_FllManualConfigure Cy_SysClk_FllEnable Cy_SysClk_FllGetFrequency Cy_SysClk_Pll400MIsEnabled Cy_SysClk_Pll400MLocked Cy_SysClk_Pll400MLostLock Cy_SysClk_Pll400MDisable Cy_SysClk_Pll400MConfigure Cy_SysClk_Pll400MGetConfiguration Cy_SysClk_Pll400MManualConfigure Cy_SysClk_Pll400MEnable Cy_SysClk_Pll200MIsEnabled Cy_SysClk_Pll200MLocked Cy_SysClk_Pll200MLostLock Cy_SysClk_Pll200MDisable Cy_SysClk_Pll200MConfigure Cy_SysClk_Pll200MGetConfiguration Cy_SysClk_Pll200MManualConfigure Cy_SysClk_Pll200MEnable Cy_SysClk_PllLocked Cy_SysClk_PllLostLock Cy_SysClk_PllDisable Cy_SysClk_PllConfigure Cy_SysClk_PllManualConfigure Cy_SysClk_PllEnable Cy_SysClk_ClkMeasurementCountersDone Cy_SysClk_StartClkMeasurementCounters Cy_SysClk_ClkMeasurementCountersGetFreq Cy_SysClk_PiloTrim Cy_SysClk_PiloInitialTrim Cy_SysClk_PiloUpdateTrimStep Cy_SysClk_PiloSetTrim Cy_SysClk_PiloGetTrim Cy_SysClk_IloTrim Cy_SysClk_IloSetTrim Cy_SysClk_IloGetTrim Cy_SysClk_DeepSleepCallback cy_en_syspm_status_t Cy_SysClk_PeriphGetFrequency Cy_SysClk_PeriPclkGetFrequency Cy_Sysclk_PeriPclkGetClkHfNum ipBlock dividerType cy_en_divider_types_t dividerNum dividerValue retVal instNum grpNum dividerIntValue dividerFracValue periNum dividerTypePA dividerNumPA locFreq locDiv divider source fllCfg fllMult refDiv ccoRange enableOutputDiv lockTolerance igain pgain settlingCount outputMode cco_Freq cy_stc_fll_manual_config_t pllcfg feedbackDiv referenceDiv outputDiv lfMode fracDiv fracDitherEn fracEn sscgDepth sscgRate sscgEn cy_stc_pll_manual_config_t clkPath enabled oDiv rDiv fDiv freq clkHf pDiv path groupNum slaveCtl cy_en_peri_grp_sl_ctl_num_t value slaveMsk clkFastNum intDiv enable deepSleepEnable timeoutus bypass cy_en_wco_bypass_modes_t on iloNum cSum esr driveLevel frac_div int_div config tempReg inputFreq outputFreq wcoSource ccoFreq locpgain locigain kcco ki_p cmp res mlt fref divval altval trimSteps margin zeroTimeout pllNum manualConfig cy_stc_pll_config_t foutBest q p fvco out fout clock1 cy_en_meas_clks_t count1 clock2 clkOutputFastMask clkOutputSlowMask clkOutputFastVal clkOutputSlowVal measuredClock refClkFreq isMeasurementValid piloFreq trimVal iloFreq callbackParams base context cy_stc_syspm_callback_params_t mode cy_en_syspm_callback_mode_t integer hfNum locFrac peri1GrpToHfArray peri0GrpToHfArray Component: ARM Compiler 6.16 Tool: armclang [5dfeb700] ../src/pdl/drivers/source\cy_gpio.c C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_cmsis_uv unsigned int CY_GPIO_SUCCESS CY_GPIO_BAD_PARAM unsigned char HSIOM_SEL_GPIO HSIOM_SEL_GPIO_DSI HSIOM_SEL_DSI_DSI HSIOM_SEL_DSI_GPIO HSIOM_SEL_AMUXA HSIOM_SEL_AMUXB HSIOM_SEL_AMUXA_DSI HSIOM_SEL_AMUXB_DSI HSIOM_SEL_ACT_0 HSIOM_SEL_ACT_1 HSIOM_SEL_ACT_2 HSIOM_SEL_ACT_3 HSIOM_SEL_DS_0 HSIOM_SEL_DS_1 HSIOM_SEL_DS_2 HSIOM_SEL_DS_3 HSIOM_SEL_ACT_4 HSIOM_SEL_ACT_5 HSIOM_SEL_ACT_6 HSIOM_SEL_ACT_7 HSIOM_SEL_ACT_8 HSIOM_SEL_ACT_9 HSIOM_SEL_ACT_10 HSIOM_SEL_ACT_11 HSIOM_SEL_ACT_12 HSIOM_SEL_ACT_13 HSIOM_SEL_ACT_14 HSIOM_SEL_ACT_15 HSIOM_SEL_DS_4 HSIOM_SEL_DS_5 HSIOM_SEL_DS_6 HSIOM_SEL_DS_7 P6_3_SMIF0_SPIHB_CLK P6_5_SMIF0_SPIHB_SELECT0 P7_0_SMIF0_SPIHB_SELECT1 P7_1_SMIF0_SPIHB_DATA0 P7_2_SMIF0_SPIHB_DATA1 P7_3_SMIF0_SPIHB_DATA2 P7_4_SMIF0_SPIHB_DATA3 P7_5_SMIF0_SPIHB_DATA4 P8_0_SMIF0_SPIHB_DATA5 P8_1_SMIF0_SPIHB_DATA6 P8_2_SMIF0_SPIHB_DATA7 AMUX_SPLIT_CTL_0 AMUX_SPLIT_CTL_1 AMUX_SPLIT_CTL_2 CY_GPIO_AMUX_OPENALL CY_GPIO_AMUX_L CY_GPIO_AMUX_R CY_GPIO_AMUX_LR CY_GPIO_AMUX_G CY_GPIO_AMUX_GL CY_GPIO_AMUX_GR CY_GPIO_AMUX_GLR CY_GPIO_AMUXBUSA CY_GPIO_AMUXBUSB uint32_t OUT OUT_CLR OUT_SET OUT_INV IN INTR INTR_MASK INTR_MASKED INTR_SET RESERVED __ARRAY_SIZE_TYPE__ INTR_CFG CFG CFG_IN CFG_OUT CFG_SIO RESERVED1 CFG_IN_AUTOLVL RESERVED2 GPIO_PRT_Type PORT_SEL0 PORT_SEL1 HSIOM_PRT_Type PRT AMUX_SPLIT_CTL MONITOR_CTL_0 MONITOR_CTL_1 MONITOR_CTL_2 MONITOR_CTL_3 ALT_JTAG_EN HSIOM_Type cy_en_gpio_amuxconnect_t en_hsiom_sel_t Cy_GPIO_Pin_Init cy_en_gpio_status_t Cy_GPIO_SetHSIOM Cy_GPIO_SetDrivemode Cy_GPIO_SetInterruptEdge Cy_GPIO_SetInterruptMask Cy_GPIO_SetVtrip Cy_GPIO_Write Cy_GPIO_Port_Init Cy_GPIO_Pin_FastInit Cy_GPIO_Port_Deinit Cy_GPIO_SetAmuxSplit Cy_GPIO_GetAmuxSplit Cy_GPIO_GetHSIOM Cy_GPIO_Read Cy_GPIO_ReadOut Cy_GPIO_Set Cy_GPIO_Clr Cy_GPIO_Inv Cy_GPIO_GetDrivemode Cy_GPIO_GetVtrip Cy_GPIO_SetVtripAuto Cy_GPIO_GetVtripAuto Cy_GPIO_SetSlewRate Cy_GPIO_GetSlewRate Cy_GPIO_SetDriveSel Cy_GPIO_GetDriveSel Cy_GPIO_SetVregEn Cy_GPIO_GetVregEn Cy_GPIO_SetIbufMode Cy_GPIO_GetIbufMode Cy_GPIO_SetVtripSel Cy_GPIO_GetVtripSel Cy_GPIO_SetVrefSel Cy_GPIO_GetVrefSel Cy_GPIO_SetVohSel Cy_GPIO_GetVohSel Cy_GPIO_GetInterruptStatus Cy_GPIO_ClearInterrupt Cy_GPIO_GetInterruptMask Cy_GPIO_GetInterruptStatusMasked Cy_GPIO_SetSwInterrupt Cy_GPIO_GetInterruptEdge Cy_GPIO_SetFilter Cy_GPIO_GetFilter base pinNum config outVal driveMode hsiom intEdge intMask vtrip slewRate driveSel vregEn ibufMode vtripSel vrefSel vohSel cy_stc_gpio_pin_config_t status maskCfgOut tempReg tempReg2 value portNum portAddrHSIOM hsiomReg pinLoc prtCfg intrCfg intrMask cfgIn outMask out cfg cfgOut cfgSIO sel0Active sel1Active cy_stc_gpio_prt_config_t baseHSIOM switchCtrl cy_en_amux_split_t amuxConnect amuxBus cy_en_gpio_amuxselect_t tmpReg retVal returnValue cfgSio prtIntr intrSet Component: ARM Compiler 6.16 Tool: armclang [5dfeb700] ../src/pdl/devices/COMPONENT_CAT1C/source\cy_device.c C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_cmsis_uv cy_device hsiomBase unsigned int uint32_t gpioBase dwVersion unsigned char uint8_t cpussDw0ChNr cpussDw1ChNr epMonitorNr dwChOffset unsigned short uint16_t dwChSize dwChCtlPrioPos dwChCtlPreemptablePos dwStatusChIdxPos dwStatusChIdxMsk tcpwmCC1Present tcpwmAMCPresent tcpwmSMCPrecent cy_stc_device_t cy_deviceIpBlockCfgPlayer Cy_PDL_Init device Component: ARM Compiler 6.16 Tool: armclang [5dfeb700] ../src/pdl/drivers/source\cy_syslib.c C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_cmsis_uv cy_assertFileName char char_t __ARRAY_SIZE_TYPE__ cy_assertLine unsigned int uint32_t cy_faultFrame r0 r1 r2 r3 r12 lr pc psr cy_stc_fault_frame_t CY_SYSLIB_SUCCESS CY_SYSLIB_BAD_PARAM CY_SYSLIB_TIMEOUT CY_SYSLIB_INVALID_STATE CY_SYSLIB_UNKNOWN CTL RESERVED RTC_RW CAL_CTL STATUS RTC_TIME RTC_DATE ALM1_TIME ALM1_DATE ALM2_TIME ALM2_DATE INTR INTR_SET INTR_MASK INTR_MASKED RESERVED1 PMIC_CTL RESET RESERVED2 LPECO_CTL LPECO_PRESCALE LPECO_STATUS RESERVED3 BREG BACKUP_Type PWR_LVD_STATUS PWR_LVD_STATUS2 CLK_DSI_SELECT CLK_OUTPUT_FAST CLK_OUTPUT_SLOW CLK_CAL_CNT1 CLK_CAL_CNT2 SRSS_INTR SRSS_INTR_SET SRSS_INTR_MASK SRSS_INTR_MASKED PWR_CTL PWR_CTL2 PWR_HIBERNATE RESERVED4 PWR_BUCK_CTL PWR_BUCK_CTL2 PWR_SSV_CTL PWR_SSV_STATUS PWR_LVD_CTL PWR_LVD_CTL2 PWR_REGHC_CTL PWR_REGHC_STATUS PWR_REGHC_CTL2 RESERVED5 PWR_REGHC_CTL4 RESERVED6 PWR_HIB_DATA RESERVED7 PWR_PMIC_CTL PWR_PMIC_STATUS PWR_PMIC_CTL2 RESERVED8 PWR_PMIC_CTL4 RESERVED9 CLK_PATH_SELECT CLK_ROOT_SELECT RESERVED10 CSV_HF CSV REF_CTL REF_LIMIT MON_CTL CSV_HF_CSV_Type CSV_HF_Type CLK_SELECT CLK_TIMER_CTL CLK_ILO0_CONFIG CLK_ILO1_CONFIG RESERVED11 CLK_IMO_CONFIG CLK_ECO_CONFIG CLK_ECO_PRESCALE CLK_ECO_STATUS CLK_PILO_CONFIG RESERVED12 CLK_FLL_CONFIG CLK_FLL_CONFIG2 CLK_FLL_CONFIG3 CLK_FLL_CONFIG4 CLK_FLL_STATUS CLK_ECO_CONFIG2 RESERVED13 CLK_PLL_CONFIG RESERVED14 CLK_PLL_STATUS RESERVED15 CSV_REF_SEL RESERVED16 CSV_REF CSV_REF_CSV_Type CSV_REF_Type CSV_LF CSV_LF_CSV_Type CSV_LF_Type CSV_ILO CSV_ILO_CSV_Type CSV_ILO_Type RESERVED17 RES_CAUSE RES_CAUSE2 RESERVED18 CLK_PLL400M CONFIG CONFIG2 CONFIG3 CLK_PLL400M_Type RESERVED19 CLK_TRIM_ILO0_CTL RESERVED20 PWR_TRIM_PWRSYS_CTL RESERVED21 CLK_TRIM_PILO_CTL CLK_TRIM_PILO_CTL2 CLK_TRIM_PILO_CTL3 RESERVED22 CLK_TRIM_ILO1_CTL RESERVED23 MCWDT CTR LOWER_LIMIT UPPER_LIMIT WARN_LIMIT CNT MCWDT_CTR_Type CPU_SELECT CTR2_CTL CTR2_CONFIG CTR2_CNT LOCK SERVICE MCWDT_Type RESERVED24 WDT WDT_Type SRSS_Type Cy_SysLib_Delay Cy_SysLib_DelayUs Cy_SysLib_Rtos_Delay Cy_SysLib_Rtos_DelayUs Cy_SysLib_Halt Cy_SysLib_AssertFailed Cy_SysLib_ResetBackupDomain cy_en_syslib_status_t Cy_SysLib_GetResetStatus Cy_SysLib_GetResetReason Cy_SysLib_ClearResetReason Cy_SysLib_FaultHandler Cy_SysLib_ProcessingFault Cy_SysLib_AsmInfiniteLoop Cy_SysLib_SetWaitStates Cy_SysLib_GetDeviceRevision unsigned char uint8_t Cy_SysLib_GetDevice unsigned short uint16_t milliseconds microseconds reason file line retVal faultStackAddr ulpMode _Bool clkHfMHz Component: ARM Compiler 6.16 Tool: armclang [5dfeb700] ../src/pdl/drivers/source\cy_smif_sfdp.c C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_cmsis_uv unsigned int CY_SMIF_SUCCESS CY_SMIF_CMD_FIFO_FULL CY_SMIF_EXCEED_TIMEOUT CY_SMIF_NO_QE_BIT CY_SMIF_BAD_PARAM CY_SMIF_NO_SFDP_SUPPORT CY_SMIF_NOT_HYBRID_MEM CY_SMIF_SFDP_CORRUPTED_TABLE CY_SMIF_SFDP_SS0_FAILED CY_SMIF_SFDP_SS1_FAILED CY_SMIF_SFDP_SS2_FAILED CY_SMIF_SFDP_SS3_FAILED CY_SMIF_CMD_NOT_FOUND CY_SMIF_SFDP_BUFFER_INSUFFICIENT CY_SMIF_NO_OE_BIT CY_SMIF_BUSY unsigned char CY_SMIF_SLAVE_SELECT_0 CY_SMIF_SLAVE_SELECT_1 CY_SMIF_SLAVE_SELECT_2 CY_SMIF_SLAVE_SELECT_3 CY_SMIF_DATA_SEL0 CY_SMIF_DATA_SEL1 CY_SMIF_DATA_SEL2 CY_SMIF_DATA_SEL3 CY_SMIF_WIDTH_SINGLE CY_SMIF_WIDTH_DUAL CY_SMIF_WIDTH_QUAD CY_SMIF_WIDTH_OCTAL CY_SMIF_WIDTH_NA CY_SMIF_SDR CY_SMIF_DDR CY_SMIF_NOT_PRESENT CY_SMIF_PRESENT_1BYTE CY_SMIF_PRESENT_2BYTE CY_SMIF_100MHZ_OPERATION CY_SMIF_133MHZ_OPERATION CY_SMIF_166MHZ_OPERATION CY_SMIF_200MHZ_OPERATION CY_SMIF_MERGE_TIMEOUT_1_CYCLE CY_SMIF_MERGE_TIMEOUT_16_CYCLES CY_SMIF_MERGE_TIMEOUT_256_CYCLES CY_SMIF_MERGE_TIMEOUT_4096_CYCLES CY_SMIF_MERGE_TIMEOUT_65536_CYCLES CY_SMIF_SFDP_QER_0 CY_SMIF_SFDP_QER_1 CY_SMIF_SFDP_QER_2 CY_SMIF_SFDP_QER_3 CY_SMIF_SFDP_QER_4 CY_SMIF_SFDP_QER_5 CY_SMIF_SFDP_QER_6 PROTOCOL_MODE_1S_1S_1S PROTOCOL_MODE_1S_1S_2S PROTOCOL_MODE_1S_2S_2S PROTOCOL_MODE_1S_1S_4S PROTOCOL_MODE_1S_4S_4S PROTOCOL_MODE_1S_4D_4D PROTOCOL_MODE_1S_1S_8S PROTOCOL_MODE_1S_8S_8S PROTOCOL_MODE_8D_8D_8D PROTOCOL_MODE_WRONG uint8_t cy_en_smif_qer_t uint32_t CTL STATUS RESERVED __ARRAY_SIZE_TYPE__ INT_CLOCK_DELAY_TAP_SEL0 INT_CLOCK_DELAY_TAP_SEL1 DLP RESERVED1 DL_STATUS0 DL_STATUS1 RESERVED2 DELAY_TAP_SEL RESERVED3 TX_CMD_FIFO_STATUS RESERVED4 TX_CMD_FIFO_WR RESERVED5 TX_DATA_FIFO_CTL TX_DATA_FIFO_STATUS RESERVED6 TX_DATA_FIFO_WR1 TX_DATA_FIFO_WR2 TX_DATA_FIFO_WR4 TX_DATA_FIFO_WR1ODD RESERVED7 RX_DATA_MMIO_FIFO_CTL RX_DATA_MMIO_FIFO_STATUS RX_DATA_FIFO_STATUS RESERVED8 RX_DATA_MMIO_FIFO_RD1 RX_DATA_MMIO_FIFO_RD2 RX_DATA_MMIO_FIFO_RD4 RESERVED9 RX_DATA_MMIO_FIFO_RD1_SILENT RESERVED10 SLOW_CA_CTL RESERVED11 SLOW_CA_CMD RESERVED12 FAST_CA_CTL RESERVED13 FAST_CA_CMD RESERVED14 CRYPTO_CMD RESERVED15 CRYPTO_INPUT0 CRYPTO_INPUT1 CRYPTO_INPUT2 CRYPTO_INPUT3 RESERVED16 CRYPTO_KEY0 CRYPTO_KEY1 CRYPTO_KEY2 CRYPTO_KEY3 RESERVED17 CRYPTO_OUTPUT0 CRYPTO_OUTPUT1 CRYPTO_OUTPUT2 CRYPTO_OUTPUT3 RESERVED18 CRC_CMD RESERVED19 CRC_INPUT0 CRC_INPUT1 RESERVED20 CRC_OUTPUT RESERVED21 INTR INTR_SET INTR_MASK INTR_MASKED RESERVED22 DEVICE ADDR MASK ADDR_CTL RD_STATUS RD_CMD_CTL RD_ADDR_CTL RD_MODE_CTL RD_DUMMY_CTL RD_DATA_CTL RD_CRC_CTL RD_BOUND_CTL WR_CMD_CTL WR_ADDR_CTL WR_MODE_CTL WR_DUMMY_CTL WR_DATA_CTL WR_CRC_CTL SMIF_DEVICE_Type SMIF_Type _Bool unsigned short uint16_t Cy_SMIF_MemInitSfdpMode cy_en_smif_status_t SfdpReadBuffer SfdpFindParameterTableAddress SfdpGetEraseSizeAndCmd SfdpGetMemoryDensity SfdpGetNumOfAddrBytes SfdpSetWriteEnableCommand SfdpSetWriteDisableCommand SfdpSetWipStatusRegisterCommand SfdpGetQuadEnableParameters SfdpSetChipEraseCommand SfdpGetPageSize SfdpGetChipEraseTime SfdpGetPageProgramTime SfdpGetReadCmdParams cy_en_smif_protocol_mode_t SfdpEnterFourByteAddressing GetOctalDDRParams GetOctalSDRParams SfdpGetReadFourBytesCmd SfdpGetProgramFourBytesCmd SfdpGetSectorEraseCommand SfdpSetProgramCommand_1_1_1 SfdpGetEraseTime SfdpPopulateRegionInfo Cy_SMIF_GetDeviceBySlot XipRegInit Cy_SMIF_MemSfdpDetect SfdpFindParameterHeader Cy_SMIF_PackBytesArray SfdpGetReadCmd_1S_4D_4D SfdpGetReadCmd_1_4_4 SfdpGetReadCmd_1_1_4 SfdpGetReadCmd_1_2_2 SfdpGetReadCmd_1_1_2 SfdpGetReadCmd_1_1_1 SfdpSetVariableLatencyCmd ValueToByteArray Cy_SMIF_MemCmdWriteRegister ByteArrayToValue SfdpGetReadCmd_1_8_8 SfdpSetProgramCommandFourBytes_1_4_4 SfdpSetProgramCommandFourBytes_1_1_4 SfdpSetProgramCommandFourBytes_1_1_1 ReadAnyReg sfdpBuffer sfdpAddress addr4ByteAddress sectorMapAddr sccrMapAddr xSPiProfile1Addr cmdSeqODDRAddr eraseType eraseCmd eraseSize eraseTime cy_stc_smif_erase_type_t fourByteAddressBuffer base memCfg slaveSelect cy_en_smif_slave_select_t flags dataSelect cy_en_smif_data_select_t baseAddress memMappedSize dualQuadSlots deviceCfg numOfAddrBytes memSize readCmd command cmdWidth cy_en_smif_txfr_width_t addrWidth mode modeWidth dummyCycles dataWidth dataRate cy_en_smif_data_rate_t dummyCyclesPresence cy_en_smif_field_presence_t modePresence modeH modeRate addrRate cmdPresence commandH cmdRate cy_stc_smif_mem_cmd_t writeEnCmd writeDisCmd chipEraseCmd programCmd programSize readStsRegWipCmd readStsRegQeCmd writeStsRegQeCmd readSfdpCmd stsRegBusyMask stsRegQuadEnableMask chipEraseTime programTime hybridRegionCount hybridRegionInfo regionAddress sectorsCount cy_stc_smif_hybrid_region_info_t readLatencyCmd writeLatencyCmd latencyCyclesRegAddr latencyCyclesMask octalDDREnableSeq cmdSeq1Len cmdSeq2Len cmdSeq1 cmdSeq2 cy_stc_smif_octal_ddr_en_seq_t readStsRegOeCmd writeStsRegOeCmd stsRegOctalEnableMask octalEnableRegAddr freq_of_operation cy_en_smif_interface_freq_t cy_stc_smif_mem_device_cfg_t mergeTimeout cy_en_smif_merge_timeout_t cy_stc_smif_mem_config_t maxdataWidth qer_id context txBufferAddress txBufferSize txBufferCounter rxBufferAddress rxBufferSize rxBufferCounter transferStatus txCompleteCb cy_smif_event_cb_t rxCompleteCb timeout memReadyPollDealy preCmdDataRate preCmdWidth preXIPDataRate cy_stc_smif_context_t result basicSpiTableLength addr4ByteTableLength sccrMapTableLength cmdSeqODDRTableLength sectorMapTableLength xSPIProfile1TableLength device cmdSfdp sfdp_minor_revision pMode cmdRead eraseTypeOffset octalProtocolMode device_base size is2byte_command sfdpAddr_4byte i int id address tableLength headerOffset idx currET locSize memorySize addrBytesNum sfdpAddrCode cmdWriteEnable cmdWriteDisable qerId cmdChipErase chipEraseProgTime chipEraseUnits chipEraseCount chipEraseMs eraseMul readEraseTime chipEraseTimeMax programTimeMax progMul programTimeCount programTimeUnits progUs maxDataWidth sfdpDataIndex protocolMode quadEnabled entryMethodByte writeEn xSPiProfile1AddrBuffer cfr_reg_address cmdSeqODDRAddrBuffer cfr_value oDDREnSeq sccrMapAddrBuffer sfdpForBytesTableDword1 protocol sccrMapAddrBufferDword16 cmdProgram eraseTypeStc eraseOffset eraseTypeMask eraseMs eraseCount eraseUnits eraseTimeDefaultIndex eraseTypeTypicalTime currRegisterAddr sectorMapBuff buffLength addrCode currTableIdx regionInfoIdx regValue regMask currCmd numOfRegions currRegionAddr regionSize currRegion currRegionPtr supportedEraseType eraseTypeCode dev devCfg prog read memSfdpDetect maxMinorRevison buff fourBytes sccrMapDWord9Value cmdReadLatency cmdWriteLatency sccrMapDW9_Address latencyMaskoffset latencyBits value byteArray startPos writeCmd cmdParam paramSize addressSize Component: ARM Compiler 6.16 Tool: armclang [5dfeb700] ../src/pdl/drivers/source\cy_smif_memslot.c C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_cmsis_uv unsigned int CY_SMIF_SUCCESS CY_SMIF_CMD_FIFO_FULL CY_SMIF_EXCEED_TIMEOUT CY_SMIF_NO_QE_BIT CY_SMIF_BAD_PARAM CY_SMIF_NO_SFDP_SUPPORT CY_SMIF_NOT_HYBRID_MEM CY_SMIF_SFDP_CORRUPTED_TABLE CY_SMIF_SFDP_SS0_FAILED CY_SMIF_SFDP_SS1_FAILED CY_SMIF_SFDP_SS2_FAILED CY_SMIF_SFDP_SS3_FAILED CY_SMIF_CMD_NOT_FOUND CY_SMIF_SFDP_BUFFER_INSUFFICIENT CY_SMIF_NO_OE_BIT CY_SMIF_BUSY unsigned char CY_SMIF_SLAVE_SELECT_0 CY_SMIF_SLAVE_SELECT_1 CY_SMIF_SLAVE_SELECT_2 CY_SMIF_SLAVE_SELECT_3 CY_SMIF_DATA_SEL0 CY_SMIF_DATA_SEL1 CY_SMIF_DATA_SEL2 CY_SMIF_DATA_SEL3 CY_SMIF_WIDTH_SINGLE CY_SMIF_WIDTH_DUAL CY_SMIF_WIDTH_QUAD CY_SMIF_WIDTH_OCTAL CY_SMIF_WIDTH_NA CY_SMIF_SDR CY_SMIF_DDR CY_SMIF_NOT_PRESENT CY_SMIF_PRESENT_1BYTE CY_SMIF_PRESENT_2BYTE CY_SMIF_100MHZ_OPERATION CY_SMIF_133MHZ_OPERATION CY_SMIF_166MHZ_OPERATION CY_SMIF_200MHZ_OPERATION CY_SMIF_MERGE_TIMEOUT_1_CYCLE CY_SMIF_MERGE_TIMEOUT_16_CYCLES CY_SMIF_MERGE_TIMEOUT_256_CYCLES CY_SMIF_MERGE_TIMEOUT_4096_CYCLES CY_SMIF_MERGE_TIMEOUT_65536_CYCLES uint32_t CTL RESERVED ADDR MASK RESERVED1 __ARRAY_SIZE_TYPE__ ADDR_CTL RESERVED2 RD_STATUS RESERVED3 RD_CMD_CTL RD_ADDR_CTL RD_MODE_CTL RD_DUMMY_CTL RD_DATA_CTL RD_CRC_CTL RD_BOUND_CTL RESERVED4 WR_CMD_CTL WR_ADDR_CTL WR_MODE_CTL WR_DUMMY_CTL WR_DATA_CTL WR_CRC_CTL RESERVED5 SMIF_DEVICE_Type STATUS INT_CLOCK_DELAY_TAP_SEL0 INT_CLOCK_DELAY_TAP_SEL1 DLP DL_STATUS0 DL_STATUS1 DELAY_TAP_SEL TX_CMD_FIFO_STATUS TX_CMD_FIFO_WR TX_DATA_FIFO_CTL TX_DATA_FIFO_STATUS RESERVED6 TX_DATA_FIFO_WR1 TX_DATA_FIFO_WR2 TX_DATA_FIFO_WR4 TX_DATA_FIFO_WR1ODD RESERVED7 RX_DATA_MMIO_FIFO_CTL RX_DATA_MMIO_FIFO_STATUS RX_DATA_FIFO_STATUS RESERVED8 RX_DATA_MMIO_FIFO_RD1 RX_DATA_MMIO_FIFO_RD2 RX_DATA_MMIO_FIFO_RD4 RESERVED9 RX_DATA_MMIO_FIFO_RD1_SILENT RESERVED10 SLOW_CA_CTL RESERVED11 SLOW_CA_CMD RESERVED12 FAST_CA_CTL RESERVED13 FAST_CA_CMD RESERVED14 CRYPTO_CMD RESERVED15 CRYPTO_INPUT0 CRYPTO_INPUT1 CRYPTO_INPUT2 CRYPTO_INPUT3 RESERVED16 CRYPTO_KEY0 CRYPTO_KEY1 CRYPTO_KEY2 CRYPTO_KEY3 RESERVED17 CRYPTO_OUTPUT0 CRYPTO_OUTPUT1 CRYPTO_OUTPUT2 CRYPTO_OUTPUT3 RESERVED18 CRC_CMD RESERVED19 CRC_INPUT0 CRC_INPUT1 RESERVED20 CRC_OUTPUT RESERVED21 INTR INTR_SET INTR_MASK INTR_MASKED RESERVED22 DEVICE SMIF_Type _Bool cy_en_smif_status_t unsigned short uint16_t uint8_t cy_en_smif_slave_select_t slaveSelect flags dataSelect cy_en_smif_data_select_t baseAddress memMappedSize dualQuadSlots deviceCfg numOfAddrBytes memSize readCmd command cmdWidth cy_en_smif_txfr_width_t addrWidth mode modeWidth dummyCycles dataWidth dataRate cy_en_smif_data_rate_t dummyCyclesPresence cy_en_smif_field_presence_t modePresence modeH modeRate addrRate cmdPresence commandH cmdRate cy_stc_smif_mem_cmd_t writeEnCmd writeDisCmd eraseCmd eraseSize chipEraseCmd programCmd programSize readStsRegWipCmd readStsRegQeCmd writeStsRegQeCmd readSfdpCmd stsRegBusyMask stsRegQuadEnableMask eraseTime chipEraseTime programTime hybridRegionCount hybridRegionInfo regionAddress sectorsCount cy_stc_smif_hybrid_region_info_t readLatencyCmd writeLatencyCmd latencyCyclesRegAddr latencyCyclesMask octalDDREnableSeq cmdSeq1Len cmdSeq2Len cmdSeq1 cmdSeq2 cy_stc_smif_octal_ddr_en_seq_t readStsRegOeCmd writeStsRegOeCmd stsRegOctalEnableMask octalEnableRegAddr freq_of_operation cy_en_smif_interface_freq_t cy_stc_smif_mem_device_cfg_t mergeTimeout cy_en_smif_merge_timeout_t cy_stc_smif_mem_config_t Cy_SMIF_MemInit Cy_SMIF_GetDeviceBySlot XipRegInit Cy_SMIF_MemDeInit Cy_SMIF_MemCmdWriteEnable Cy_SMIF_MemCmdWriteDisable Cy_SMIF_MemIsBusy Cy_SMIF_MemCmdReadStatus Cy_SMIF_MemQuadEnable Cy_SMIF_MemCmdWriteStatus Cy_SMIF_MemOctalEnable ReadAnyReg Cy_SMIF_MemOctalDDREnable Cy_SMIF_MemCmdChipErase Cy_SMIF_MemCmdSectorErase Cy_SMIF_MemLocateHybridRegion ByteArrayToValue Cy_SMIF_MemCmdProgram Cy_SMIF_MemCmdRead Cy_SMIF_SetReadyPollingDelay Cy_SMIF_MemIsReady Cy_SMIF_MemIsQuadEnabled Cy_SMIF_MemEnableQuadMode Cy_SMIF_MemRead ValueToByteArray Cy_SMIF_MemWrite Cy_SMIF_MemEraseSector Cy_SMIF_MemEraseChip base blockConfig memCount memConfig majorVersion minorVersion cy_stc_smif_block_config_t context txBufferAddress txBufferSize txBufferCounter rxBufferAddress rxBufferSize rxBufferCounter transferStatus txCompleteCb cy_smif_event_cb_t rxCompleteCb timeout memReadyPollDealy preCmdDataRate preCmdWidth preXIPDataRate cy_stc_smif_context_t sfdpRes result idx memCfg device sfdpRet size extMemCfg dev devCfg prog read deviceIndex memDevice writeEn writeDis status readStsResult addr_param statusReg writeQeCmd readWipCmd readQeCmd qeMask octalEnableAddr writeOeCmd readOeCmd oeMask value addressSize address oDDREnSeq cmdErase sectorAddr hybrInfo eraseCommand regionInfo currInfo regionStartAddr regionEndAddr byteArray addr writeBuff cmdCompleteCb cmdProg slaveSelected readBuff cmdRead pollTimeoutUs timeoutUs isBusy pollingDelay delayMs timeoutSlice delayUs isQuadEnabled readStatus statusCmd maskQE rxBuffer addrArray chunk length interruptState startPos txBuffer offset pageSize cmdProgram hybridRegionStart eraseEnd endAddress maxEraseTime eraseSectorSize Component: ARM Compiler 6.16 Tool: armclang [5dfeb700] ../src/pdl/drivers/source\cy_smif.c C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_cmsis_uv unsigned int CY_SMIF_SUCCESS CY_SMIF_CMD_FIFO_FULL CY_SMIF_EXCEED_TIMEOUT CY_SMIF_NO_QE_BIT CY_SMIF_BAD_PARAM CY_SMIF_NO_SFDP_SUPPORT CY_SMIF_NOT_HYBRID_MEM CY_SMIF_SFDP_CORRUPTED_TABLE CY_SMIF_SFDP_SS0_FAILED CY_SMIF_SFDP_SS1_FAILED CY_SMIF_SFDP_SS2_FAILED CY_SMIF_SFDP_SS3_FAILED CY_SMIF_CMD_NOT_FOUND CY_SMIF_SFDP_BUFFER_INSUFFICIENT CY_SMIF_NO_OE_BIT CY_SMIF_BUSY unsigned char CY_SMIF_SDR CY_SMIF_DDR CY_SMIF_WIDTH_SINGLE CY_SMIF_WIDTH_DUAL CY_SMIF_WIDTH_QUAD CY_SMIF_WIDTH_OCTAL CY_SMIF_WIDTH_NA CY_SMIF_NORMAL CY_SMIF_MEMORY CY_SMIF_SLAVE_SELECT_0 CY_SMIF_SLAVE_SELECT_1 CY_SMIF_SLAVE_SELECT_2 CY_SMIF_SLAVE_SELECT_3 CY_SMIF_DATA_SEL0 CY_SMIF_DATA_SEL1 CY_SMIF_DATA_SEL2 CY_SMIF_DATA_SEL3 CY_SMIF_STARTED CY_SMIF_SEND_COMPLETE CY_SMIF_SEND_BUSY CY_SMIF_RX_COMPLETE CY_SMIF_RX_BUSY CY_SMIF_XIP_ERROR CY_SMIF_CMD_ERROR CY_SMIF_TX_ERROR CY_SMIF_RX_ERROR CY_SMIF_CACHE_SLOW CY_SMIF_CACHE_FAST CY_SMIF_CACHE_BOTH CY_SYSPM_SUCCESS CY_SYSPM_BAD_PARAM CY_SYSPM_TIMEOUT CY_SYSPM_INVALID_STATE CY_SYSPM_CANCELED CY_SYSPM_SYSCALL_PENDING CY_SYSPM_FAIL CY_SYSPM_CHECK_READY CY_SYSPM_CHECK_FAIL CY_SYSPM_BEFORE_TRANSITION CY_SYSPM_AFTER_TRANSITION CTL uint32_t STATUS RESERVED __ARRAY_SIZE_TYPE__ INT_CLOCK_DELAY_TAP_SEL0 INT_CLOCK_DELAY_TAP_SEL1 DLP RESERVED1 DL_STATUS0 DL_STATUS1 RESERVED2 DELAY_TAP_SEL RESERVED3 TX_CMD_FIFO_STATUS RESERVED4 TX_CMD_FIFO_WR RESERVED5 TX_DATA_FIFO_CTL TX_DATA_FIFO_STATUS RESERVED6 TX_DATA_FIFO_WR1 TX_DATA_FIFO_WR2 TX_DATA_FIFO_WR4 TX_DATA_FIFO_WR1ODD RESERVED7 RX_DATA_MMIO_FIFO_CTL RX_DATA_MMIO_FIFO_STATUS RX_DATA_FIFO_STATUS RESERVED8 RX_DATA_MMIO_FIFO_RD1 RX_DATA_MMIO_FIFO_RD2 RX_DATA_MMIO_FIFO_RD4 RESERVED9 RX_DATA_MMIO_FIFO_RD1_SILENT RESERVED10 SLOW_CA_CTL RESERVED11 SLOW_CA_CMD RESERVED12 FAST_CA_CTL RESERVED13 FAST_CA_CMD RESERVED14 CRYPTO_CMD RESERVED15 CRYPTO_INPUT0 CRYPTO_INPUT1 CRYPTO_INPUT2 CRYPTO_INPUT3 RESERVED16 CRYPTO_KEY0 CRYPTO_KEY1 CRYPTO_KEY2 CRYPTO_KEY3 RESERVED17 CRYPTO_OUTPUT0 CRYPTO_OUTPUT1 CRYPTO_OUTPUT2 CRYPTO_OUTPUT3 RESERVED18 CRC_CMD RESERVED19 CRC_INPUT0 CRC_INPUT1 RESERVED20 CRC_OUTPUT RESERVED21 INTR INTR_SET INTR_MASK INTR_MASKED RESERVED22 DEVICE ADDR MASK ADDR_CTL RD_STATUS RD_CMD_CTL RD_ADDR_CTL RD_MODE_CTL RD_DUMMY_CTL RD_DATA_CTL RD_CRC_CTL RD_BOUND_CTL WR_CMD_CTL WR_ADDR_CTL WR_MODE_CTL WR_DUMMY_CTL WR_DATA_CTL WR_CRC_CTL SMIF_DEVICE_Type SMIF_Type unsigned short uint16_t uint8_t txBufferAddress txBufferSize txBufferCounter rxBufferAddress rxBufferSize rxBufferCounter transferStatus txCompleteCb cy_smif_event_cb_t rxCompleteCb timeout memReadyPollDealy preCmdDataRate cy_en_smif_data_rate_t preCmdWidth cy_en_smif_txfr_width_t preXIPDataRate cy_stc_smif_context_t cy_en_smif_txfr_status_t Cy_SMIF_Init cy_en_smif_status_t Cy_SMIF_SetInterruptMask Cy_SMIF_GetInterruptMask Cy_SMIF_DeInit Cy_SMIF_SetMode Cy_SMIF_GetMode cy_en_smif_mode_t Cy_SMIF_SetDataSelect Cy_SMIF_GetDeviceBySlot Cy_SMIF_TransmitCommand Cy_SMIF_TransmitCommand_Ext Cy_SMIF_TransmitData Cy_SMIF_TransmitData_Ext Cy_SMIF_TransmitDataBlocking Cy_SMIF_TransmitDataBlocking_Ext Cy_SMIF_ReceiveData Cy_SMIF_ReceiveData_Ext Cy_SMIF_ReceiveDataBlocking Cy_SMIF_ReceiveDataBlocking_Ext Cy_SMIF_SendDummyCycles Cy_SMIF_SendDummyCycles_Ext Cy_SMIF_GetTransferStatus Cy_SMIF_Enable Cy_SMIF_GetCmdFifoStatus Cy_SMIF_TimeoutRun Cy_SMIF_PushTxFifo Cy_SMIF_PopRxFifo Cy_SMIF_SetCryptoKey Cy_SMIF_SetCryptoIV Cy_SMIF_ConvertSlaveSlotToIndex Cy_SMIF_SetCryptoEnable Cy_SMIF_SetCryptoDisable Cy_SMIF_Encrypt Cy_SMIF_UnPackByteArray Cy_SMIF_CacheEnable Cy_SMIF_CacheDisable Cy_SMIF_CachePrefetchingEnable Cy_SMIF_CachePrefetchingDisable Cy_SMIF_CacheInvalidate Cy_SMIF_DeepSleepCallback cy_en_syspm_status_t Cy_SMIF_BusyCheck _Bool Cy_SMIF_Disable Cy_SMIF_HibernateCallback Cy_SMIF_GetTxFifoStatus Cy_SMIF_PackBytesArray Cy_SMIF_GetRxFifoStatus base config mode deselectDelay rxClockSel blockEvent cy_stc_smif_config_t context result smif_ctl_vlaue interrupt idx read_cmd_data_ctl temp slaveSelect cy_en_smif_slave_select_t dataSelect cy_en_smif_data_select_t device cmd cmdTxfrWidth cmdParam paramTxfrWidth completeTxfr paramSize isCommand2byte cmdDataRate timeoutUnits bufIndex constCmdPart paramDataRate txBuffer size transferWidth TxCompleteCb TxCmpltCb dataDataRate trUnitNum contextLoc rxBuffer RxCompleteCb dataRate RxCmpltCb rxUnitNum cycles status baseaddr buffCounter buff freeFifoBytes writeBytes loadedFifoBytes readBytes key nonce ss device_idx ret slaveId cryptoOut address data dataIndex outIndex inValue outBuff fourBytes cacheType cy_en_smif_cache_t callbackParams cy_stc_syspm_callback_params_t cy_en_syspm_callback_mode_t retStatus locContext locBase checkFail Component: ARM Compiler 6.16 Tool: armclang [5dfeb700] ../src/cycfg\cycfg_qspi_memslot_SFDP.c C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_cmsis_uv CFGSMIF_SlaveSlot_0_readCmd command unsigned int uint32_t cmdWidth unsigned char CY_SMIF_WIDTH_SINGLE CY_SMIF_WIDTH_DUAL CY_SMIF_WIDTH_QUAD CY_SMIF_WIDTH_OCTAL CY_SMIF_WIDTH_NA cy_en_smif_txfr_width_t addrWidth mode modeWidth dummyCycles dataWidth dataRate CY_SMIF_SDR CY_SMIF_DDR cy_en_smif_data_rate_t dummyCyclesPresence CY_SMIF_NOT_PRESENT CY_SMIF_PRESENT_1BYTE CY_SMIF_PRESENT_2BYTE cy_en_smif_field_presence_t modePresence modeH modeRate addrRate cmdPresence commandH cmdRate cy_stc_smif_mem_cmd_t CFGSMIF_SlaveSlot_0_writeEnCmd CFGSMIF_SlaveSlot_0_writeDisCmd CFGSMIF_SlaveSlot_0_eraseCmd CFGSMIF_SlaveSlot_0_chipEraseCmd CFGSMIF_SlaveSlot_0_programCmd CFGSMIF_SlaveSlot_0_readStsRegQeCmd CFGSMIF_SlaveSlot_0_readStsRegWipCmd CFGSMIF_SlaveSlot_0_writeStsRegQeCmd CFGSMIF_SlaveSlot_0_readSfdpCmd CFGSMIF_SlaveSlot_0_region0 regionAddress sectorsCount eraseCmd eraseSize eraseTime cy_stc_smif_hybrid_region_info_t CFGSMIF_SlaveSlot_0_region1 CFGSMIF_SlaveSlot_0_region2 CFGSMIF_SlaveSlot_0_region3 CFGSMIF_SlaveSlot_0_region4 CFGSMIF_SlaveSlot_0_region5 CFGSMIF_SlaveSlot_0_region6 CFGSMIF_SlaveSlot_0_region7 CFGSMIF_SlaveSlot_0_region8 CFGSMIF_SlaveSlot_0_region9 CFGSMIF_SlaveSlot_0_region10 CFGSMIF_SlaveSlot_0_region11 CFGSMIF_SlaveSlot_0_region12 CFGSMIF_SlaveSlot_0_region13 CFGSMIF_SlaveSlot_0_region14 CFGSMIF_SlaveSlot_0_region15 CFGSMIF_SlaveSlot_0_regionInfo __ARRAY_SIZE_TYPE__ CFGSMIF_deviceCfg_SlaveSlot_0 numOfAddrBytes memSize readCmd writeEnCmd writeDisCmd chipEraseCmd programCmd programSize readStsRegWipCmd readStsRegQeCmd writeStsRegQeCmd readSfdpCmd stsRegBusyMask stsRegQuadEnableMask chipEraseTime programTime hybridRegionCount hybridRegionInfo readLatencyCmd writeLatencyCmd latencyCyclesRegAddr latencyCyclesMask octalDDREnableSeq cmdSeq1Len uint8_t cmdSeq2Len cmdSeq1 cmdSeq2 cy_stc_smif_octal_ddr_en_seq_t readStsRegOeCmd writeStsRegOeCmd stsRegOctalEnableMask octalEnableRegAddr freq_of_operation CY_SMIF_100MHZ_OPERATION CY_SMIF_133MHZ_OPERATION CY_SMIF_166MHZ_OPERATION CY_SMIF_200MHZ_OPERATION cy_en_smif_interface_freq_t cy_stc_smif_mem_device_cfg_t CFGSMIF_SlaveSlot_0 slaveSelect CY_SMIF_SLAVE_SELECT_0 CY_SMIF_SLAVE_SELECT_1 CY_SMIF_SLAVE_SELECT_2 CY_SMIF_SLAVE_SELECT_3 cy_en_smif_slave_select_t flags dataSelect CY_SMIF_DATA_SEL0 CY_SMIF_DATA_SEL1 CY_SMIF_DATA_SEL2 CY_SMIF_DATA_SEL3 cy_en_smif_data_select_t baseAddress memMappedSize dualQuadSlots deviceCfg mergeTimeout CY_SMIF_MERGE_TIMEOUT_1_CYCLE CY_SMIF_MERGE_TIMEOUT_16_CYCLES CY_SMIF_MERGE_TIMEOUT_256_CYCLES CY_SMIF_MERGE_TIMEOUT_4096_CYCLES CY_SMIF_MERGE_TIMEOUT_65536_CYCLES cy_en_smif_merge_timeout_t cy_stc_smif_mem_config_t CFGSMIF_SlaveSlot_1_readCmd CFGSMIF_SlaveSlot_1_writeEnCmd CFGSMIF_SlaveSlot_1_writeDisCmd CFGSMIF_SlaveSlot_1_eraseCmd CFGSMIF_SlaveSlot_1_chipEraseCmd CFGSMIF_SlaveSlot_1_programCmd CFGSMIF_SlaveSlot_1_readStsRegQeCmd CFGSMIF_SlaveSlot_1_readStsRegWipCmd CFGSMIF_SlaveSlot_1_writeStsRegQeCmd CFGSMIF_SlaveSlot_1_readSfdpCmd CFGSMIF_SlaveSlot_1_region0 CFGSMIF_SlaveSlot_1_region1 CFGSMIF_SlaveSlot_1_region2 CFGSMIF_SlaveSlot_1_region3 CFGSMIF_SlaveSlot_1_region4 CFGSMIF_SlaveSlot_1_region5 CFGSMIF_SlaveSlot_1_region6 CFGSMIF_SlaveSlot_1_region7 CFGSMIF_SlaveSlot_1_region8 CFGSMIF_SlaveSlot_1_region9 CFGSMIF_SlaveSlot_1_region10 CFGSMIF_SlaveSlot_1_region11 CFGSMIF_SlaveSlot_1_region12 CFGSMIF_SlaveSlot_1_region13 CFGSMIF_SlaveSlot_1_region14 CFGSMIF_SlaveSlot_1_region15 CFGSMIF_SlaveSlot_1_regionInfo CFGSMIF_deviceCfg_SlaveSlot_1 CFGSMIF_SlaveSlot_1 CFGSMIF_SlaveSlot_2_readCmd CFGSMIF_SlaveSlot_2_writeEnCmd CFGSMIF_SlaveSlot_2_writeDisCmd CFGSMIF_SlaveSlot_2_eraseCmd CFGSMIF_SlaveSlot_2_chipEraseCmd CFGSMIF_SlaveSlot_2_programCmd CFGSMIF_SlaveSlot_2_readStsRegQeCmd CFGSMIF_SlaveSlot_2_readStsRegWipCmd CFGSMIF_SlaveSlot_2_writeStsRegQeCmd CFGSMIF_SlaveSlot_2_readSfdpCmd CFGSMIF_SlaveSlot_2_region0 CFGSMIF_SlaveSlot_2_region1 CFGSMIF_SlaveSlot_2_region2 CFGSMIF_SlaveSlot_2_region3 CFGSMIF_SlaveSlot_2_region4 CFGSMIF_SlaveSlot_2_region5 CFGSMIF_SlaveSlot_2_region6 CFGSMIF_SlaveSlot_2_region7 CFGSMIF_SlaveSlot_2_region8 CFGSMIF_SlaveSlot_2_region9 CFGSMIF_SlaveSlot_2_region10 CFGSMIF_SlaveSlot_2_region11 CFGSMIF_SlaveSlot_2_region12 CFGSMIF_SlaveSlot_2_region13 CFGSMIF_SlaveSlot_2_region14 CFGSMIF_SlaveSlot_2_region15 CFGSMIF_SlaveSlot_2_regionInfo CFGSMIF_deviceCfg_SlaveSlot_2 CFGSMIF_SlaveSlot_2 CFGSMIF_SlaveSlot_3_readCmd CFGSMIF_SlaveSlot_3_writeEnCmd CFGSMIF_SlaveSlot_3_writeDisCmd CFGSMIF_SlaveSlot_3_eraseCmd CFGSMIF_SlaveSlot_3_chipEraseCmd CFGSMIF_SlaveSlot_3_programCmd CFGSMIF_SlaveSlot_3_readStsRegQeCmd CFGSMIF_SlaveSlot_3_readStsRegWipCmd CFGSMIF_SlaveSlot_3_writeStsRegQeCmd CFGSMIF_SlaveSlot_3_readSfdpCmd CFGSMIF_SlaveSlot_3_region0 CFGSMIF_SlaveSlot_3_region1 CFGSMIF_SlaveSlot_3_region2 CFGSMIF_SlaveSlot_3_region3 CFGSMIF_SlaveSlot_3_region4 CFGSMIF_SlaveSlot_3_region5 CFGSMIF_SlaveSlot_3_region6 CFGSMIF_SlaveSlot_3_region7 CFGSMIF_SlaveSlot_3_region8 CFGSMIF_SlaveSlot_3_region9 CFGSMIF_SlaveSlot_3_region10 CFGSMIF_SlaveSlot_3_region11 CFGSMIF_SlaveSlot_3_region12 CFGSMIF_SlaveSlot_3_region13 CFGSMIF_SlaveSlot_3_region14 CFGSMIF_SlaveSlot_3_region15 CFGSMIF_SlaveSlot_3_regionInfo CFGSMIF_deviceCfg_SlaveSlot_3 CFGSMIF_SlaveSlot_3 CFGSMIF_smifMemConfigs CFGSMIF_smifBlockConfig memCount memConfig majorVersion minorVersion cy_stc_smif_block_config_t Component: ARM Compiler 6.16 Tool: armclang [5dfeb700] ../src/algo\algo_smif.c C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_cmsis_uv SMIF_State isHwInitialized _Bool activeConfig mode unsigned int uint32_t deselectDelay rxClockSel blockEvent cy_stc_smif_config_t cy_smif_state_t SMIF_context txBufferAddress unsigned char uint8_t txBufferSize txBufferCounter rxBufferAddress rxBufferSize rxBufferCounter transferStatus txCompleteCb cy_smif_event_cb_t rxCompleteCb timeout memReadyPollDealy unsigned short uint16_t preCmdDataRate CY_SMIF_SDR CY_SMIF_DDR cy_en_smif_data_rate_t preCmdWidth CY_SMIF_WIDTH_SINGLE CY_SMIF_WIDTH_DUAL CY_SMIF_WIDTH_QUAD CY_SMIF_WIDTH_OCTAL CY_SMIF_WIDTH_NA cy_en_smif_txfr_width_t preXIPDataRate cy_stc_smif_context_t SMIF_ConfigXIP SMIF_ConfigMMIO CY_SMIF_SLAVE_SELECT_0 CY_SMIF_SLAVE_SELECT_1 CY_SMIF_SLAVE_SELECT_2 CY_SMIF_SLAVE_SELECT_3 CY_SMIF_DATA_SEL0 CY_SMIF_DATA_SEL1 CY_SMIF_DATA_SEL2 CY_SMIF_DATA_SEL3 CY_SMIF_NOT_PRESENT CY_SMIF_PRESENT_1BYTE CY_SMIF_PRESENT_2BYTE CY_SMIF_100MHZ_OPERATION CY_SMIF_133MHZ_OPERATION CY_SMIF_166MHZ_OPERATION CY_SMIF_200MHZ_OPERATION CY_SMIF_MERGE_TIMEOUT_1_CYCLE CY_SMIF_MERGE_TIMEOUT_16_CYCLES CY_SMIF_MERGE_TIMEOUT_256_CYCLES CY_SMIF_MERGE_TIMEOUT_4096_CYCLES CY_SMIF_MERGE_TIMEOUT_65536_CYCLES CY_SMIF_SFDP_QER_0 CY_SMIF_SFDP_QER_1 CY_SMIF_SFDP_QER_2 CY_SMIF_SFDP_QER_3 CY_SMIF_SFDP_QER_4 CY_SMIF_SFDP_QER_5 CY_SMIF_SFDP_QER_6 CY_SMIF_SUCCESS CY_SMIF_CMD_FIFO_FULL CY_SMIF_EXCEED_TIMEOUT CY_SMIF_NO_QE_BIT CY_SMIF_BAD_PARAM CY_SMIF_NO_SFDP_SUPPORT CY_SMIF_NOT_HYBRID_MEM CY_SMIF_SFDP_CORRUPTED_TABLE CY_SMIF_SFDP_SS0_FAILED CY_SMIF_SFDP_SS1_FAILED CY_SMIF_SFDP_SS2_FAILED CY_SMIF_SFDP_SS3_FAILED CY_SMIF_CMD_NOT_FOUND CY_SMIF_SFDP_BUFFER_INSUFFICIENT CY_SMIF_NO_OE_BIT CY_SMIF_BUSY CY_SMIF_NORMAL CY_SMIF_MEMORY CY_SMIF_STARTED CY_SMIF_SEND_COMPLETE CY_SMIF_SEND_BUSY CY_SMIF_RX_COMPLETE CY_SMIF_RX_BUSY CY_SMIF_XIP_ERROR CY_SMIF_CMD_ERROR CY_SMIF_TX_ERROR CY_SMIF_RX_ERROR slaveSelect cy_en_smif_slave_select_t flags dataSelect cy_en_smif_data_select_t baseAddress memMappedSize dualQuadSlots deviceCfg numOfAddrBytes memSize readCmd command cmdWidth addrWidth modeWidth dummyCycles dataWidth dataRate dummyCyclesPresence cy_en_smif_field_presence_t modePresence modeH modeRate addrRate cmdPresence commandH cmdRate cy_stc_smif_mem_cmd_t writeEnCmd writeDisCmd eraseCmd eraseSize chipEraseCmd programCmd programSize readStsRegWipCmd readStsRegQeCmd writeStsRegQeCmd readSfdpCmd stsRegBusyMask stsRegQuadEnableMask eraseTime chipEraseTime programTime hybridRegionCount hybridRegionInfo regionAddress sectorsCount cy_stc_smif_hybrid_region_info_t readLatencyCmd writeLatencyCmd latencyCyclesRegAddr latencyCyclesMask octalDDREnableSeq cmdSeq1Len cmdSeq2Len cmdSeq1 __ARRAY_SIZE_TYPE__ cmdSeq2 cy_stc_smif_octal_ddr_en_seq_t readStsRegOeCmd writeStsRegOeCmd stsRegOctalEnableMask octalEnableRegAddr freq_of_operation cy_en_smif_interface_freq_t cy_stc_smif_mem_device_cfg_t mergeTimeout cy_en_smif_merge_timeout_t cy_stc_smif_mem_config_t CTL STATUS RESERVED INT_CLOCK_DELAY_TAP_SEL0 INT_CLOCK_DELAY_TAP_SEL1 DLP RESERVED1 DL_STATUS0 DL_STATUS1 RESERVED2 DELAY_TAP_SEL RESERVED3 TX_CMD_FIFO_STATUS RESERVED4 TX_CMD_FIFO_WR RESERVED5 TX_DATA_FIFO_CTL TX_DATA_FIFO_STATUS RESERVED6 TX_DATA_FIFO_WR1 TX_DATA_FIFO_WR2 TX_DATA_FIFO_WR4 TX_DATA_FIFO_WR1ODD RESERVED7 RX_DATA_MMIO_FIFO_CTL RX_DATA_MMIO_FIFO_STATUS RX_DATA_FIFO_STATUS RESERVED8 RX_DATA_MMIO_FIFO_RD1 RX_DATA_MMIO_FIFO_RD2 RX_DATA_MMIO_FIFO_RD4 RESERVED9 RX_DATA_MMIO_FIFO_RD1_SILENT RESERVED10 SLOW_CA_CTL RESERVED11 SLOW_CA_CMD RESERVED12 FAST_CA_CTL RESERVED13 FAST_CA_CMD RESERVED14 CRYPTO_CMD RESERVED15 CRYPTO_INPUT0 CRYPTO_INPUT1 CRYPTO_INPUT2 CRYPTO_INPUT3 RESERVED16 CRYPTO_KEY0 CRYPTO_KEY1 CRYPTO_KEY2 CRYPTO_KEY3 RESERVED17 CRYPTO_OUTPUT0 CRYPTO_OUTPUT1 CRYPTO_OUTPUT2 CRYPTO_OUTPUT3 RESERVED18 CRC_CMD RESERVED19 CRC_INPUT0 CRC_INPUT1 RESERVED20 CRC_OUTPUT RESERVED21 INTR INTR_SET INTR_MASK INTR_MASKED RESERVED22 DEVICE ADDR MASK ADDR_CTL RD_STATUS RD_CMD_CTL RD_ADDR_CTL RD_MODE_CTL RD_DUMMY_CTL RD_DATA_CTL RD_CRC_CTL RD_BOUND_CTL WR_CMD_CTL WR_ADDR_CTL WR_MODE_CTL WR_DUMMY_CTL WR_DATA_CTL WR_CRC_CTL SMIF_DEVICE_Type SMIF_Type memCount memConfig majorVersion minorVersion cy_stc_smif_block_config_t int SMIF_InitHardware result_t SMIF_PrepareConfigs SMIF_SetCmdPtr SMIF_TuneConfigs SMIF_FindMappedDevice SMIF_FindDualQuadPair SMIF_Init_XIP SMIF_Init SMIF_EnableQuad SMIF_UnInit Cy_SMIF_BusyCheck Cy_SMIF_Disable SMIF_Read SMIF_EraseChip SMIF_Erase SMIF_Program SMIF_Verify SMIF_IsMemoryFilled SMIF_IsQuadEnabled SMIF_PollBusy SMIF_PollTransferStatus result dst_cmd src_cmd memIdx device address pMem maxSize dualChMask smifConfig smifstat cy_en_smif_status_t readStatus statusCmd isQuadEnabled maskQE polCnt base size buffer dualQuadMembers i isDualQuadPair memConfigDualQuadPair memAddress regionInfo sectorsInRegion offsetInRegion addrAlign sizeAlign pageSize addrEnd maxMemSize blockAddr offsetInBlock xipAddr memAbsAddr blockSize lastVerifiedAddr result1 value curAddress valueWord chunkEnd timeoutAttempts memConfigSecondDev attemptsElapsed isMem1Busy isMem2Busy cy_en_smif_txfr_status_t transferTimeout Component: ARM Compiler 6.16 Tool: armclang [5dfeb700] ../src/algo\algo_base.c C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_cmsis_uv Backup gpio_prt6_cfg out unsigned int uint32_t intrMask intrCfg cfg cfgIn cfgOut cfgSIO sel0Active sel1Active cy_stc_gpio_prt_config_t gpio_prt7_cfg gpio_prt8_cfg clk_root2 cy_backup_t unsigned char CPUSS_MS_ID_CM0 CPUSS_MS_ID_CRYPTO CPUSS_MS_ID_DW0 CPUSS_MS_ID_DW1 CPUSS_MS_ID_DMAC CPUSS_MS_ID_SLOW0 CPUSS_MS_ID_SLOW1 CPUSS_MS_ID_FAST0 CPUSS_MS_ID_FAST1 CPUSS_MS_ID_FAST2 CPUSS_MS_ID_FAST3 CPUSS_MS_ID_CM7_1 CPUSS_MS_ID_CM7_0 CPUSS_MS_ID_TC CY_GPIO_SUCCESS CY_GPIO_BAD_PARAM IDENTITY CM7_0_STATUS FAST_0_CLOCK_CTL CM7_0_CTL RESERVED __ARRAY_SIZE_TYPE__ CM7_0_INT_STATUS RESERVED1 CM7_0_VECTOR_TABLE_BASE RESERVED2 CM7_0_NMI_CTL RESERVED3 UDB_PWR_CTL UDB_PWR_DELAY_CTL RESERVED4 TRC_DBG_CLOCK_CTL RESERVED5 CM7_1_STATUS FAST_1_CLOCK_CTL CM7_1_CTL RESERVED6 CM7_1_INT_STATUS RESERVED7 CM7_1_VECTOR_TABLE_BASE RESERVED8 CM7_1_NMI_CTL RESERVED9 CM0_CTL CM0_STATUS SLOW_CLOCK_CTL PERI_CLOCK_CTL MEM_CLOCK_CTL RESERVED10 CM0_INT0_STATUS CM0_INT1_STATUS CM0_INT2_STATUS CM0_INT3_STATUS CM0_INT4_STATUS CM0_INT5_STATUS CM0_INT6_STATUS CM0_INT7_STATUS CM0_VECTOR_TABLE_BASE RESERVED11 CM0_NMI_CTL RESERVED12 CM7_0_PWR_CTL CM7_0_PWR_DELAY_CTL RESERVED13 CM7_1_PWR_CTL CM7_1_PWR_DELAY_CTL RESERVED14 RAM0_CTL0 RAM0_STATUS RESERVED15 RAM0_PWR_MACRO_CTL RAM1_CTL0 RAM1_STATUS RAM1_PWR_CTL RESERVED16 RAM2_CTL0 RAM2_STATUS RAM2_PWR_CTL RESERVED17 RAM_PWR_DELAY_CTL ROM_CTL ECC_CTL RESERVED18 PRODUCT_ID RESERVED19 DP_STATUS AP_CTL RESERVED20 BUFF_CTL RESERVED21 SYSTICK_CTL RESERVED22 MBIST_STAT RESERVED23 CAL_SUP_SET CAL_SUP_CLR RESERVED24 CM0_PC_CTL RESERVED25 CM0_PC0_HANDLER CM0_PC1_HANDLER CM0_PC2_HANDLER CM0_PC3_HANDLER RESERVED26 PROTECTION RESERVED27 TRIM_ROM_CTL TRIM_RAM_CTL TRIM_RAM200_CTL TRIM_RAM350_CTL RESERVED28 CM0_SYSTEM_INT_CTL RESERVED29 CM7_0_SYSTEM_INT_CTL RESERVED30 CM7_1_SYSTEM_INT_CTL CPUSS_Type OUT OUT_CLR OUT_SET OUT_INV IN INTR INTR_MASK INTR_MASKED INTR_SET INTR_CFG CFG CFG_IN CFG_OUT CFG_SIO CFG_IN_AUTOLVL GPIO_PRT_Type PRT INTR_CAUSE0 INTR_CAUSE1 INTR_CAUSE2 INTR_CAUSE3 VDD_ACTIVE VDD_INTR VDD_INTR_MASK VDD_INTR_MASKED VDD_INTR_SET GPIO_Type PORT_SEL0 PORT_SEL1 HSIOM_PRT_Type IsCoreM0 _Bool Loader_Backup int result_t Cy_GPIO_Port_Backup cy_en_gpio_status_t Loader_Restore result base config status baseHSIOM portNum Component: ARM Compiler 6.16 Tool: armclang [5dfeb700] ../src/algo\algo_common.c C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_cmsis_uv char Count unsigned char uint8_t NumToStr number unsigned int uint32_t base res num ptr digs Component: ARM Compiler 6.16 Tool: armclang [5dfeb700] ../src/framework/cmsis\FlashPrg.c C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_cmsis_uv CFGALGO_EraseChunkSize unsigned int uint32_t NeedClockUpdate _Bool buffer_sram_params unsigned char uint8_t __ARRAY_SIZE_TYPE__ algo_extra_buffer buffer_sram_data Init int UnInit EraseChip EraseSector ProgramPage Verify long unsigned int BlankCheck adr clk fnc result result_t sz buf pat Component: ARM Compiler 6.16 Tool: armclang [5dfeb700] ../src/framework/cmsis\FlashDev.c C:\GitLab-Runner\builds\C2Tf-s-X\0\flashloaders\cat1c\prj_cmsis_uv FlashDevice Vers unsigned short DevName char __ARRAY_SIZE_TYPE__ DevType DevAdr long unsigned int szDev szPage Res valEmpty unsigned char toProg toErase sectors szSector AddrSector FlashSectors
$t.0 $d.1 $t $t.2 $d.3 $t.4 $d.5 $t.6 $d.7 $t.8 $d.9 $t.10 $d.11 $t.12 $d.13 $t.14 $d.15 $t.16 $d.17 $t.18 $d.19 $t.20 $d.21 $t.22 $d.23 $t.24 $d.25 $t.26 $d.27 $t.28 $d.29 $t.30 $d.31 $t.32 $d.33 $t.34 $d.35 $t.36 $d.37 $t.38 $d.39 $t.40 $d.41 $t.42 $d.43 $t.44 $d.45 $t.46 $d.47 $t.48 $d.49 $t.50 $d.51 $t.52 $d.53 $t.54 $d.55 $t.56 $d.57 $t.58 $d.59 $t.60 $d.61 $t.62 $d.63 $t.64 $d.65 $t.66 $d.67 $t.68 $d.69 $t.70 $d.71 $t.72 $d.73 $t.74 $d.75 $t.76 $d.77 $t.78 $d.79 $t.80 $d.81 $t.82 $d.83 $t.84 $d.85 $t.86 $d.87 $t.88 $d.89 $t.90 $d.91 $t.92 $d.93 $t.94 $d.95 $t.96 $d.97 $t.98 $d.99 $t.100 $d.101 $t.102 $d.103 $t.104 $d.105 $t.106 $d.107 $t.108 $d.109 $t.110 $d.111 $t.112 $d.113 $t.114 $d.115 $t.116 $d.117 $t.118 $d.119 $t.120 $d.121 $t.122 $d.123 $t.124 $d.125 $t.126 $d.127 $t.128 $d.129 $t.130 $d.131 $t.132 $d.133 $t.134 $d.135 $t.136 $d.137 $t.138 $d.139 $t.140 $d.141 $t.142 $d.143 $t.144 $d.145 $t.146 $d.147 $t.148 $d.149 $t.150 $d.151 $t.152 $d.153 $t.154 $d.155 $t.156 $d.157 $t.158 $d.159 $t.160 $d.161 $t.162 $d.163 $t.164 $d.165 $t.166 $d.167 $t.168 $d.169 $t.170 $d.171 $t.172 $d.173 $t.174 $d.175 $t.176 $d.177 $t.178 $d.179 $t.180 $d.181 $t.182 $d.183 $t.184 $d.185 $d $d.realdata FlashDev.c FlashPrg.c algo_common.c algo_base.c Cy_GPIO_Port_Backup algo_smif.c Cy_SMIF_BusyCheck Cy_SMIF_Disable SMIF_context SMIF_ConfigXIP SMIF_ConfigMMIO SMIF_State.0 SMIF_State.1 algo_xflash.c algo_target_syscall.c dbg_main.c dbg_main_cmsis.c cycfg_qspi_memslot_SFDP.c cy_pdl_crop.c ..\src\pdl\drivers\source\TOOLCHAIN_ARM\cy_syslib_mdk.s .text cy_smif.c Cy_SMIF_SetInterruptMask Cy_SMIF_GetInterruptMask Cy_SMIF_GetDeviceBySlot Cy_SMIF_GetCmdFifoStatus Cy_SMIF_TimeoutRun Cy_SMIF_PushTxFifo Cy_SMIF_PopRxFifo Cy_SMIF_UnPackByteArray Cy_SMIF_GetTxFifoStatus Cy_SMIF_PackBytesArray Cy_SMIF_GetRxFifoStatus cy_smif_memslot.c XipRegInit ReadAnyReg ByteArrayToValue ValueToByteArray cy_smif_sfdp.c SfdpReadBuffer SfdpFindParameterTableAddress SfdpGetEraseSizeAndCmd SfdpGetMemoryDensity SfdpGetNumOfAddrBytes SfdpSetWriteEnableCommand SfdpSetWriteDisableCommand SfdpSetWipStatusRegisterCommand SfdpGetQuadEnableParameters SfdpSetChipEraseCommand SfdpGetPageSize SfdpGetChipEraseTime SfdpGetPageProgramTime SfdpGetReadCmdParams SfdpEnterFourByteAddressing GetOctalDDRParams GetOctalSDRParams SfdpGetReadFourBytesCmd SfdpGetProgramFourBytesCmd SfdpGetSectorEraseCommand SfdpSetProgramCommand_1_1_1 SfdpGetEraseTime SfdpPopulateRegionInfo SfdpFindParameterHeader SfdpGetReadCmd_1S_4D_4D SfdpGetReadCmd_1_4_4 SfdpGetReadCmd_1_1_4 SfdpGetReadCmd_1_2_2 SfdpGetReadCmd_1_1_2 SfdpGetReadCmd_1_1_1 SfdpSetVariableLatencyCmd Cy_SMIF_MemCmdWriteRegister SfdpGetReadCmd_1_8_8 SfdpSetProgramCommandFourBytes_1_4_4 SfdpSetProgramCommandFourBytes_1_1_4 SfdpSetProgramCommandFourBytes_1_1_1 cy_syslib.c Cy_SysLib_GetResetStatus Cy_SysLib_AsmInfiniteLoop cy_device.c cy_gpio.c cy_sysclk_v2.c cySysClkExtFreq clk1Count1 cy_btss.c cy_pd_pdcm.c cy_wdt.c cy_wdt_b.c Cy_WDT_Disable Cy_WDT_SetLowerLimit Cy_WDT_SetUpperLimit Cy_WDT_SetWarnLimit Cy_WDT_SetLowerAction Cy_WDT_SetUpperAction Cy_WDT_SetWarnAction Cy_WDT_SetService system_cm0plus.c cycfg.c cycfg_clocks.c cycfg_peripherals.c cycfg_pins.c cycfg_system.c Cy_SysClk_FllDeInit Cy_SysClk_ClkPath1Init Cy_SysClk_ClkPath2Init Cy_SysClk_ClkPath3Init Cy_SysClk_ClkPath4Init Cy_SysClk_ClkPath5Init Cy_SysClk_ClkPath6Init Cy_SysClk_Pll0Init Cy_SysClk_Pll1Init Cy_SysClk_Pll2Init Cy_SysClk_Pll3Init Cy_SysClk_ClkHf1Init Cy_SysClk_ClkHf2Init Cy_SysClk_ClkHf3Init Cy_SysClk_ClkHf4Init Cy_SysClk_ClkHf5Init Cy_SysClk_ClkHf6Init Cy_SysClk_ClkHf7Init Cy_SysClk_FllInit Cy_SysClk_ClkPath0Init Cy_SysClk_ClkHf0Init Cy_SysClk_ClkFast_0_Init srss_0_clock_0_pll400m_0_pllConfig srss_0_clock_0_pll400m_1_pllConfig srss_0_clock_0_pll_0_pllConfig srss_0_clock_0_pll_1_pllConfig srss_0_clock_0_fll_0_fllConfig dc.s ../clib/longlong.c ../clib/division.c ../clib/string.c ../clib/memcpset.c .emb_text ../clib/division.s .text_divfast ../clib/angel/rt.s ../clib/signal.c ../clib/angel/sysapp.c ../clib/angel/sys.s ../clib/signal.s BuildAttributes$$THM_ISAv3M$S$PE$A:L22$X:L11$S22$IEEE1$IW$~IW$RWPI$USESV6$~STKCKD$USESV7$~SHL$OTIME$ROPI$EBA8$STANDARDLIB$REQ8$PRES8$EABIv2 Init __aeabi_memcpy4 __aeabi_memcpy8 UnInit EraseChip EraseSector ProgramPage Verify BlankCheck Count NumToStr IsCoreM0 Loader_Backup Loader_Restore SMIF_InitHardware SMIF_PrepareConfigs SMIF_SetCmdPtr SMIF_TuneConfigs SMIF_FindMappedDevice SMIF_FindDualQuadPair SMIF_Init_XIP SMIF_Init SMIF_EnableQuad SMIF_UnInit SMIF_Read SMIF_EraseChip SMIF_Erase SMIF_Program SMIF_Verify SMIF_IsMemoryFilled SMIF_IsQuadEnabled SMIF_PollBusy SMIF_PollTransferStatus Cy_SysLib_DelayCycles Cy_SysLib_EnterCriticalSection Cy_SysLib_ExitCriticalSection Cy_SMIF_Init Cy_SMIF_DeInit Cy_SMIF_SetMode Cy_SMIF_GetMode Cy_SMIF_SetDataSelect Cy_SMIF_TransmitCommand Cy_SMIF_TransmitCommand_Ext Cy_SMIF_TransmitData Cy_SMIF_TransmitData_Ext Cy_SMIF_TransmitDataBlocking Cy_SMIF_TransmitDataBlocking_Ext Cy_SMIF_ReceiveData Cy_SMIF_ReceiveData_Ext Cy_SMIF_ReceiveDataBlocking Cy_SMIF_ReceiveDataBlocking_Ext Cy_SMIF_SendDummyCycles Cy_SMIF_SendDummyCycles_Ext Cy_SMIF_GetTransferStatus Cy_SMIF_Enable Cy_SMIF_SetCryptoKey Cy_SMIF_SetCryptoIV Cy_SMIF_ConvertSlaveSlotToIndex Cy_SMIF_SetCryptoEnable Cy_SMIF_SetCryptoDisable Cy_SMIF_Encrypt Cy_SMIF_CacheEnable Cy_SMIF_CacheDisable Cy_SMIF_CachePrefetchingEnable Cy_SMIF_CachePrefetchingDisable Cy_SMIF_CacheInvalidate Cy_SMIF_DeepSleepCallback Cy_SMIF_HibernateCallback Cy_SMIF_MemInit Cy_SMIF_MemDeInit Cy_SMIF_MemCmdWriteEnable Cy_SMIF_MemCmdWriteDisable Cy_SMIF_MemIsBusy Cy_SMIF_MemCmdReadStatus Cy_SMIF_MemQuadEnable Cy_SMIF_MemCmdWriteStatus Cy_SMIF_MemOctalEnable Cy_SMIF_MemOctalDDREnable Cy_SMIF_MemCmdChipErase Cy_SMIF_MemCmdSectorErase Cy_SMIF_MemLocateHybridRegion Cy_SMIF_MemCmdProgram Cy_SMIF_MemCmdRead Cy_SMIF_SetReadyPollingDelay Cy_SMIF_MemIsReady Cy_SMIF_MemIsQuadEnabled Cy_SMIF_MemEnableQuadMode Cy_SMIF_MemRead Cy_SMIF_MemWrite Cy_SMIF_MemEraseSector Cy_SMIF_MemEraseChip Cy_SMIF_MemInitSfdpMode Cy_SMIF_MemSfdpDetect Cy_SysLib_Delay Cy_SysLib_DelayUs Cy_SysLib_Rtos_Delay Cy_SysLib_Rtos_DelayUs Cy_SysLib_Halt Cy_SysLib_AssertFailed Cy_SysLib_ResetBackupDomain Cy_SysLib_GetResetReason Cy_SysLib_ClearResetReason Cy_SysLib_FaultHandler Cy_SysLib_ProcessingFault Cy_SysLib_SetWaitStates Cy_SysLib_GetDeviceRevision Cy_SysLib_GetDevice Cy_PDL_Init Cy_GPIO_Pin_Init Cy_GPIO_SetHSIOM Cy_GPIO_SetDrivemode Cy_GPIO_SetInterruptEdge Cy_GPIO_SetInterruptMask Cy_GPIO_SetVtrip Cy_GPIO_Write Cy_GPIO_Port_Init Cy_GPIO_Pin_FastInit Cy_GPIO_Port_Deinit Cy_GPIO_SetAmuxSplit Cy_GPIO_GetAmuxSplit Cy_GPIO_GetHSIOM Cy_GPIO_Read Cy_GPIO_ReadOut Cy_GPIO_Set Cy_GPIO_Clr Cy_GPIO_Inv Cy_GPIO_GetDrivemode Cy_GPIO_GetVtrip Cy_GPIO_SetVtripAuto Cy_GPIO_GetVtripAuto Cy_GPIO_SetSlewRate Cy_GPIO_GetSlewRate Cy_GPIO_SetDriveSel Cy_GPIO_GetDriveSel Cy_GPIO_SetVregEn Cy_GPIO_GetVregEn Cy_GPIO_SetIbufMode Cy_GPIO_GetIbufMode Cy_GPIO_SetVtripSel Cy_GPIO_GetVtripSel Cy_GPIO_SetVrefSel Cy_GPIO_GetVrefSel Cy_GPIO_SetVohSel Cy_GPIO_GetVohSel Cy_GPIO_GetInterruptStatus Cy_GPIO_ClearInterrupt Cy_GPIO_GetInterruptMask Cy_GPIO_GetInterruptStatusMasked Cy_GPIO_SetSwInterrupt Cy_GPIO_GetInterruptEdge Cy_GPIO_SetFilter Cy_GPIO_GetFilter Cy_SysClk_PeriPclkSetDivider Cy_SysClk_PeriPclkGetDivider Cy_SysClk_PeriPclkSetFracDivider Cy_SysClk_PeriPclkGetFracDivider Cy_SysClk_PeriPclkAssignDivider Cy_SysClk_PeriPclkGetAssignedDivider Cy_SysClk_PeriPclkEnableDivider Cy_SysClk_PeriPclkDisableDivider Cy_SysClk_PeriPclkEnablePhaseAlignDivider Cy_SysClk_PeriphDisableDivider Cy_SysClk_PeriPclkGetDividerEnabled Cy_SysClk_PeriphSetDivider Cy_SysClk_PeriphGetDivider Cy_SysClk_PeriphSetFracDivider Cy_SysClk_PeriphGetFracDivider Cy_SysClk_PeriphAssignDivider Cy_SysClk_PeriphGetAssignedDivider Cy_SysClk_PeriphEnableDivider Cy_SysClk_PeriphEnablePhaseAlignDivider Cy_SysClk_PeriphGetDividerEnabled Cy_SysClk_ClkSlowGetFrequency Cy_SysClk_ClkPeriGetFrequency Cy_SysClk_ClkSlowGetDivider Cy_SysClk_ClkSlowSetDivider Cy_SysClk_ClkPumpSetSource Cy_SysClk_ClkPumpGetSource Cy_SysClk_ClkPumpSetDivider Cy_SysClk_ClkPumpGetDivider Cy_SysClk_ClkPumpIsEnabled Cy_SysClk_ClkPumpEnable Cy_SysClk_ClkPumpDisable Cy_SysClk_ClkPumpGetFrequency Cy_SysClk_ClkPathGetFrequency Cy_SysClk_ClkBakSetSource Cy_SysClk_ClkBakGetSource Cy_SysClk_ClkTimerSetSource Cy_SysClk_ClkTimerGetSource Cy_SysClk_ClkTimerSetDivider Cy_SysClk_ClkTimerGetDivider Cy_SysClk_ClkTimerEnable Cy_SysClk_ClkTimerDisable Cy_SysClk_ClkLfSetSource Cy_SysClk_ClkLfGetSource Cy_SysClk_ClkHfGetFrequency Cy_SysClk_ClkPeriGetDivider Cy_SysClk_ClkPeriSetDivider Cy_SysClk_PeriGroupSetDivider Cy_SysClk_PeriGroupGetDivider Cy_SysClk_PeriGroupSetSlaveCtl Cy_SysClk_PeriGroupGetSlaveCtl Cy_SysClk_IsPeriGroupSlaveCtlSet Cy_SysClk_ClkFastGetFrequency Cy_SysClk_ClkFastGetDivider Cy_SysClk_ClkFastSetDivider Cy_SysClk_ClkHfEnable Cy_SysClk_ClkHfIsEnabled Cy_SysClk_ClkHfDisable Cy_SysClk_ClkHfSetSource Cy_SysClk_ClkHfGetSource Cy_SysClk_ClkHfSetDivider Cy_SysClk_ClkHfGetDivider Cy_SysClk_ClkHfDirectSel Cy_SysClk_IsClkHfDirectSelEnabled Cy_SysClk_MfoEnable Cy_SysClk_MfoIsEnabled Cy_SysClk_MfoDisable Cy_SysClk_WcoEnable Cy_SysClk_WcoOkay Cy_SysClk_WcoDisable Cy_SysClk_WcoBypass Cy_SysClk_PiloEnable Cy_SysClk_PiloBackupEnable Cy_SysClk_PiloIsEnabled Cy_SysClk_PiloDisable Cy_SysClk_PiloBackupDisable Cy_SysClk_AltHfGetFrequency Cy_SysClk_AltHfEnable Cy_SysClk_IsAltHfEnabled Cy_SysClk_AltLfGetFrequency Cy_SysClk_AltLfIsEnabled Cy_SysClk_IloEnable Cy_SysClk_IloDisable Cy_SysClk_IloIsEnabled Cy_SysClk_IloHibernateOn Cy_SysClk_IloSrcEnable Cy_SysClk_IloSrcDisable Cy_SysClk_IloSrcIsEnabled Cy_SysClk_IloSrcHibernateOn Cy_SysClk_ExtClkSetFrequency Cy_SysClk_ExtClkGetFrequency Cy_SysClk_EcoDisable Cy_SysClk_EcoGetStatus Cy_SysClk_EcoBleGetStatus Cy_SysClk_EcoConfigure Cy_SysClk_EcoEnable Cy_SysClk_EcoGetFrequency Cy_SysClk_EcoPrescaleConfigure Cy_SysClk_IhoIsEnabled Cy_SysClk_IhoDisable Cy_SysClk_IhoEnable Cy_SysClk_ClkPathSetSource Cy_SysClk_ClkPathGetSource Cy_SysClk_ClkPathMuxGetFrequency Cy_SysClk_FllGetConfiguration Cy_SysClk_FllIsEnabled Cy_SysClk_PllGetConfiguration Cy_SysClk_PllIsEnabled Cy_SysClk_FllLocked Cy_SysClk_FllDisable Cy_SysClk_FllOutputDividerEnable Cy_SysClk_FllConfigure Cy_SysClk_FllManualConfigure Cy_SysClk_FllEnable Cy_SysClk_FllGetFrequency Cy_SysClk_Pll400MIsEnabled Cy_SysClk_Pll400MLocked Cy_SysClk_Pll400MLostLock Cy_SysClk_Pll400MDisable Cy_SysClk_Pll400MConfigure Cy_SysClk_Pll400MGetConfiguration Cy_SysClk_Pll400MManualConfigure Cy_SysClk_Pll400MEnable Cy_SysClk_Pll200MIsEnabled Cy_SysClk_Pll200MLocked Cy_SysClk_Pll200MLostLock Cy_SysClk_Pll200MDisable Cy_SysClk_Pll200MConfigure Cy_SysClk_Pll200MGetConfiguration Cy_SysClk_Pll200MManualConfigure Cy_SysClk_Pll200MEnable Cy_SysClk_PllLocked Cy_SysClk_PllLostLock Cy_SysClk_PllDisable Cy_SysClk_PllConfigure Cy_SysClk_PllManualConfigure Cy_SysClk_PllEnable Cy_SysClk_ClkMeasurementCountersDone Cy_SysClk_StartClkMeasurementCounters Cy_SysClk_ClkMeasurementCountersGetFreq Cy_SysClk_PiloTrim Cy_SysClk_PiloInitialTrim Cy_SysClk_PiloUpdateTrimStep Cy_SysClk_PiloSetTrim Cy_SysClk_PiloGetTrim Cy_SysClk_IloTrim Cy_SysClk_IloSetTrim Cy_SysClk_IloGetTrim Cy_SysClk_DeepSleepCallback Cy_SysClk_PeriphGetFrequency Cy_SysClk_PeriPclkGetFrequency Cy_Sysclk_PeriPclkGetClkHfNum Cy_WDT_Init Cy_WDT_Unlock Cy_WDT_Lock Cy_WDT_Locked Cy_WDT_ClearInterrupt Cy_WDT_ClearWatchdog SystemInit Cy_SystemInit SystemCoreClockUpdate Cy_SysGetCM7Status Cy_SysEnableCM7 Cy_SysResetCM7 Cy_SysDisableCM7 Cy_SysRetainCM7 Cy_DefaultUserHandler init_cycfg_all init_cycfg_clocks init_cycfg_peripherals init_cycfg_pins cycfg_ClockStartupError init_cycfg_system __aeabi_lmul _ll_mul __aeabi_uldivmod _ll_udiv memcmp __aeabi_memcpy __rt_memcpy _memset_w _memset __aeabi_memclr __rt_memclr __aeabi_memclr4 __aeabi_memclr8 __rt_memclr_w strncpy __aeabi_uidivmod __aeabi_idivmod __aeabi_uidiv __aeabi_idiv SMIF_config cy_deviceIpBlockCfgPlayer ioss_0_port_6_pin_3_config ioss_0_port_6_pin_5_config ioss_0_port_7_pin_0_config ioss_0_port_7_pin_1_config ioss_0_port_7_pin_2_config ioss_0_port_7_pin_3_config ioss_0_port_7_pin_4_config ioss_0_port_7_pin_5_config ioss_0_port_8_pin_0_config ioss_0_port_8_pin_1_config ioss_0_port_8_pin_2_config cy_device Backup CFGALGO_EraseChunkSize CFGSMIF_SlaveSlot_0 CFGSMIF_SlaveSlot_0_chipEraseCmd CFGSMIF_SlaveSlot_0_eraseCmd CFGSMIF_SlaveSlot_0_programCmd CFGSMIF_SlaveSlot_0_readCmd CFGSMIF_SlaveSlot_0_readSfdpCmd CFGSMIF_SlaveSlot_0_readStsRegQeCmd CFGSMIF_SlaveSlot_0_readStsRegWipCmd CFGSMIF_SlaveSlot_0_region0 CFGSMIF_SlaveSlot_0_region1 CFGSMIF_SlaveSlot_0_region10 CFGSMIF_SlaveSlot_0_region11 CFGSMIF_SlaveSlot_0_region12 CFGSMIF_SlaveSlot_0_region13 CFGSMIF_SlaveSlot_0_region14 CFGSMIF_SlaveSlot_0_region15 CFGSMIF_SlaveSlot_0_region2 CFGSMIF_SlaveSlot_0_region3 CFGSMIF_SlaveSlot_0_region4 CFGSMIF_SlaveSlot_0_region5 CFGSMIF_SlaveSlot_0_region6 CFGSMIF_SlaveSlot_0_region7 CFGSMIF_SlaveSlot_0_region8 CFGSMIF_SlaveSlot_0_region9 CFGSMIF_SlaveSlot_0_regionInfo CFGSMIF_SlaveSlot_0_writeDisCmd CFGSMIF_SlaveSlot_0_writeEnCmd CFGSMIF_SlaveSlot_0_writeStsRegQeCmd CFGSMIF_SlaveSlot_1 CFGSMIF_SlaveSlot_1_chipEraseCmd CFGSMIF_SlaveSlot_1_eraseCmd CFGSMIF_SlaveSlot_1_programCmd CFGSMIF_SlaveSlot_1_readCmd CFGSMIF_SlaveSlot_1_readSfdpCmd CFGSMIF_SlaveSlot_1_readStsRegQeCmd CFGSMIF_SlaveSlot_1_readStsRegWipCmd CFGSMIF_SlaveSlot_1_region0 CFGSMIF_SlaveSlot_1_region1 CFGSMIF_SlaveSlot_1_region10 CFGSMIF_SlaveSlot_1_region11 CFGSMIF_SlaveSlot_1_region12 CFGSMIF_SlaveSlot_1_region13 CFGSMIF_SlaveSlot_1_region14 CFGSMIF_SlaveSlot_1_region15 CFGSMIF_SlaveSlot_1_region2 CFGSMIF_SlaveSlot_1_region3 CFGSMIF_SlaveSlot_1_region4 CFGSMIF_SlaveSlot_1_region5 CFGSMIF_SlaveSlot_1_region6 CFGSMIF_SlaveSlot_1_region7 CFGSMIF_SlaveSlot_1_region8 CFGSMIF_SlaveSlot_1_region9 CFGSMIF_SlaveSlot_1_regionInfo CFGSMIF_SlaveSlot_1_writeDisCmd CFGSMIF_SlaveSlot_1_writeEnCmd CFGSMIF_SlaveSlot_1_writeStsRegQeCmd CFGSMIF_SlaveSlot_2 CFGSMIF_SlaveSlot_2_chipEraseCmd CFGSMIF_SlaveSlot_2_eraseCmd CFGSMIF_SlaveSlot_2_programCmd CFGSMIF_SlaveSlot_2_readCmd CFGSMIF_SlaveSlot_2_readSfdpCmd CFGSMIF_SlaveSlot_2_readStsRegQeCmd CFGSMIF_SlaveSlot_2_readStsRegWipCmd CFGSMIF_SlaveSlot_2_region0 CFGSMIF_SlaveSlot_2_region1 CFGSMIF_SlaveSlot_2_region10 CFGSMIF_SlaveSlot_2_region11 CFGSMIF_SlaveSlot_2_region12 CFGSMIF_SlaveSlot_2_region13 CFGSMIF_SlaveSlot_2_region14 CFGSMIF_SlaveSlot_2_region15 CFGSMIF_SlaveSlot_2_region2 CFGSMIF_SlaveSlot_2_region3 CFGSMIF_SlaveSlot_2_region4 CFGSMIF_SlaveSlot_2_region5 CFGSMIF_SlaveSlot_2_region6 CFGSMIF_SlaveSlot_2_region7 CFGSMIF_SlaveSlot_2_region8 CFGSMIF_SlaveSlot_2_region9 CFGSMIF_SlaveSlot_2_regionInfo CFGSMIF_SlaveSlot_2_writeDisCmd CFGSMIF_SlaveSlot_2_writeEnCmd CFGSMIF_SlaveSlot_2_writeStsRegQeCmd CFGSMIF_SlaveSlot_3 CFGSMIF_SlaveSlot_3_chipEraseCmd CFGSMIF_SlaveSlot_3_eraseCmd CFGSMIF_SlaveSlot_3_programCmd CFGSMIF_SlaveSlot_3_readCmd CFGSMIF_SlaveSlot_3_readSfdpCmd CFGSMIF_SlaveSlot_3_readStsRegQeCmd CFGSMIF_SlaveSlot_3_readStsRegWipCmd CFGSMIF_SlaveSlot_3_region0 CFGSMIF_SlaveSlot_3_region1 CFGSMIF_SlaveSlot_3_region10 CFGSMIF_SlaveSlot_3_region11 CFGSMIF_SlaveSlot_3_region12 CFGSMIF_SlaveSlot_3_region13 CFGSMIF_SlaveSlot_3_region14 CFGSMIF_SlaveSlot_3_region15 CFGSMIF_SlaveSlot_3_region2 CFGSMIF_SlaveSlot_3_region3 CFGSMIF_SlaveSlot_3_region4 CFGSMIF_SlaveSlot_3_region5 CFGSMIF_SlaveSlot_3_region6 CFGSMIF_SlaveSlot_3_region7 CFGSMIF_SlaveSlot_3_region8 CFGSMIF_SlaveSlot_3_region9 CFGSMIF_SlaveSlot_3_regionInfo CFGSMIF_SlaveSlot_3_writeDisCmd CFGSMIF_SlaveSlot_3_writeEnCmd CFGSMIF_SlaveSlot_3_writeStsRegQeCmd CFGSMIF_deviceCfg_SlaveSlot_0 CFGSMIF_deviceCfg_SlaveSlot_1 CFGSMIF_deviceCfg_SlaveSlot_2 CFGSMIF_deviceCfg_SlaveSlot_3 CFGSMIF_smifBlockConfig CFGSMIF_smifMemConfigs NeedClockUpdate SystemCoreClock cy_Hfclk0FreqHz cy_PeriClkFreqHz cy_delay32kMs cy_delayFreqHz cy_delayFreqKhz cy_delayFreqMhz cy_assertFileName cy_assertLine cy_faultFrame buffer_sram_params algo_extra_buffer buffer_sram_data FlashDevice
Component: ARM Compiler 6.16 Tool: armlink [5dfeaa00] ArmLink --strict --callgraph --load_addr_map_info --map --symbols --xref --diag_suppress=9931,L6305,L9529W --cpu=Cortex-M0+ --list=..\output\objects\cmsis\CAT1C_SMIF\CAT1C_SMIF.map --output=..\output\objects\cmsis\CAT1C_SMIF\CAT1C_SMIF.axf --scatter=..\src\framework\cmsis\link_uv_cat1c.lin --info=summarysizes,sizes,totals,unused,veneers C:\Keil_v5\ARM\ARMCLANG\Bin\..\lib\armlib\c_pe.l C:\Keil_v5\ARM\ARMCLANG\Bin\..\lib\armlib\fz_ps.l C:\Keil_v5\ARM\ARMCLANG\Bin\..\lib\armlib\h_pe.l C:\Keil_v5\ARM\ARMCLANG\Bin\..\lib\libcxx\libcpp-experimental_pe.l C:\Keil_v5\ARM\ARMCLANG\Bin\..\lib\libcxx\libcpp_pe.l C:\Keil_v5\ARM\ARMCLANG\Bin\..\lib\libcxx\libcppabi_pe.l C:\Keil_v5\ARM\ARMCLANG\Bin\..\lib\armlib\m_ps.l C:\Keil_v5\ARM\ARMCLANG\Bin\..\lib\armlib\vfpsupport.l Input Comments: cy_syslib_mdk.o Component: ARM Compiler 6.16 Tool: armasm [5dfea300] ArmAsm --debug --diag_suppress=9931 --cpu=Cortex-M0+ --depend=..\output\objects\cmsis\cat1c_smif\cy_syslib_mdk.d -IC:\Users\cydesigner\AppData\Local\Arm\Packs\ARM\CMSIS\5.8.0\Device\ARM\ARMCM0plus\Include -IC: flashdev.o flashprg.o algo_common.o algo_base.o algo_smif.o algo_xflash.o algo_target_syscall.o dbg_main.o dbg_main_cmsis.o cycfg_qspi_memslot_sfdp.o cy_pdl_crop.o cy_smif.o cy_smif_memslot.o cy_smif_sfdp.o cy_syslib.o cy_device.o cy_gpio.o cy_sysclk_v2.o cy_btss.o cy_pd_pdcm.o cy_wdt.o cy_wdt_b.o system_cm0plus.o cycfg.o cycfg_clocks.o cycfg_peripherals.o cycfg_pins.o cycfg_system.o Component: ARM Compiler 6.16 Tool: armclang [5dfeb700]
PrgCode PrgData DevDscr .debug_abbrev .debug_frame .debug_info .debug_line .debug_loc .debug_str .debug_ranges .symtab .strtab .note .comment .shstrtab