1 /******************************************************************************
2 * Copyright (c) 2022 Telink Semiconductor (Shanghai) Co., Ltd. ("TELINK")
3 * All rights reserved.
4 *
5 * Licensed under the Apache License, Version 2.0 (the "License");
6 * you may not use this file except in compliance with the License.
7 * You may obtain a copy of the License at
8 *
9 * http://www.apache.org/licenses/LICENSE-2.0
10 *
11 * Unless required by applicable law or agreed to in writing, software
12 * distributed under the License is distributed on an "AS IS" BASIS,
13 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
14 * See the License for the specific language governing permissions and
15 * limitations under the License.
16 *
17 *****************************************************************************/
18
19 #ifndef DRIVERS_B91_EXT_MISC_H_
20 #define DRIVERS_B91_EXT_MISC_H_
21
22 #include "../analog.h"
23 #include "../dma.h"
24 #include "../gpio.h"
25 #include "../pm.h"
26 #include "../timer.h"
27 #include "../flash.h"
28 #include "../mdec.h"
29 #include "../trng.h"
30 #include "../sys.h"
31 #include "../plic.h"
32 #include "../stimer.h"
33 #include "../clock.h"
34 #include "../uart.h"
35 #include "types.h"
36 #include "compiler.h"
37
38 /* for debug */
39 #define DBG_SRAM_ADDR 0x00014
40
41
42 /*
43 * addr - only 0x00012 ~ 0x00021 can be used !!! */
44 #define write_dbg32(addr, value) write_sram32(addr, value)
45
46 #define write_log32(err_code) write_sram32(0x00014, err_code)
47
48
49
50 /******************************* stimer_start ******************************************************************/
51 #define SYSTICK_NUM_PER_US 16
52 #define reg_system_tick_irq reg_system_irq_level
53
54 typedef enum {
55 STIMER_IRQ_MASK = BIT(0),
56 STIMER_32K_CAL_IRQ_MASK = BIT(1),
57 }stimer_irq_mask_e;
58
59 typedef enum {
60 FLD_IRQ_SYSTEM_TIMER = BIT(0),
61 }system_timer_irq_mask_e;
62
63
64 typedef enum {
65 STIMER_IRQ_CLR = BIT(0),
66 STIMER_32K_CAL_IRQ_CLR = BIT(1),
67 }stimer_irq_clr_e;
68
69
70 /**
71 * @brief This function serves to enable system timer interrupt.
72 * @return none
73 */
systimer_irq_enable(void)74 static inline void systimer_irq_enable(void)
75 {
76 reg_irq_src0 |= BIT(IRQ1_SYSTIMER);
77 //plic_interrupt_enable(IRQ1_SYSTIMER);
78 }
79
80 /**
81 * @brief This function serves to disable system timer interrupt.
82 * @return none
83 */
systimer_irq_disable(void)84 static inline void systimer_irq_disable(void)
85 {
86 reg_irq_src0 &= ~BIT(IRQ1_SYSTIMER);
87 //plic_interrupt_disable(IRQ1_SYSTIMER);
88 }
89
systimer_set_irq_mask(void)90 static inline void systimer_set_irq_mask(void)
91 {
92 reg_system_irq_mask |= STIMER_IRQ_MASK;
93 }
94
systimer_clr_irq_mask(void)95 static inline void systimer_clr_irq_mask(void)
96 {
97 reg_system_irq_mask &= (~STIMER_IRQ_MASK);
98 }
99
systimer_get_irq_status(void)100 static inline unsigned char systimer_get_irq_status(void)
101 {
102 return reg_system_cal_irq & FLD_IRQ_SYSTEM_TIMER;
103 }
104
systimer_clr_irq_status(void)105 static inline void systimer_clr_irq_status(void)
106 {
107 reg_system_cal_irq = STIMER_IRQ_CLR;
108 }
109
systimer_set_irq_capture(unsigned int tick)110 static inline void systimer_set_irq_capture(unsigned int tick)
111 {
112 reg_system_irq_level = tick;
113 }
114
systimer_get_irq_capture(void)115 static inline unsigned int systimer_get_irq_capture(void)
116 {
117 return reg_system_irq_level;
118 }
119
tick1_exceed_tick2(unsigned int tick1,unsigned int tick2)120 static inline int tick1_exceed_tick2(unsigned int tick1, unsigned int tick2)
121 {
122 return (unsigned int)(tick1 - tick2) < BIT(30);
123 }
124 /******************************* stimer_end ********************************************************************/
125
126
127
128 /******************************* aes_start ******************************************************************/
129 extern unsigned int aes_data_buff[8];
130 /******************************* aes_end ********************************************************************/
131
132
133
134 /******************************* core_start ******************************************************************/
135 #define irq_disable core_interrupt_disable
136 #define irq_enable core_interrupt_enable
137 #define irq_restore(en) core_restore_interrupt(en)
138 /******************************* core_end ********************************************************************/
139
140
141
142 /******************************* analog_start ******************************************************************/
143 #define analog_write analog_write_reg8
144 #define analog_read analog_read_reg8
145
146 /******************************* analog_end ********************************************************************/
147
148
149
150 /******************************* clock_start ******************************************************************/
151 typedef enum{
152 SYSCLK_16M = 16,
153 SYSCLK_24M = 24,
154 SYSCLK_32M = 32,
155 SYSCLK_48M = 48,
156 SYSCLK_64M = 64,
157 }sys_clk_fre_t;
158
clock_get_system_clk()159 static inline unsigned char clock_get_system_clk()
160 {
161 return sys_clk.cclk;
162 }
163 /******************************* clock_end ********************************************************************/
164
165
166
167 /******************************* trng_start ******************************************************************/
168 #define rand trng_rand
169 #define random_generator_init trng_init
170
171
172 /**
173 * @brief This function performs to generate a series of random numbers
174 * @param[in] len - data length
175 * @param[out] data - data pointer
176 * @return none
177 **/
178 void generateRandomNum(int len, unsigned char *data);
179
180 /******************************* trng_end ********************************************************************/
181
182
183
184 /******************************* sys_start ******************************************************************/
185 #define sleep_us(x) delay_us(x)
186 #define sleep_ms(x) delay_ms(x)
187
188
189 /******************************* sys_end ********************************************************************/
190
191
192
193 /******************************* dma_start ***************************************************************/
194
195
196
197 /**
198 * @brief ACL RX Data buffer length = maxRxOct + 21, then 16 Byte align
199 * maxRxOct + 21 = 4(DMA_len) + 2(BLE header) + maxRxOct + 4(MIC) + 3(CRC) + 8(ExtraInfor)
200 RX buffer size must be be 16*n, due to MCU design
201 */
202 #define CAL_LL_ACL_RX_FIFO_SIZE(maxRxOct) (((maxRxOct+21) + 15) / 16 *16)
203
204
205 /**
206 * @brief ACL TX Data buffer length = maxTxOct + 10, then 16 Byte align
207 * maxTxOct + 10 = 4(DMA_len) + 2(BLE header) + maxTxOct + 4(MIC)
208 TX buffer size must be be 16*n, due to MCU design
209 */
210 #define CAL_LL_ACL_TX_FIFO_SIZE(maxTxOct) (((maxTxOct+10) + 15) / 16 *16)
211
212
213 /*HCI TX RX buffer len = uart_fifo+ dma 4byte */
214 #define HCI_FIFO_SIZE(n) (((n+2+4) + 15) / 16 *16)
215
216
217 /*
218 * @brief ISO RX Data buffer length = ISORxOct + 21, then 16 Byte align
219 * ISORxOct + 21 = 4(DMA_len) + 2(BLE header) + ISORxOct + 4(MIC) + 3(CRC) + 8(ExtraInfor)
220 * RX buffer size must be be 16*n, due to MCU design
221 */
222 #define CAL_LL_ISO_RX_FIFO_SIZE(n) (((n + 21) + 15) / 16 * 16)
223
224
225 /*
226 * @brief ISO TX Data buffer length = ISOTxOct + 10, then 16 Byte align
227 * ISORxOct + 10 = 4(DMA_len) + 2(BLE header) + ISOTxOct + 4(MIC)
228 * TX buffer size must be be 16*n, due to MCU design
229 */
230 #define CAL_LL_ISO_TX_FIFO_SIZE(n) (((n + 10) + 15) / 16 * 16)
231
232
233 /*
234 * DMA_LEN(4B)+Hdr(2B)+PLD(251B)+MIC(4B)+CRC(3B)+TLK_PKT_INFO(12B)
235 * **use 2B enough**
236 */
237 #define ISO_BIS_RX_PDU_SIZE_ALLIGN16(n) (((n + 25) + 15) / 16 * 16) //4+2+4+2+4+3+12
238
239 //12 = 4(struct bis_rx_pdu_tag *next) + 4(u32 payloadNum) + 4(u32 idealPldAnchorTick) in bis_rx_pdu_t
240 #define BIS_LL_RX_PDU_FIFO_SIZE(n) (CAL_LL_ISO_RX_FIFO_SIZE(n) + 12)
241
242 /******************************* dma_end ********************************************************************/
243
244
245
246 /******************************* plic_start ******************************************************************/
247 enum{//todo
248 FLD_IRQ_EXCEPTION_EN ,
249 FLD_IRQ_SYSTIMER_EN,
250 FLD_IRQ_ALG_EN,
251 FLD_IRQ_TIMER1_EN,
252 FLD_IRQ_TIMER0_EN,
253 FLD_IRQ_DMA_EN,
254 FLD_IRQ_BMC_EN,
255 FLD_IRQ_USB_CTRL_EP_SETUP_EN,
256 FLD_IRQ_USB_CTRL_EP_DATA_EN,
257 FLD_IRQ_USB_CTRL_EP_STATUS_EN,
258 FLD_IRQ_USB_CTRL_EP_SETINF_EN,
259 FLD_IRQ_USB_ENDPOINT_EN,
260 FLD_IRQ_ZB_DM_EN,
261 FLD_IRQ_ZB_BLE_EN,
262 FLD_IRQ_ZB_BT_EN,
263 FLD_IRQ_ZB_RT_EN,
264 FLD_IRQ_PWM_EN,
265 FLD_IRQ_PKE_EN,//add
266 FLD_IRQ_UART1_EN,
267 FLD_IRQ_UART0_EN,
268 FLD_IRQ_DFIFO_EN,
269 FLD_IRQ_I2C_EN,
270 FLD_IRQ_SPI_APB_EN,
271 FLD_IRQ_USB_PWDN_EN,
272 FLD_IRQ_EN,
273 FLD_IRQ_GPIO2RISC0_EN,
274 FLD_IRQ_GPIO2RISC1_EN,
275 FLD_IRQ_SOFT_EN,
276
277 FLD_IRQ_NPE_BUS0_EN,
278 FLD_IRQ_NPE_BUS1_EN,
279 FLD_IRQ_NPE_BUS2_EN,
280 FLD_IRQ_NPE_BUS3_EN,
281 FLD_IRQ_NPE_BUS4_EN,
282
283 FLD_IRQ_USB_250US_EN,
284 FLD_IRQ_USB_RESET_EN,
285 FLD_IRQ_NPE_BUS7_EN,
286 FLD_IRQ_NPE_BUS8_EN,
287
288 FLD_IRQ_NPE_BUS13_EN=42,
289 FLD_IRQ_NPE_BUS14_EN,
290 FLD_IRQ_NPE_BUS15_EN,
291
292 FLD_IRQ_NPE_BUS17_EN=46,
293
294 FLD_IRQ_NPE_BUS21_EN=50,
295 FLD_IRQ_NPE_BUS22_EN,
296 FLD_IRQ_NPE_BUS23_EN,
297 FLD_IRQ_NPE_BUS24_EN,
298 FLD_IRQ_NPE_BUS25_EN,
299 FLD_IRQ_NPE_BUS26_EN,
300 FLD_IRQ_NPE_BUS27_EN,
301 FLD_IRQ_NPE_BUS28_EN,
302 FLD_IRQ_NPE_BUS29_EN,
303 FLD_IRQ_NPE_BUS30_EN,
304 FLD_IRQ_NPE_BUS31_EN,
305
306 FLD_IRQ_NPE_COMB_EN,
307 FLD_IRQ_PM_TM_EN,
308 FLD_IRQ_EOC_EN,
309
310 };
311
312 /******************************* plic_end ********************************************************************/
313
314
315
316 /******************************* flash_start *****************************************************************/
317 /**
318 * @brief flash capacity definition
319 * Call flash_read_mid function to get the size of flash capacity.
320 * Example is as follows:
321 * unsigned char temp_buf[4];
322 * flash_read_mid(temp_buf);
323 * The value of temp_buf[2] reflects flash capacity.
324 */
325 typedef enum {
326 FLASH_CAPACITY_64K = 0x10,
327 FLASH_CAPACITY_128K = 0x11,
328 FLASH_CAPACITY_256K = 0x12,
329 FLASH_CAPACITY_512K = 0x13,
330 FLASH_CAPACITY_1M = 0x14,
331 FLASH_CAPACITY_2M = 0x15,
332 FLASH_CAPACITY_4M = 0x16,
333 FLASH_CAPACITY_8M = 0x17,
334 } Flash_CapacityDef;
335 void flash_set_capacity(Flash_CapacityDef flash_cap);
336 Flash_CapacityDef flash_get_capacity(void);
337
338 /******************************* flash_end *******************************************************************/
339
340
341
342 /******************************* usb_end *********************************************************************/
343 #define reg_usb_irq REG_ADDR8(0x100839)
344 /******************************* usb_end *********************************************************************/
345
346
347
348 /******************************* core_start ******************************************************************/
349 #define SUPPORT_PFT_ARCH 1
350 /******************************* core_end ********************************************************************/
351
352
353
354 /******************************* uart_start ******************************************************************/
355 _attribute_ram_code_ void uart_receive_dma_set(dma_chn_e chn, unsigned char * addr,unsigned int rev_size);
356
357 void uart0_init(unsigned int baudrate);
358 /******************************* uart_end ********************************************************************/
359
360
361 #endif /* DRIVERS_B91_EXT_MISC_H_ */
362
