1 /* W5500 Stand-alone Ethernet Controller with SPI
2 *
3 * Copyright (c) 2020 Linumiz
4 * Author: Parthiban Nallathambi <parthiban@linumiz.com>
5 *
6 * SPDX-License-Identifier: Apache-2.0
7 */
8
9 #define DT_DRV_COMPAT wiznet_w5500
10
11 #include <zephyr/logging/log.h>
12 LOG_MODULE_REGISTER(eth_w5500, CONFIG_ETHERNET_LOG_LEVEL);
13
14 #include <zephyr/kernel.h>
15 #include <zephyr/device.h>
16 #include <string.h>
17 #include <errno.h>
18 #include <zephyr/drivers/gpio.h>
19 #include <zephyr/drivers/spi.h>
20 #include <zephyr/net/net_pkt.h>
21 #include <zephyr/net/net_if.h>
22 #include <zephyr/net/ethernet.h>
23 #include <ethernet/eth_stats.h>
24
25 #include "eth.h"
26 #include "eth_w5500_priv.h"
27
28 #define WIZNET_OUI_B0 0x00
29 #define WIZNET_OUI_B1 0x08
30 #define WIZNET_OUI_B2 0xdc
31
32 #define W5500_SPI_BLOCK_SELECT(addr) (((addr) >> 16) & 0x1f)
33 #define W5500_SPI_READ_CONTROL(addr) (W5500_SPI_BLOCK_SELECT(addr) << 3)
34 #define W5500_SPI_WRITE_CONTROL(addr) \
35 ((W5500_SPI_BLOCK_SELECT(addr) << 3) | BIT(2))
36
w5500_spi_read(const struct device * dev,uint32_t addr,uint8_t * data,uint32_t len)37 static int w5500_spi_read(const struct device *dev, uint32_t addr,
38 uint8_t *data, uint32_t len)
39 {
40 const struct w5500_config *cfg = dev->config;
41 int ret;
42 /* 3 bytes as 0x010203 during command phase */
43 uint8_t tmp[len + 3];
44
45 uint8_t cmd[3] = {
46 addr >> 8,
47 addr,
48 W5500_SPI_READ_CONTROL(addr)
49 };
50 const struct spi_buf tx_buf = {
51 .buf = cmd,
52 .len = ARRAY_SIZE(cmd),
53 };
54 const struct spi_buf_set tx = {
55 .buffers = &tx_buf,
56 .count = 1,
57 };
58 const struct spi_buf rx_buf = {
59 .buf = tmp,
60 .len = ARRAY_SIZE(tmp),
61 };
62 const struct spi_buf_set rx = {
63 .buffers = &rx_buf,
64 .count = 1,
65 };
66
67 ret = spi_transceive_dt(&cfg->spi, &tx, &rx);
68
69 if (!ret) {
70 /* skip the default dummy 0x010203 */
71 memcpy(data, &tmp[3], len);
72 }
73
74 return ret;
75 }
76
w5500_spi_write(const struct device * dev,uint32_t addr,uint8_t * data,uint32_t len)77 static int w5500_spi_write(const struct device *dev, uint32_t addr,
78 uint8_t *data, uint32_t len)
79 {
80 const struct w5500_config *cfg = dev->config;
81 int ret;
82 uint8_t cmd[3] = {
83 addr >> 8,
84 addr,
85 W5500_SPI_WRITE_CONTROL(addr),
86 };
87 const struct spi_buf tx_buf[2] = {
88 {
89 .buf = cmd,
90 .len = ARRAY_SIZE(cmd),
91 },
92 {
93 .buf = data,
94 .len = len,
95 },
96 };
97 const struct spi_buf_set tx = {
98 .buffers = tx_buf,
99 .count = ARRAY_SIZE(tx_buf),
100 };
101
102 ret = spi_write_dt(&cfg->spi, &tx);
103
104 return ret;
105 }
106
w5500_readbuf(const struct device * dev,uint16_t offset,uint8_t * buf,int len)107 static int w5500_readbuf(const struct device *dev, uint16_t offset, uint8_t *buf,
108 int len)
109 {
110 uint32_t addr;
111 int remain = 0;
112 int ret;
113 const uint32_t mem_start = W5500_Sn_RX_MEM_START;
114 const uint16_t mem_size = W5500_RX_MEM_SIZE;
115
116 offset %= mem_size;
117 addr = mem_start + offset;
118
119 if (offset + len > mem_size) {
120 remain = (offset + len) % mem_size;
121 len = mem_size - offset;
122 }
123
124 ret = w5500_spi_read(dev, addr, buf, len);
125 if (ret || !remain) {
126 return ret;
127 }
128
129 return w5500_spi_read(dev, mem_start, buf + len, remain);
130 }
131
w5500_writebuf(const struct device * dev,uint16_t offset,uint8_t * buf,int len)132 static int w5500_writebuf(const struct device *dev, uint16_t offset, uint8_t *buf,
133 int len)
134 {
135 uint32_t addr;
136 int ret = 0;
137 int remain = 0;
138 const uint32_t mem_start = W5500_Sn_TX_MEM_START;
139 const uint32_t mem_size = W5500_TX_MEM_SIZE;
140
141 offset %= mem_size;
142 addr = mem_start + offset;
143
144 if (offset + len > mem_size) {
145 remain = (offset + len) % mem_size;
146 len = mem_size - offset;
147 }
148
149 ret = w5500_spi_write(dev, addr, buf, len);
150 if (ret || !remain) {
151 return ret;
152 }
153
154 return w5500_spi_write(dev, mem_start, buf + len, remain);
155 }
156
w5500_command(const struct device * dev,uint8_t cmd)157 static int w5500_command(const struct device *dev, uint8_t cmd)
158 {
159 uint8_t reg;
160 k_timepoint_t end = sys_timepoint_calc(K_MSEC(100));
161
162 w5500_spi_write(dev, W5500_S0_CR, &cmd, 1);
163 while (1) {
164 w5500_spi_read(dev, W5500_S0_CR, ®, 1);
165 if (!reg) {
166 break;
167 }
168 if (sys_timepoint_expired(end)) {
169 return -EIO;
170 }
171 k_busy_wait(W5500_PHY_ACCESS_DELAY);
172 }
173 return 0;
174 }
175
w5500_tx(const struct device * dev,struct net_pkt * pkt)176 static int w5500_tx(const struct device *dev, struct net_pkt *pkt)
177 {
178 struct w5500_runtime *ctx = dev->data;
179 uint16_t len = net_pkt_get_len(pkt);
180 uint16_t offset;
181 uint8_t off[2];
182 int ret;
183
184 w5500_spi_read(dev, W5500_S0_TX_WR, off, 2);
185 offset = sys_get_be16(off);
186
187 if (net_pkt_read(pkt, ctx->buf, len)) {
188 return -EIO;
189 }
190
191 ret = w5500_writebuf(dev, offset, ctx->buf, len);
192 if (ret < 0) {
193 return ret;
194 }
195
196 sys_put_be16(offset + len, off);
197 w5500_spi_write(dev, W5500_S0_TX_WR, off, 2);
198
199 w5500_command(dev, S0_CR_SEND);
200 if (k_sem_take(&ctx->tx_sem, K_MSEC(10))) {
201 return -EIO;
202 }
203
204 return 0;
205 }
206
w5500_rx(const struct device * dev)207 static void w5500_rx(const struct device *dev)
208 {
209 uint8_t header[2];
210 uint8_t tmp[2];
211 uint16_t off;
212 uint16_t rx_len;
213 uint16_t rx_buf_len;
214 uint16_t read_len;
215 uint16_t reader;
216 struct net_buf *pkt_buf = NULL;
217 struct net_pkt *pkt;
218 struct w5500_runtime *ctx = dev->data;
219 const struct w5500_config *config = dev->config;
220
221 w5500_spi_read(dev, W5500_S0_RX_RSR, tmp, 2);
222 rx_buf_len = sys_get_be16(tmp);
223
224 if (rx_buf_len == 0) {
225 return;
226 }
227
228 w5500_spi_read(dev, W5500_S0_RX_RD, tmp, 2);
229 off = sys_get_be16(tmp);
230
231 w5500_readbuf(dev, off, header, 2);
232 rx_len = sys_get_be16(header) - 2;
233
234 pkt = net_pkt_rx_alloc_with_buffer(ctx->iface, rx_len,
235 AF_UNSPEC, 0, K_MSEC(config->timeout));
236 if (!pkt) {
237 eth_stats_update_errors_rx(ctx->iface);
238 return;
239 }
240
241 pkt_buf = pkt->buffer;
242
243 read_len = rx_len;
244 reader = off + 2;
245
246 do {
247 size_t frag_len;
248 uint8_t *data_ptr;
249 size_t frame_len;
250
251 data_ptr = pkt_buf->data;
252
253 frag_len = net_buf_tailroom(pkt_buf);
254
255 if (read_len > frag_len) {
256 frame_len = frag_len;
257 } else {
258 frame_len = read_len;
259 }
260
261 w5500_readbuf(dev, reader, data_ptr, frame_len);
262 net_buf_add(pkt_buf, frame_len);
263 reader += frame_len;
264
265 read_len -= frame_len;
266 pkt_buf = pkt_buf->frags;
267 } while (read_len > 0);
268
269 if (net_recv_data(ctx->iface, pkt) < 0) {
270 net_pkt_unref(pkt);
271 }
272
273 sys_put_be16(off + 2 + rx_len, tmp);
274 w5500_spi_write(dev, W5500_S0_RX_RD, tmp, 2);
275 w5500_command(dev, S0_CR_RECV);
276 }
277
w5500_thread(void * p1,void * p2,void * p3)278 static void w5500_thread(void *p1, void *p2, void *p3)
279 {
280 ARG_UNUSED(p2);
281 ARG_UNUSED(p3);
282
283 const struct device *dev = p1;
284 uint8_t ir;
285 struct w5500_runtime *ctx = dev->data;
286 const struct w5500_config *config = dev->config;
287
288 while (true) {
289 k_sem_take(&ctx->int_sem, K_FOREVER);
290
291 while (gpio_pin_get_dt(&(config->interrupt))) {
292 /* Read interrupt */
293 w5500_spi_read(dev, W5500_S0_IR, &ir, 1);
294
295 if (ir) {
296 /* Clear interrupt */
297 w5500_spi_write(dev, W5500_S0_IR, &ir, 1);
298
299 LOG_DBG("IR received");
300
301 if (ir & S0_IR_SENDOK) {
302 k_sem_give(&ctx->tx_sem);
303 LOG_DBG("TX Done");
304 }
305
306 if (ir & S0_IR_RECV) {
307 w5500_rx(dev);
308 LOG_DBG("RX Done");
309 }
310 }
311 }
312 }
313 }
314
w5500_iface_init(struct net_if * iface)315 static void w5500_iface_init(struct net_if *iface)
316 {
317 const struct device *dev = net_if_get_device(iface);
318 struct w5500_runtime *ctx = dev->data;
319
320 net_if_set_link_addr(iface, ctx->mac_addr,
321 sizeof(ctx->mac_addr),
322 NET_LINK_ETHERNET);
323
324 if (!ctx->iface) {
325 ctx->iface = iface;
326 }
327
328 ethernet_init(iface);
329 }
330
w5500_get_capabilities(const struct device * dev)331 static enum ethernet_hw_caps w5500_get_capabilities(const struct device *dev)
332 {
333 ARG_UNUSED(dev);
334
335 return ETHERNET_LINK_10BASE_T | ETHERNET_LINK_100BASE_T
336 #if defined(CONFIG_NET_PROMISCUOUS_MODE)
337 | ETHERNET_PROMISC_MODE
338 #endif
339 ;
340 }
341
w5500_set_config(const struct device * dev,enum ethernet_config_type type,const struct ethernet_config * config)342 static int w5500_set_config(const struct device *dev,
343 enum ethernet_config_type type,
344 const struct ethernet_config *config)
345 {
346 struct w5500_runtime *ctx = dev->data;
347
348 switch (type) {
349 case ETHERNET_CONFIG_TYPE_MAC_ADDRESS:
350 memcpy(ctx->mac_addr,
351 config->mac_address.addr,
352 sizeof(ctx->mac_addr));
353 w5500_spi_write(dev, W5500_SHAR, ctx->mac_addr, sizeof(ctx->mac_addr));
354 LOG_INF("%s MAC set to %02x:%02x:%02x:%02x:%02x:%02x",
355 dev->name,
356 ctx->mac_addr[0], ctx->mac_addr[1],
357 ctx->mac_addr[2], ctx->mac_addr[3],
358 ctx->mac_addr[4], ctx->mac_addr[5]);
359
360 /* Register Ethernet MAC Address with the upper layer */
361 net_if_set_link_addr(ctx->iface, ctx->mac_addr,
362 sizeof(ctx->mac_addr),
363 NET_LINK_ETHERNET);
364
365 return 0;
366 case ETHERNET_CONFIG_TYPE_PROMISC_MODE:
367 if (IS_ENABLED(CONFIG_NET_PROMISCUOUS_MODE)) {
368 uint8_t mode;
369 uint8_t mr = W5500_S0_MR_MF;
370
371 w5500_spi_read(dev, W5500_S0_MR, &mode, 1);
372
373 if (config->promisc_mode) {
374 if (!(mode & BIT(mr))) {
375 return -EALREADY;
376 }
377
378 /* disable MAC filtering */
379 WRITE_BIT(mode, mr, 0);
380 } else {
381 if (mode & BIT(mr)) {
382 return -EALREADY;
383 }
384
385 /* enable MAC filtering */
386 WRITE_BIT(mode, mr, 1);
387 }
388
389 return w5500_spi_write(dev, W5500_S0_MR, &mode, 1);
390 }
391
392 return -ENOTSUP;
393 default:
394 return -ENOTSUP;
395 }
396 }
397
w5500_hw_start(const struct device * dev)398 static int w5500_hw_start(const struct device *dev)
399 {
400 uint8_t mode = S0_MR_MACRAW | BIT(W5500_S0_MR_MF);
401 uint8_t mask = IR_S0;
402
403 /* configure Socket 0 with MACRAW mode and MAC filtering enabled */
404 w5500_spi_write(dev, W5500_S0_MR, &mode, 1);
405 w5500_command(dev, S0_CR_OPEN);
406
407 /* enable interrupt */
408 w5500_spi_write(dev, W5500_SIMR, &mask, 1);
409
410 return 0;
411 }
412
w5500_hw_stop(const struct device * dev)413 static int w5500_hw_stop(const struct device *dev)
414 {
415 uint8_t mask = 0;
416
417 /* disable interrupt */
418 w5500_spi_write(dev, W5500_SIMR, &mask, 1);
419 w5500_command(dev, S0_CR_CLOSE);
420
421 return 0;
422 }
423
424 static struct ethernet_api w5500_api_funcs = {
425 .iface_api.init = w5500_iface_init,
426 .get_capabilities = w5500_get_capabilities,
427 .set_config = w5500_set_config,
428 .start = w5500_hw_start,
429 .stop = w5500_hw_stop,
430 .send = w5500_tx,
431 };
432
w5500_hw_reset(const struct device * dev)433 static int w5500_hw_reset(const struct device *dev)
434 {
435 int ret;
436 uint8_t mask = 0;
437 uint8_t tmp = MR_RST;
438
439 ret = w5500_spi_write(dev, W5500_MR, &tmp, 1);
440 if (ret < 0) {
441 return ret;
442 }
443
444 k_msleep(5);
445 tmp = MR_PB;
446 w5500_spi_write(dev, W5500_MR, &tmp, 1);
447
448 /* disable interrupt */
449 return w5500_spi_write(dev, W5500_SIMR, &mask, 1);
450 }
451
w5500_gpio_callback(const struct device * dev,struct gpio_callback * cb,uint32_t pins)452 static void w5500_gpio_callback(const struct device *dev,
453 struct gpio_callback *cb,
454 uint32_t pins)
455 {
456 struct w5500_runtime *ctx =
457 CONTAINER_OF(cb, struct w5500_runtime, gpio_cb);
458
459 k_sem_give(&ctx->int_sem);
460 }
461
w5500_set_macaddr(const struct device * dev)462 static void w5500_set_macaddr(const struct device *dev)
463 {
464 struct w5500_runtime *ctx = dev->data;
465
466 #if DT_INST_PROP(0, zephyr_random_mac_address)
467 /* override vendor bytes */
468 memset(ctx->mac_addr, '\0', sizeof(ctx->mac_addr));
469 ctx->mac_addr[0] = WIZNET_OUI_B0;
470 ctx->mac_addr[1] = WIZNET_OUI_B1;
471 ctx->mac_addr[2] = WIZNET_OUI_B2;
472 if (ctx->generate_mac) {
473 ctx->generate_mac(ctx->mac_addr);
474 }
475 #endif
476
477 w5500_spi_write(dev, W5500_SHAR, ctx->mac_addr, sizeof(ctx->mac_addr));
478 }
479
w5500_memory_configure(const struct device * dev)480 static void w5500_memory_configure(const struct device *dev)
481 {
482 int i;
483 uint8_t mem = 0x10;
484
485 /* Configure RX & TX memory to 16K */
486 w5500_spi_write(dev, W5500_Sn_RXMEM_SIZE(0), &mem, 1);
487 w5500_spi_write(dev, W5500_Sn_TXMEM_SIZE(0), &mem, 1);
488
489 mem = 0;
490 for (i = 1; i < 8; i++) {
491 w5500_spi_write(dev, W5500_Sn_RXMEM_SIZE(i), &mem, 1);
492 w5500_spi_write(dev, W5500_Sn_TXMEM_SIZE(i), &mem, 1);
493 }
494 }
495
w5500_random_mac(uint8_t * mac_addr)496 static void w5500_random_mac(uint8_t *mac_addr)
497 {
498 gen_random_mac(mac_addr, WIZNET_OUI_B0, WIZNET_OUI_B1, WIZNET_OUI_B2);
499 }
500
w5500_init(const struct device * dev)501 static int w5500_init(const struct device *dev)
502 {
503 int err;
504 uint8_t rtr[2];
505 const struct w5500_config *config = dev->config;
506 struct w5500_runtime *ctx = dev->data;
507
508 if (!spi_is_ready_dt(&config->spi)) {
509 LOG_ERR("SPI master port %s not ready", config->spi.bus->name);
510 return -EINVAL;
511 }
512
513 if (!gpio_is_ready_dt(&config->interrupt)) {
514 LOG_ERR("GPIO port %s not ready", config->interrupt.port->name);
515 return -EINVAL;
516 }
517
518 if (gpio_pin_configure_dt(&config->interrupt, GPIO_INPUT)) {
519 LOG_ERR("Unable to configure GPIO pin %u", config->interrupt.pin);
520 return -EINVAL;
521 }
522
523 gpio_init_callback(&(ctx->gpio_cb), w5500_gpio_callback,
524 BIT(config->interrupt.pin));
525
526 if (gpio_add_callback(config->interrupt.port, &(ctx->gpio_cb))) {
527 return -EINVAL;
528 }
529
530 gpio_pin_interrupt_configure_dt(&config->interrupt,
531 GPIO_INT_EDGE_FALLING);
532
533 if (config->reset.port) {
534 if (!gpio_is_ready_dt(&config->reset)) {
535 LOG_ERR("GPIO port %s not ready", config->reset.port->name);
536 return -EINVAL;
537 }
538 if (gpio_pin_configure_dt(&config->reset, GPIO_OUTPUT)) {
539 LOG_ERR("Unable to configure GPIO pin %u", config->reset.pin);
540 return -EINVAL;
541 }
542 gpio_pin_set_dt(&config->reset, 0);
543 k_usleep(500);
544 }
545
546 err = w5500_hw_reset(dev);
547 if (err) {
548 LOG_ERR("Reset failed");
549 return err;
550 }
551
552 w5500_set_macaddr(dev);
553 w5500_memory_configure(dev);
554
555 /* check retry time value */
556 w5500_spi_read(dev, W5500_RTR, rtr, 2);
557 if (sys_get_be16(rtr) != RTR_DEFAULT) {
558 LOG_ERR("Unable to read RTR register");
559 return -ENODEV;
560 }
561
562 k_thread_create(&ctx->thread, ctx->thread_stack,
563 CONFIG_ETH_W5500_RX_THREAD_STACK_SIZE,
564 w5500_thread,
565 (void *)dev, NULL, NULL,
566 K_PRIO_COOP(CONFIG_ETH_W5500_RX_THREAD_PRIO),
567 0, K_NO_WAIT);
568
569 LOG_INF("W5500 Initialized");
570
571 return 0;
572 }
573
574 static struct w5500_runtime w5500_0_runtime = {
575 #if NODE_HAS_VALID_MAC_ADDR(DT_DRV_INST(0))
576 .mac_addr = DT_INST_PROP(0, local_mac_address),
577 #endif
578 .generate_mac = w5500_random_mac,
579 .tx_sem = Z_SEM_INITIALIZER(w5500_0_runtime.tx_sem,
580 1, UINT_MAX),
581 .int_sem = Z_SEM_INITIALIZER(w5500_0_runtime.int_sem,
582 0, UINT_MAX),
583 };
584
585 static const struct w5500_config w5500_0_config = {
586 .spi = SPI_DT_SPEC_INST_GET(0, SPI_WORD_SET(8), 0),
587 .interrupt = GPIO_DT_SPEC_INST_GET(0, int_gpios),
588 .reset = GPIO_DT_SPEC_INST_GET_OR(0, reset_gpios, { 0 }),
589 .timeout = CONFIG_ETH_W5500_TIMEOUT,
590 };
591
592 ETH_NET_DEVICE_DT_INST_DEFINE(0,
593 w5500_init, NULL,
594 &w5500_0_runtime, &w5500_0_config,
595 CONFIG_ETH_INIT_PRIORITY, &w5500_api_funcs, NET_ETH_MTU);
596
