1 /* ENC28J60 Stand-alone Ethernet Controller with SPI
2 *
3 * Copyright (c) 2016 Intel Corporation
4 *
5 * SPDX-License-Identifier: Apache-2.0
6 */
7
8 #define DT_DRV_COMPAT microchip_enc28j60
9
10 #define LOG_MODULE_NAME eth_enc28j60
11 #define LOG_LEVEL CONFIG_ETHERNET_LOG_LEVEL
12
13 #include <zephyr/logging/log.h>
14 LOG_MODULE_REGISTER(LOG_MODULE_NAME);
15
16 #include <zephyr/kernel.h>
17 #include <zephyr/device.h>
18 #include <string.h>
19 #include <errno.h>
20 #include <zephyr/drivers/gpio.h>
21 #include <zephyr/drivers/spi.h>
22 #include <zephyr/net/net_pkt.h>
23 #include <zephyr/net/net_if.h>
24 #include <zephyr/net/ethernet.h>
25 #include <ethernet/eth_stats.h>
26
27 #include "eth_enc28j60_priv.h"
28
29 #define D10D24S 11
30
eth_enc28j60_soft_reset(const struct device * dev)31 static int eth_enc28j60_soft_reset(const struct device *dev)
32 {
33 const struct eth_enc28j60_config *config = dev->config;
34 uint8_t buf[2] = { ENC28J60_SPI_SC, 0xFF };
35 const struct spi_buf tx_buf = {
36 .buf = buf,
37 .len = 1,
38 };
39 const struct spi_buf_set tx = {
40 .buffers = &tx_buf,
41 .count = 1
42 };
43
44 return spi_write_dt(&config->spi, &tx);
45 }
46
eth_enc28j60_set_bank(const struct device * dev,uint16_t reg_addr)47 static void eth_enc28j60_set_bank(const struct device *dev, uint16_t reg_addr)
48 {
49 const struct eth_enc28j60_config *config = dev->config;
50 uint8_t buf[2];
51 const struct spi_buf tx_buf = {
52 .buf = buf,
53 .len = 2
54 };
55 const struct spi_buf rx_buf = {
56 .buf = buf,
57 .len = 2
58 };
59 const struct spi_buf_set tx = {
60 .buffers = &tx_buf,
61 .count = 1
62 };
63 const struct spi_buf_set rx = {
64 .buffers = &rx_buf,
65 .count = 1
66 };
67
68 buf[0] = ENC28J60_SPI_RCR | ENC28J60_REG_ECON1;
69 buf[1] = 0x0;
70
71 if (!spi_transceive_dt(&config->spi, &tx, &rx)) {
72 buf[0] = ENC28J60_SPI_WCR | ENC28J60_REG_ECON1;
73 buf[1] = (buf[1] & 0xFC) | ((reg_addr >> 8) & 0x0F);
74
75 spi_write_dt(&config->spi, &tx);
76 } else {
77 LOG_DBG("%s: Failure while setting bank to 0x%04x", dev->name, reg_addr);
78 }
79 }
80
eth_enc28j60_write_reg(const struct device * dev,uint16_t reg_addr,uint8_t value)81 static void eth_enc28j60_write_reg(const struct device *dev,
82 uint16_t reg_addr,
83 uint8_t value)
84 {
85 const struct eth_enc28j60_config *config = dev->config;
86 uint8_t buf[2];
87 const struct spi_buf tx_buf = {
88 .buf = buf,
89 .len = 2
90 };
91 const struct spi_buf_set tx = {
92 .buffers = &tx_buf,
93 .count = 1
94 };
95
96 buf[0] = ENC28J60_SPI_WCR | (reg_addr & 0xFF);
97 buf[1] = value;
98
99 spi_write_dt(&config->spi, &tx);
100 }
101
eth_enc28j60_read_reg(const struct device * dev,uint16_t reg_addr,uint8_t * value)102 static void eth_enc28j60_read_reg(const struct device *dev, uint16_t reg_addr,
103 uint8_t *value)
104 {
105 const struct eth_enc28j60_config *config = dev->config;
106 uint8_t buf[3];
107 const struct spi_buf tx_buf = {
108 .buf = buf,
109 .len = 2
110 };
111 const struct spi_buf_set tx = {
112 .buffers = &tx_buf,
113 .count = 1
114 };
115 struct spi_buf rx_buf = {
116 .buf = buf,
117 };
118 const struct spi_buf_set rx = {
119 .buffers = &rx_buf,
120 .count = 1
121 };
122 uint8_t rx_size = 2U;
123
124 if (reg_addr & 0xF000) {
125 rx_size = 3U;
126 }
127
128 rx_buf.len = rx_size;
129
130 buf[0] = ENC28J60_SPI_RCR | (reg_addr & 0xFF);
131 buf[1] = 0x0;
132
133 if (!spi_transceive_dt(&config->spi, &tx, &rx)) {
134 *value = buf[rx_size - 1];
135 } else {
136 LOG_DBG("%s: Failure while reading register 0x%04x", dev->name, reg_addr);
137 *value = 0U;
138 }
139 }
140
eth_enc28j60_set_eth_reg(const struct device * dev,uint16_t reg_addr,uint8_t value)141 static void eth_enc28j60_set_eth_reg(const struct device *dev,
142 uint16_t reg_addr,
143 uint8_t value)
144 {
145 const struct eth_enc28j60_config *config = dev->config;
146 uint8_t buf[2];
147 const struct spi_buf tx_buf = {
148 .buf = buf,
149 .len = 2
150 };
151 const struct spi_buf_set tx = {
152 .buffers = &tx_buf,
153 .count = 1
154 };
155
156 buf[0] = ENC28J60_SPI_BFS | (reg_addr & 0xFF);
157 buf[1] = value;
158
159 spi_write_dt(&config->spi, &tx);
160 }
161
162
eth_enc28j60_clear_eth_reg(const struct device * dev,uint16_t reg_addr,uint8_t value)163 static void eth_enc28j60_clear_eth_reg(const struct device *dev,
164 uint16_t reg_addr,
165 uint8_t value)
166 {
167 const struct eth_enc28j60_config *config = dev->config;
168 uint8_t buf[2];
169 const struct spi_buf tx_buf = {
170 .buf = buf,
171 .len = 2
172 };
173 const struct spi_buf_set tx = {
174 .buffers = &tx_buf,
175 .count = 1
176 };
177
178 buf[0] = ENC28J60_SPI_BFC | (reg_addr & 0xFF);
179 buf[1] = value;
180
181 spi_write_dt(&config->spi, &tx);
182 }
183
eth_enc28j60_write_mem(const struct device * dev,uint8_t * data_buffer,uint16_t buf_len)184 static void eth_enc28j60_write_mem(const struct device *dev,
185 uint8_t *data_buffer,
186 uint16_t buf_len)
187 {
188 const struct eth_enc28j60_config *config = dev->config;
189 uint8_t buf[1] = { ENC28J60_SPI_WBM };
190 struct spi_buf tx_buf[2] = {
191 {
192 .buf = buf,
193 .len = 1
194 },
195 };
196 const struct spi_buf_set tx = {
197 .buffers = tx_buf,
198 .count = 2
199 };
200 uint16_t num_segments;
201 uint16_t num_remaining;
202 int i;
203
204 num_segments = buf_len / MAX_BUFFER_LENGTH;
205 num_remaining = buf_len - MAX_BUFFER_LENGTH * num_segments;
206
207 for (i = 0; i < num_segments; i++, data_buffer += MAX_BUFFER_LENGTH) {
208 tx_buf[1].buf = data_buffer;
209 tx_buf[1].len = MAX_BUFFER_LENGTH;
210
211 if (spi_write_dt(&config->spi, &tx)) {
212 LOG_ERR("%s: Failed to write memory", dev->name);
213 return;
214 }
215 }
216
217 if (num_remaining > 0) {
218 tx_buf[1].buf = data_buffer;
219 tx_buf[1].len = num_remaining;
220
221 if (spi_write_dt(&config->spi, &tx)) {
222 LOG_ERR("%s: Failed to write memory", dev->name);
223 }
224 }
225 }
226
eth_enc28j60_read_mem(const struct device * dev,uint8_t * data_buffer,uint16_t buf_len)227 static void eth_enc28j60_read_mem(const struct device *dev,
228 uint8_t *data_buffer,
229 uint16_t buf_len)
230 {
231 const struct eth_enc28j60_config *config = dev->config;
232 uint8_t buf[1] = { ENC28J60_SPI_RBM };
233 const struct spi_buf tx_buf = {
234 .buf = buf,
235 .len = 1
236 };
237 const struct spi_buf_set tx = {
238 .buffers = &tx_buf,
239 .count = 1
240 };
241 struct spi_buf rx_buf[2] = {
242 {
243 .buf = NULL,
244 .len = 1
245 },
246 };
247 const struct spi_buf_set rx = {
248 .buffers = rx_buf,
249 .count = 2
250 };
251 uint16_t num_segments;
252 uint16_t num_remaining;
253 int i;
254
255 num_segments = buf_len / MAX_BUFFER_LENGTH;
256 num_remaining = buf_len - MAX_BUFFER_LENGTH * num_segments;
257
258 for (i = 0; i < num_segments; i++, data_buffer += MAX_BUFFER_LENGTH) {
259
260 rx_buf[1].buf = data_buffer;
261 rx_buf[1].len = MAX_BUFFER_LENGTH;
262
263 if (spi_transceive_dt(&config->spi, &tx, &rx)) {
264 LOG_ERR("%s: Failed to read memory", dev->name);
265 return;
266 }
267 }
268
269 if (num_remaining > 0) {
270 rx_buf[1].buf = data_buffer;
271 rx_buf[1].len = num_remaining;
272
273 if (spi_transceive_dt(&config->spi, &tx, &rx)) {
274 LOG_ERR("%s: Failed to read memory", dev->name);
275 }
276 }
277 }
278
eth_enc28j60_write_phy(const struct device * dev,uint16_t reg_addr,int16_t data)279 static void eth_enc28j60_write_phy(const struct device *dev,
280 uint16_t reg_addr,
281 int16_t data)
282 {
283 uint8_t data_mistat;
284
285 eth_enc28j60_set_bank(dev, ENC28J60_REG_MIREGADR);
286 eth_enc28j60_write_reg(dev, ENC28J60_REG_MIREGADR, reg_addr);
287 eth_enc28j60_write_reg(dev, ENC28J60_REG_MIWRL, data & 0xFF);
288 eth_enc28j60_write_reg(dev, ENC28J60_REG_MIWRH, data >> 8);
289 eth_enc28j60_set_bank(dev, ENC28J60_REG_MISTAT);
290
291 do {
292 /* wait 10.24 useconds */
293 k_busy_wait(D10D24S);
294 eth_enc28j60_read_reg(dev, ENC28J60_REG_MISTAT,
295 &data_mistat);
296 } while ((data_mistat & ENC28J60_BIT_MISTAT_BUSY));
297 }
298
eth_enc28j60_read_phy(const struct device * dev,uint16_t reg_addr,int16_t * data)299 static void eth_enc28j60_read_phy(const struct device *dev,
300 uint16_t reg_addr,
301 int16_t *data)
302 {
303 uint8_t data_mistat;
304 uint8_t lsb;
305 uint8_t msb;
306
307 eth_enc28j60_set_bank(dev, ENC28J60_REG_MIREGADR);
308 eth_enc28j60_write_reg(dev, ENC28J60_REG_MIREGADR, reg_addr);
309 eth_enc28j60_write_reg(dev, ENC28J60_REG_MICMD,
310 ENC28J60_BIT_MICMD_MIIRD);
311 eth_enc28j60_set_bank(dev, ENC28J60_REG_MISTAT);
312
313 do {
314 /* wait 10.24 useconds */
315 k_busy_wait(D10D24S);
316 eth_enc28j60_read_reg(dev, ENC28J60_REG_MISTAT,
317 &data_mistat);
318 } while ((data_mistat & ENC28J60_BIT_MISTAT_BUSY));
319
320 eth_enc28j60_set_bank(dev, ENC28J60_REG_MIREGADR);
321 eth_enc28j60_write_reg(dev, ENC28J60_REG_MICMD, 0x0);
322 eth_enc28j60_read_reg(dev, ENC28J60_REG_MIRDL, &lsb);
323 eth_enc28j60_read_reg(dev, ENC28J60_REG_MIRDH, &msb);
324
325 *data = (msb << 8) | lsb;
326 }
327
eth_enc28j60_gpio_callback(const struct device * dev,struct gpio_callback * cb,uint32_t pins)328 static void eth_enc28j60_gpio_callback(const struct device *dev,
329 struct gpio_callback *cb,
330 uint32_t pins)
331 {
332 struct eth_enc28j60_runtime *context =
333 CONTAINER_OF(cb, struct eth_enc28j60_runtime, gpio_cb);
334
335 k_sem_give(&context->int_sem);
336 }
337
eth_enc28j60_init_buffers(const struct device * dev)338 static int eth_enc28j60_init_buffers(const struct device *dev)
339 {
340 uint8_t data_estat;
341
342 /* Reception buffers initialization */
343 eth_enc28j60_set_bank(dev, ENC28J60_REG_ERXSTL);
344 eth_enc28j60_write_reg(dev, ENC28J60_REG_ERXSTL,
345 ENC28J60_RXSTART & 0xFF);
346 eth_enc28j60_write_reg(dev, ENC28J60_REG_ERXSTH,
347 ENC28J60_RXSTART >> 8);
348 eth_enc28j60_write_reg(dev, ENC28J60_REG_ERXRDPTL,
349 ENC28J60_RXSTART & 0xFF);
350 eth_enc28j60_write_reg(dev, ENC28J60_REG_ERXRDPTH,
351 ENC28J60_RXSTART >> 8);
352 eth_enc28j60_write_reg(dev, ENC28J60_REG_ERXNDL,
353 ENC28J60_RXEND & 0xFF);
354 eth_enc28j60_write_reg(dev, ENC28J60_REG_ERXNDH,
355 ENC28J60_RXEND >> 8);
356 eth_enc28j60_write_reg(dev, ENC28J60_REG_ETXSTL,
357 ENC28J60_TXSTART & 0xFF);
358 eth_enc28j60_write_reg(dev, ENC28J60_REG_ETXSTH,
359 ENC28J60_TXSTART >> 8);
360 eth_enc28j60_write_reg(dev, ENC28J60_REG_ETXNDL,
361 ENC28J60_TXEND & 0xFF);
362 eth_enc28j60_write_reg(dev, ENC28J60_REG_ETXNDH,
363 ENC28J60_TXEND >> 8);
364 eth_enc28j60_write_reg(dev, ENC28J60_REG_ERDPTL,
365 ENC28J60_RXSTART & 0xFF);
366 eth_enc28j60_write_reg(dev, ENC28J60_REG_ERDPTH,
367 ENC28J60_RXSTART >> 8);
368 eth_enc28j60_write_reg(dev, ENC28J60_REG_EWRPTL,
369 ENC28J60_TXSTART & 0xFF);
370 eth_enc28j60_write_reg(dev, ENC28J60_REG_EWRPTH,
371 ENC28J60_TXSTART >> 8);
372
373 eth_enc28j60_set_bank(dev, ENC28J60_REG_ERXFCON);
374 eth_enc28j60_write_reg(dev, ENC28J60_REG_ERXFCON,
375 ENC28J60_RECEIVE_FILTERS);
376
377 /* Waiting for OST */
378 /* 32 bits for this timer should be fine, rollover not an issue with initialisation */
379 uint32_t start_wait = (uint32_t) k_uptime_get();
380 do {
381 /* If the CLK isn't ready don't wait forever */
382 if ((k_uptime_get_32() - start_wait) > CONFIG_ETH_ENC28J60_CLKRDY_INIT_WAIT_MS) {
383 LOG_ERR("OST wait timed out");
384 return -ETIMEDOUT;
385 }
386 /* wait 10.24 useconds */
387 k_busy_wait(D10D24S);
388 eth_enc28j60_read_reg(dev, ENC28J60_REG_ESTAT, &data_estat);
389 } while (!(data_estat & ENC28J60_BIT_ESTAT_CLKRDY));
390
391 return 0;
392 }
393
eth_enc28j60_init_mac(const struct device * dev)394 static void eth_enc28j60_init_mac(const struct device *dev)
395 {
396 const struct eth_enc28j60_config *config = dev->config;
397 struct eth_enc28j60_runtime *context = dev->data;
398 uint8_t data_macon;
399
400 eth_enc28j60_set_bank(dev, ENC28J60_REG_MACON1);
401
402 /* Set MARXEN to enable MAC to receive frames */
403 eth_enc28j60_read_reg(dev, ENC28J60_REG_MACON1, &data_macon);
404 data_macon |= ENC28J60_BIT_MACON1_MARXEN | ENC28J60_BIT_MACON1_RXPAUS
405 | ENC28J60_BIT_MACON1_TXPAUS;
406 eth_enc28j60_write_reg(dev, ENC28J60_REG_MACON1, data_macon);
407
408 data_macon = ENC28J60_MAC_CONFIG;
409
410 if (config->full_duplex) {
411 data_macon |= ENC28J60_BIT_MACON3_FULDPX;
412 }
413
414 eth_enc28j60_write_reg(dev, ENC28J60_REG_MACON3, data_macon);
415 eth_enc28j60_write_reg(dev, ENC28J60_REG_MAIPGL, ENC28J60_MAC_NBBIPGL);
416
417 if (config->full_duplex) {
418 eth_enc28j60_write_reg(dev, ENC28J60_REG_MAIPGH,
419 ENC28J60_MAC_NBBIPGH);
420 eth_enc28j60_write_reg(dev, ENC28J60_REG_MABBIPG,
421 ENC28J60_MAC_BBIPG_FD);
422 } else {
423 eth_enc28j60_write_reg(dev, ENC28J60_REG_MABBIPG,
424 ENC28J60_MAC_BBIPG_HD);
425 eth_enc28j60_write_reg(dev, ENC28J60_REG_MACON4, 1 << 6);
426 }
427
428 /* Configure MAC address */
429 eth_enc28j60_set_bank(dev, ENC28J60_REG_MAADR1);
430 eth_enc28j60_write_reg(dev, ENC28J60_REG_MAADR6,
431 context->mac_address[5]);
432 eth_enc28j60_write_reg(dev, ENC28J60_REG_MAADR5,
433 context->mac_address[4]);
434 eth_enc28j60_write_reg(dev, ENC28J60_REG_MAADR4,
435 context->mac_address[3]);
436 eth_enc28j60_write_reg(dev, ENC28J60_REG_MAADR3,
437 context->mac_address[2]);
438 eth_enc28j60_write_reg(dev, ENC28J60_REG_MAADR2,
439 context->mac_address[1]);
440 eth_enc28j60_write_reg(dev, ENC28J60_REG_MAADR1,
441 context->mac_address[0]);
442 }
443
eth_enc28j60_init_phy(const struct device * dev)444 static void eth_enc28j60_init_phy(const struct device *dev)
445 {
446 const struct eth_enc28j60_config *config = dev->config;
447
448 if (config->full_duplex) {
449 eth_enc28j60_write_phy(dev, ENC28J60_PHY_PHCON1,
450 ENC28J60_BIT_PHCON1_PDPXMD);
451 eth_enc28j60_write_phy(dev, ENC28J60_PHY_PHCON2, 0x0);
452 } else {
453 eth_enc28j60_write_phy(dev, ENC28J60_PHY_PHCON1, 0x0);
454 eth_enc28j60_write_phy(dev, ENC28J60_PHY_PHCON2,
455 ENC28J60_BIT_PHCON2_HDLDIS);
456 }
457 }
458
get_iface(struct eth_enc28j60_runtime * ctx,uint16_t vlan_tag)459 static struct net_if *get_iface(struct eth_enc28j60_runtime *ctx,
460 uint16_t vlan_tag)
461 {
462 #if defined(CONFIG_NET_VLAN)
463 struct net_if *iface;
464
465 iface = net_eth_get_vlan_iface(ctx->iface, vlan_tag);
466 if (!iface) {
467 return ctx->iface;
468 }
469
470 return iface;
471 #else
472 ARG_UNUSED(vlan_tag);
473
474 return ctx->iface;
475 #endif
476 }
477
eth_enc28j60_tx(const struct device * dev,struct net_pkt * pkt)478 static int eth_enc28j60_tx(const struct device *dev, struct net_pkt *pkt)
479 {
480 struct eth_enc28j60_runtime *context = dev->data;
481 uint16_t tx_bufaddr = ENC28J60_TXSTART;
482 uint16_t len = net_pkt_get_len(pkt);
483 uint8_t per_packet_control;
484 uint16_t tx_bufaddr_end;
485 struct net_buf *frag;
486 uint8_t tx_end;
487
488 LOG_DBG("%s: pkt %p (len %u)", dev->name, pkt, len);
489
490 k_sem_take(&context->tx_rx_sem, K_FOREVER);
491
492 /* Latest errata sheet: DS80349C
493 * always reset transmit logic (Errata Issue 12)
494 * the Microchip TCP/IP stack implementation used to first check
495 * whether TXERIF is set and only then reset the transmit logic
496 * but this has been changed in later versions; possibly they
497 * have a reason for this; they don't mention this in the errata
498 * sheet
499 */
500 eth_enc28j60_set_eth_reg(dev, ENC28J60_REG_ECON1,
501 ENC28J60_BIT_ECON1_TXRST);
502 eth_enc28j60_clear_eth_reg(dev, ENC28J60_REG_ECON1,
503 ENC28J60_BIT_ECON1_TXRST);
504
505 /* Write the buffer content into the transmission buffer */
506 eth_enc28j60_set_bank(dev, ENC28J60_REG_ETXSTL);
507 eth_enc28j60_write_reg(dev, ENC28J60_REG_EWRPTL, tx_bufaddr & 0xFF);
508 eth_enc28j60_write_reg(dev, ENC28J60_REG_EWRPTH, tx_bufaddr >> 8);
509 eth_enc28j60_write_reg(dev, ENC28J60_REG_ETXSTL, tx_bufaddr & 0xFF);
510 eth_enc28j60_write_reg(dev, ENC28J60_REG_ETXSTH, tx_bufaddr >> 8);
511
512 /* Write the data into the buffer */
513 per_packet_control = ENC28J60_PPCTL_BYTE;
514 eth_enc28j60_write_mem(dev, &per_packet_control, 1);
515
516 for (frag = pkt->frags; frag; frag = frag->frags) {
517 eth_enc28j60_write_mem(dev, frag->data, frag->len);
518 }
519
520 tx_bufaddr_end = tx_bufaddr + len;
521 eth_enc28j60_write_reg(dev, ENC28J60_REG_ETXNDL,
522 tx_bufaddr_end & 0xFF);
523 eth_enc28j60_write_reg(dev, ENC28J60_REG_ETXNDH, tx_bufaddr_end >> 8);
524
525 /* Signal ENC28J60 to send the buffer */
526 eth_enc28j60_set_eth_reg(dev, ENC28J60_REG_ECON1,
527 ENC28J60_BIT_ECON1_TXRTS);
528
529 do {
530 /* wait 10.24 useconds */
531 k_busy_wait(D10D24S);
532 eth_enc28j60_read_reg(dev, ENC28J60_REG_EIR, &tx_end);
533 tx_end &= ENC28J60_BIT_EIR_TXIF;
534 } while (!tx_end);
535
536
537 eth_enc28j60_read_reg(dev, ENC28J60_REG_ESTAT, &tx_end);
538
539 k_sem_give(&context->tx_rx_sem);
540
541 if (tx_end & ENC28J60_BIT_ESTAT_TXABRT) {
542 LOG_ERR("%s: TX failed!", dev->name);
543 return -EIO;
544 }
545
546 LOG_DBG("%s: Tx successful", dev->name);
547
548 return 0;
549 }
550
enc28j60_read_packet(const struct device * dev,uint16_t * vlan_tag,uint16_t frm_len)551 static void enc28j60_read_packet(const struct device *dev, uint16_t *vlan_tag,
552 uint16_t frm_len)
553 {
554 const struct eth_enc28j60_config *config = dev->config;
555 struct eth_enc28j60_runtime *context = dev->data;
556 struct net_buf *pkt_buf;
557 struct net_pkt *pkt;
558 uint16_t lengthfr;
559 uint8_t dummy[4];
560
561 /* Get the frame from the buffer */
562 pkt = net_pkt_rx_alloc_with_buffer(get_iface(context, *vlan_tag), frm_len,
563 AF_UNSPEC, 0, K_MSEC(config->timeout));
564 if (!pkt) {
565 LOG_ERR("%s: Could not allocate rx buffer", dev->name);
566 eth_stats_update_errors_rx(get_iface(context, *vlan_tag));
567 return;
568 }
569
570 pkt_buf = pkt->buffer;
571 lengthfr = frm_len;
572
573 do {
574 size_t frag_len;
575 uint8_t *data_ptr;
576 size_t spi_frame_len;
577
578 data_ptr = pkt_buf->data;
579
580 /* Review the space available for the new frag */
581 frag_len = net_buf_tailroom(pkt_buf);
582
583 if (frm_len > frag_len) {
584 spi_frame_len = frag_len;
585 } else {
586 spi_frame_len = frm_len;
587 }
588
589 eth_enc28j60_read_mem(dev, data_ptr, spi_frame_len);
590
591 net_buf_add(pkt_buf, spi_frame_len);
592
593 /* One fragment has been written via SPI */
594 frm_len -= spi_frame_len;
595 pkt_buf = pkt_buf->frags;
596 } while (frm_len > 0);
597
598 /* Let's pop the useless CRC */
599 eth_enc28j60_read_mem(dev, dummy, 4);
600
601 /* Pops one padding byte from spi circular buffer
602 * introduced by the device when the frame length is odd
603 */
604 if (lengthfr & 0x01) {
605 eth_enc28j60_read_mem(dev, dummy, 1);
606 }
607
608 #if defined(CONFIG_NET_VLAN)
609 struct net_eth_hdr *hdr = NET_ETH_HDR(pkt);
610
611 if (ntohs(hdr->type) == NET_ETH_PTYPE_VLAN) {
612 struct net_eth_vlan_hdr *hdr_vlan =
613 (struct net_eth_vlan_hdr *)NET_ETH_HDR(pkt);
614
615 net_pkt_set_vlan_tci(pkt, ntohs(hdr_vlan->vlan.tci));
616 *vlan_tag = net_pkt_vlan_tag(pkt);
617
618 #if CONFIG_NET_TC_RX_COUNT > 1
619 enum net_priority prio;
620
621 prio = net_vlan2priority(net_pkt_vlan_priority(pkt));
622 net_pkt_set_priority(pkt, prio);
623 #endif
624 } else {
625 net_pkt_set_iface(pkt, context->iface);
626 }
627 #else /* CONFIG_NET_VLAN */
628 net_pkt_set_iface(pkt, context->iface);
629 #endif /* CONFIG_NET_VLAN */
630
631 /* Feed buffer frame to IP stack */
632 LOG_DBG("%s: Received packet of length %u", dev->name, lengthfr);
633 if (net_recv_data(net_pkt_iface(pkt), pkt) < 0) {
634 net_pkt_unref(pkt);
635 }
636 }
637
eth_enc28j60_rx(const struct device * dev,uint16_t * vlan_tag)638 static int eth_enc28j60_rx(const struct device *dev, uint16_t *vlan_tag)
639 {
640 struct eth_enc28j60_runtime *context = dev->data;
641 uint8_t counter;
642
643 /* Errata 6. The Receive Packet Pending Interrupt Flag (EIR.PKTIF)
644 * does not reliably/accurately report the status of pending packet.
645 * Use EPKTCNT register instead.
646 */
647 eth_enc28j60_set_bank(dev, ENC28J60_REG_EPKTCNT);
648 eth_enc28j60_read_reg(dev, ENC28J60_REG_EPKTCNT, &counter);
649 if (!counter) {
650 return 0;
651 }
652
653 k_sem_take(&context->tx_rx_sem, K_FOREVER);
654
655 do {
656 uint16_t frm_len = 0U;
657 uint8_t info[RSV_SIZE];
658 uint16_t next_packet;
659 uint8_t rdptl = 0U;
660 uint8_t rdpth = 0U;
661
662 /* remove read fifo address to packet header address */
663 eth_enc28j60_set_bank(dev, ENC28J60_REG_ERXRDPTL);
664 eth_enc28j60_read_reg(dev, ENC28J60_REG_ERXRDPTL, &rdptl);
665 eth_enc28j60_read_reg(dev, ENC28J60_REG_ERXRDPTH, &rdpth);
666 eth_enc28j60_write_reg(dev, ENC28J60_REG_ERDPTL, rdptl);
667 eth_enc28j60_write_reg(dev, ENC28J60_REG_ERDPTH, rdpth);
668
669 /* Read address for next packet */
670 eth_enc28j60_read_mem(dev, info, 2);
671 next_packet = info[0] | (uint16_t)info[1] << 8;
672
673 /* Errata 14. Even values in ERXRDPT
674 * may corrupt receive buffer.
675 No need adjust next packet
676 if (next_packet == 0) {
677 next_packet = ENC28J60_RXEND;
678 } else if (!(next_packet & 0x01)) {
679 next_packet--;
680 }*/
681
682 /* Read reception status vector */
683 eth_enc28j60_read_mem(dev, info, 4);
684
685 /* Get the frame length from the rx status vector,
686 * minus CRC size at the end which is always present
687 */
688 frm_len = sys_get_le16(info) - 4;
689
690 enc28j60_read_packet(dev, vlan_tag, frm_len);
691
692 /* Free buffer memory and decrement rx counter */
693 eth_enc28j60_set_bank(dev, ENC28J60_REG_ERXRDPTL);
694 eth_enc28j60_write_reg(dev, ENC28J60_REG_ERXRDPTL,
695 next_packet & 0xFF);
696 eth_enc28j60_write_reg(dev, ENC28J60_REG_ERXRDPTH,
697 next_packet >> 8);
698 eth_enc28j60_set_eth_reg(dev, ENC28J60_REG_ECON2,
699 ENC28J60_BIT_ECON2_PKTDEC);
700
701 /* Check if there are frames to clean from the buffer */
702 eth_enc28j60_set_bank(dev, ENC28J60_REG_EPKTCNT);
703 eth_enc28j60_read_reg(dev, ENC28J60_REG_EPKTCNT, &counter);
704 } while (counter);
705
706 k_sem_give(&context->tx_rx_sem);
707
708 return 0;
709 }
710
eth_enc28j60_rx_thread(void * p1,void * p2,void * p3)711 static void eth_enc28j60_rx_thread(void *p1, void *p2, void *p3)
712 {
713 ARG_UNUSED(p2);
714 ARG_UNUSED(p3);
715
716 const struct device *dev = p1;
717 struct eth_enc28j60_runtime *context = dev->data;
718 uint16_t vlan_tag = NET_VLAN_TAG_UNSPEC;
719 uint8_t int_stat;
720
721 while (true) {
722 k_sem_take(&context->int_sem, K_FOREVER);
723
724 eth_enc28j60_read_reg(dev, ENC28J60_REG_EIR, &int_stat);
725 if (int_stat & ENC28J60_BIT_EIR_PKTIF) {
726 eth_enc28j60_rx(dev, &vlan_tag);
727 /* Clear rx interruption flag */
728 eth_enc28j60_clear_eth_reg(dev, ENC28J60_REG_EIR,
729 ENC28J60_BIT_EIR_PKTIF
730 | ENC28J60_BIT_EIR_RXERIF);
731 } else if (int_stat & ENC28J60_BIT_EIR_LINKIF) {
732 uint16_t phir;
733 uint16_t phstat2;
734 /* Clear link change interrupt flag by PHIR reg read */
735 eth_enc28j60_read_phy(dev, ENC28J60_PHY_PHIR, &phir);
736 eth_enc28j60_read_phy(dev, ENC28J60_PHY_PHSTAT2, &phstat2);
737 if (phstat2 & ENC28J60_BIT_PHSTAT2_LSTAT) {
738 LOG_INF("%s: Link up", dev->name);
739 net_eth_carrier_on(context->iface);
740 } else {
741 LOG_INF("%s: Link down", dev->name);
742
743 if (context->iface_initialized) {
744 net_eth_carrier_off(context->iface);
745 }
746 }
747 }
748 }
749 }
750
eth_enc28j60_get_capabilities(const struct device * dev)751 static enum ethernet_hw_caps eth_enc28j60_get_capabilities(const struct device *dev)
752 {
753 ARG_UNUSED(dev);
754
755 return ETHERNET_LINK_10BASE_T
756 #if defined(CONFIG_NET_VLAN)
757 | ETHERNET_HW_VLAN
758 #endif
759 ;
760 }
761
eth_enc28j60_iface_init(struct net_if * iface)762 static void eth_enc28j60_iface_init(struct net_if *iface)
763 {
764 const struct device *dev = net_if_get_device(iface);
765 struct eth_enc28j60_runtime *context = dev->data;
766
767 net_if_set_link_addr(iface, context->mac_address,
768 sizeof(context->mac_address),
769 NET_LINK_ETHERNET);
770
771 /* For VLAN, this value is only used to get the correct L2 driver.
772 * The iface pointer in context should contain the main interface
773 * if the VLANs are enabled.
774 */
775 if (context->iface == NULL) {
776 context->iface = iface;
777 }
778
779 ethernet_init(iface);
780
781 net_if_carrier_off(iface);
782 context->iface_initialized = true;
783 }
784
785 static const struct ethernet_api api_funcs = {
786 .iface_api.init = eth_enc28j60_iface_init,
787
788 .get_capabilities = eth_enc28j60_get_capabilities,
789 .send = eth_enc28j60_tx,
790 };
791
eth_enc28j60_init(const struct device * dev)792 static int eth_enc28j60_init(const struct device *dev)
793 {
794 const struct eth_enc28j60_config *config = dev->config;
795 struct eth_enc28j60_runtime *context = dev->data;
796
797 /* SPI config */
798 if (!spi_is_ready_dt(&config->spi)) {
799 LOG_ERR("%s: SPI master port %s not ready", dev->name, config->spi.bus->name);
800 return -EINVAL;
801 }
802
803 /* Initialize GPIO */
804 if (!gpio_is_ready_dt(&config->interrupt)) {
805 LOG_ERR("%s: GPIO port %s not ready", dev->name, config->interrupt.port->name);
806 return -EINVAL;
807 }
808
809 if (gpio_pin_configure_dt(&config->interrupt, GPIO_INPUT)) {
810 LOG_ERR("%s: Unable to configure GPIO pin %u", dev->name, config->interrupt.pin);
811 return -EINVAL;
812 }
813
814 gpio_init_callback(&(context->gpio_cb), eth_enc28j60_gpio_callback,
815 BIT(config->interrupt.pin));
816
817 if (gpio_add_callback(config->interrupt.port, &(context->gpio_cb))) {
818 return -EINVAL;
819 }
820
821 gpio_pin_interrupt_configure_dt(&config->interrupt,
822 GPIO_INT_EDGE_TO_ACTIVE);
823
824 if (eth_enc28j60_soft_reset(dev)) {
825 LOG_ERR("%s: Soft-reset failed", dev->name);
826 return -EIO;
827 }
828
829 /* Errata B7/1 */
830 k_busy_wait(D10D24S);
831
832 /* Assign octets not previously taken from devicetree */
833 context->mac_address[0] = MICROCHIP_OUI_B0;
834 context->mac_address[1] = MICROCHIP_OUI_B1;
835 context->mac_address[2] = MICROCHIP_OUI_B2;
836
837 if (eth_enc28j60_init_buffers(dev)) {
838 return -ETIMEDOUT;
839 }
840 eth_enc28j60_init_mac(dev);
841 eth_enc28j60_init_phy(dev);
842
843 /* Enable interruptions */
844 eth_enc28j60_set_eth_reg(dev, ENC28J60_REG_EIE, ENC28J60_BIT_EIE_INTIE);
845 eth_enc28j60_set_eth_reg(dev, ENC28J60_REG_EIE, ENC28J60_BIT_EIE_PKTIE);
846 eth_enc28j60_set_eth_reg(dev, ENC28J60_REG_EIE, ENC28J60_BIT_EIE_LINKIE);
847 eth_enc28j60_write_phy(dev, ENC28J60_PHY_PHIE, ENC28J60_BIT_PHIE_PGEIE |
848 ENC28J60_BIT_PHIE_PLNKIE);
849
850 /* Enable Reception */
851 eth_enc28j60_set_eth_reg(dev, ENC28J60_REG_ECON1,
852 ENC28J60_BIT_ECON1_RXEN);
853
854 /* Start interruption-poll thread */
855 k_thread_create(&context->thread, context->thread_stack,
856 CONFIG_ETH_ENC28J60_RX_THREAD_STACK_SIZE,
857 eth_enc28j60_rx_thread,
858 (void *)dev, NULL, NULL,
859 K_PRIO_COOP(CONFIG_ETH_ENC28J60_RX_THREAD_PRIO),
860 0, K_NO_WAIT);
861
862 LOG_INF("%s: Initialized", dev->name);
863
864 return 0;
865 }
866
867 #define ENC28J60_DEFINE(inst) \
868 static struct eth_enc28j60_runtime eth_enc28j60_runtime_##inst = { \
869 .mac_address = DT_INST_PROP(inst, local_mac_address), \
870 .tx_rx_sem = \
871 Z_SEM_INITIALIZER((eth_enc28j60_runtime_##inst).tx_rx_sem, 1, UINT_MAX), \
872 .int_sem = Z_SEM_INITIALIZER((eth_enc28j60_runtime_##inst).int_sem, 0, UINT_MAX), \
873 }; \
874 \
875 static const struct eth_enc28j60_config eth_enc28j60_config_##inst = { \
876 .spi = SPI_DT_SPEC_INST_GET(inst, SPI_WORD_SET(8), 0), \
877 .interrupt = GPIO_DT_SPEC_INST_GET(inst, int_gpios), \
878 .full_duplex = DT_INST_PROP(0, full_duplex), \
879 .timeout = CONFIG_ETH_ENC28J60_TIMEOUT, \
880 }; \
881 \
882 ETH_NET_DEVICE_DT_INST_DEFINE(inst, eth_enc28j60_init, NULL, ð_enc28j60_runtime_##inst, \
883 ð_enc28j60_config_##inst, CONFIG_ETH_INIT_PRIORITY, \
884 &api_funcs, NET_ETH_MTU);
885
886 DT_INST_FOREACH_STATUS_OKAY(ENC28J60_DEFINE);
887
