1 /* 2 * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #pragma once 8 9 #include "sdkconfig.h" 10 #include <stdbool.h> 11 #include <stddef.h> 12 #include <stdint.h> 13 #include "esp_err.h" 14 15 #ifdef __cplusplus 16 extern "C" { 17 #endif 18 19 /** 20 * This header file contains declarations of cache manipulation functions 21 * used both in flash_ops.c and flash_mmap.c. 22 * 23 * These functions are considered internal and are not designed to be called from applications. 24 */ 25 26 // Init mutex protecting access to spi_flash_* APIs 27 void spi_flash_init_lock(void); 28 29 // Take mutex protecting access to spi_flash_* APIs 30 void spi_flash_op_lock(void); 31 32 // Release said mutex 33 void spi_flash_op_unlock(void); 34 35 // Suspend the scheduler on both CPUs, disable cache. 36 // Contrary to its name this doesn't do anything with interrupts, yet. 37 // Interrupt disabling capability will be added once we implement 38 // interrupt allocation API. 39 void spi_flash_disable_interrupts_caches_and_other_cpu(void); 40 41 // Enable cache, enable interrupts (to be added in future), resume scheduler 42 void spi_flash_enable_interrupts_caches_and_other_cpu(void); 43 44 // Disables non-IRAM interrupt handlers on current CPU and caches on both CPUs. 45 // This function is implied to be called when other CPU is not running or running code from IRAM. 46 void spi_flash_disable_interrupts_caches_and_other_cpu_no_os(void); 47 48 // Enable cache, enable interrupts on current CPU. 49 // This function is implied to be called when other CPU is not running or running code from IRAM. 50 void spi_flash_enable_interrupts_caches_no_os(void); 51 52 // Mark the pages containing a flash region as having been 53 // erased or written to. This means the flash cache needs 54 // to be evicted before these pages can be flash_mmap()ed again, 55 // as they may contain stale data 56 // 57 // Only call this while holding spi_flash_op_lock() 58 // Returns true if cache was flushed, false otherwise 59 bool spi_flash_check_and_flush_cache(size_t start_addr, size_t length); 60 61 //config cache mode 62 #if !CONFIG_IDF_TARGET_ESP32 63 //config instrcutin cache size and cache block size by menuconfig 64 void esp_config_instruction_cache_mode(void); 65 //config data cache size and cache block size by menuconfig 66 void esp_config_data_cache_mode(void); 67 //enable cache wrap mode for instruction cache and data cache 68 esp_err_t esp_enable_cache_wrap(bool icache_wrap_enable, bool dcache_wrap_enable); 69 #endif 70 71 /** @brief Check at runtime if flash cache is enabled on both CPUs 72 * 73 * @return true if both CPUs have flash cache enabled, false otherwise. 74 */ 75 bool spi_flash_cache_enabled(void); 76 77 /** 78 * @brief Re-enable cache for the core defined as cpuid parameter. 79 * 80 * @param cpuid the core number to enable instruction cache for 81 */ 82 void spi_flash_enable_cache(uint32_t cpuid); 83 84 #ifdef __cplusplus 85 } 86 #endif 87
