1 /*
2  * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
3  *
4  * SPDX-License-Identifier: Apache-2.0
5  */
6 #pragma once
7 
8 #include <stdlib.h>
9 #include <stdint.h>
10 #include "esp_err.h"
11 #include "esp_bit_defs.h"
12 
13 #ifdef __cplusplus
14 extern "C" {
15 #endif
16 
17 /**
18  * Cache msync flags
19  */
20 /**
21  * @brief Do an invalidation with the values that just written
22  */
23 #define ESP_CACHE_MSYNC_FLAG_INVALIDATE    BIT(0)
24 /**
25  * @brief Allow writeback a block that are not aligned to the data cache line size
26  */
27 #define ESP_CACHE_MSYNC_FLAG_UNALIGNED     BIT(1)
28 
29 
30 /**
31  * @brief Memory sync between Cache and external memory
32  *
33  * - For cache writeback supported chips (you can refer to SOC_CACHE_WRITEBACK_SUPPORTED in soc_caps.h)
34  *   - this API will do a writeback to synchronise between cache and the PSRAM
35  *   - with ESP_CACHE_MSYNC_FLAG_INVALIDATE, this API will also invalidate the values that just written
36  *   - note: although ESP32 is with PSRAM, but cache writeback isn't supported, so this API will do nothing on ESP32
37  * - For other chips, this API will do nothing. The out-of-sync should be already dealt by the SDK
38  *
39  * This API is cache-safe and thread-safe
40  *
41  * @note You should not call this during any Flash operations (e.g. esp_flash APIs, nvs and some other APIs that are based on esp_flash APIs)
42  * @note If XIP_From_PSRAM is enabled (by enabling both CONFIG_SPIRAM_FETCH_INSTRUCTIONS and CONFIG_SPIRAM_RODATA), you can call this API during Flash operations
43  *
44  * @param[in] addr   Starting address to do the msync
45  * @param[in] size   Size to do the msync
46  * @param[in] flags  Flags, see `ESP_CACHE_MSYNC_FLAG_x`
47  *
48  * @return
49  *        - ESP_OK:
50  *                  - Successful msync
51  *                  - If this chip doesn't support cache writeback, if the input addr is a cache supported one, this API will return ESP_OK
52  *        - ESP_ERR_INVALID_ARG:   Invalid argument, not cache supported addr, see printed logs
53  */
54 esp_err_t esp_cache_msync(void *addr, size_t size, int flags);
55 
56 #ifdef __cplusplus
57 }
58 #endif
59