1 /* 2 * copyright (c) Espressif System 2019 3 * 4 */ 5 6 #ifndef _ROM_OPI_FLASH_H_ 7 #define _ROM_OPI_FLASH_H_ 8 #include <stdio.h> 9 #include <string.h> 10 #include <stdint.h> 11 #include <stdbool.h> 12 #include "spi_flash.h" 13 14 #ifdef __cplusplus 15 extern "C" { 16 #endif 17 18 19 20 typedef struct { 21 uint8_t mode; 22 uint8_t cmd_bit_len; 23 uint16_t cmd; 24 uint32_t addr; 25 uint8_t addr_bit_len; 26 uint8_t dummy_bit_len; 27 uint8_t data_bit_len; 28 uint8_t cs_sel: 4; 29 uint8_t is_pe: 4; 30 } esp_rom_opiflash_cmd_t; 31 32 typedef struct { 33 uint8_t addr_bit_len; 34 uint8_t dummy_bit_len; 35 uint16_t cmd; 36 uint8_t cmd_bit_len; 37 uint8_t var_dummy_en; 38 } esp_rom_opiflash_spi0rd_t; 39 40 typedef struct { 41 esp_rom_opiflash_cmd_t rdid; 42 esp_rom_opiflash_cmd_t rdsr; 43 esp_rom_opiflash_cmd_t wren; 44 esp_rom_opiflash_cmd_t se; 45 esp_rom_opiflash_cmd_t be64k; 46 esp_rom_opiflash_cmd_t read; 47 esp_rom_opiflash_cmd_t pp; 48 esp_rom_opiflash_spi0rd_t cache_rd_cmd; 49 } esp_rom_opiflash_def_t; 50 51 typedef struct { 52 uint16_t cmd; /*!< Command value */ 53 uint16_t cmdBitLen; /*!< Command byte length*/ 54 uint32_t *addr; /*!< Point to address value*/ 55 uint32_t addrBitLen; /*!< Address byte length*/ 56 uint32_t *txData; /*!< Point to send data buffer*/ 57 uint32_t txDataBitLen; /*!< Send data byte length.*/ 58 uint32_t *rxData; /*!< Point to recevie data buffer*/ 59 uint32_t rxDataBitLen; /*!< Recevie Data byte length.*/ 60 uint32_t dummyBitLen; 61 } esp_rom_spi_cmd_t; 62 63 #define ESP_ROM_OPIFLASH_MUX_TAKE() 64 #define ESP_ROM_OPIFLASH_MUX_GIVE() 65 #define ESP_ROM_OPIFLASH_SEL_CS0 (BIT(0)) 66 #define ESP_ROM_OPIFLASH_SEL_CS1 (BIT(1)) 67 68 // Definition of MX25UM25645G Octa Flash 69 // SPI status register 70 #define ESP_ROM_SPIFLASH_BUSY_FLAG BIT0 71 #define ESP_ROM_SPIFLASH_WRENABLE_FLAG BIT1 72 #define ESP_ROM_SPIFLASH_BP0 BIT2 73 #define ESP_ROM_SPIFLASH_BP1 BIT3 74 #define ESP_ROM_SPIFLASH_BP2 BIT4 75 #define ESP_ROM_SPIFLASH_WR_PROTECT (ESP_ROM_SPIFLASH_BP0|ESP_ROM_SPIFLASH_BP1|ESP_ROM_SPIFLASH_BP2) 76 #define ESP_ROM_SPIFLASH_QE BIT9 77 78 #define FLASH_OP_MODE_RDCMD_DOUT 0x3B 79 #define ESP_ROM_FLASH_SECTOR_SIZE 0x1000 80 #define ESP_ROM_FLASH_BLOCK_SIZE_64K 0x10000 81 #define ESP_ROM_FLASH_PAGE_SIZE 256 82 83 // FLASH commands 84 #define ROM_FLASH_CMD_RDID 0x9F 85 #define ROM_FLASH_CMD_WRSR 0x01 86 #define ROM_FLASH_CMD_WRSR2 0x31 /* Not all SPI flash uses this command */ 87 #define ROM_FLASH_CMD_WREN 0x06 88 #define ROM_FLASH_CMD_WRDI 0x04 89 #define ROM_FLASH_CMD_RDSR 0x05 90 #define ROM_FLASH_CMD_RDSR2 0x35 /* Not all SPI flash uses this command */ 91 #define ROM_FLASH_CMD_ERASE_SEC 0x20 92 #define ROM_FLASH_CMD_ERASE_BLK_32K 0x52 93 #define ROM_FLASH_CMD_ERASE_BLK_64K 0xD8 94 #define ROM_FLASH_CMD_OTPEN 0x3A /* Enable OTP mode, not all SPI flash uses this command */ 95 #define ROM_FLASH_CMD_RSTEN 0x66 96 #define ROM_FLASH_CMD_RST 0x99 97 98 #define ROM_FLASH_CMD_SE4B 0x21 99 #define ROM_FLASH_CMD_SE4B_OCT 0xDE21 100 #define ROM_FLASH_CMD_BE4B 0xDC 101 #define ROM_FLASH_CMD_BE4B_OCT 0x23DC 102 #define ROM_FLASH_CMD_RSTEN_OCT 0x9966 103 #define ROM_FLASH_CMD_RST_OCT 0x6699 104 105 #define ROM_FLASH_CMD_FSTRD4B_STR 0x13EC 106 #define ROM_FLASH_CMD_FSTRD4B_DTR 0x11EE 107 #define ROM_FLASH_CMD_FSTRD4B 0x0C 108 #define ROM_FLASH_CMD_PP4B 0x12 109 #define ROM_FLASH_CMD_PP4B_OCT 0xED12 110 111 #define ROM_FLASH_CMD_RDID_OCT 0x609F 112 #define ROM_FLASH_CMD_WREN_OCT 0xF906 113 #define ROM_FLASH_CMD_RDSR_OCT 0xFA05 114 #define ROM_FLASH_CMD_RDCR2 0x71 115 #define ROM_FLASH_CMD_RDCR2_OCT 0x8E71 116 #define ROM_FLASH_CMD_WRCR2 0x72 117 #define ROM_FLASH_CMD_WRCR2_OCT 0x8D72 118 119 // Definitions for GigaDevice GD25LX256E Flash 120 #define ROM_FLASH_CMD_RDFSR_GD 0x70 121 #define ROM_FLASH_CMD_RD_GD 0x03 122 #define ROM_FLASH_CMD_RD4B_GD 0x13 123 #define ROM_FLASH_CMD_FSTRD_GD 0x0B 124 #define ROM_FLASH_CMD_FSTRD4B_GD 0x0C 125 #define ROM_FLASH_CMD_FSTRD_OOUT_GD 0x8B 126 #define ROM_FLASH_CMD_FSTRD4B_OOUT_GD 0x7C 127 #define ROM_FLASH_CMD_FSTRD_OIOSTR_GD 0xCB 128 #define ROM_FLASH_CMD_FSTRD4B_OIOSTR_GD 0xCC 129 #define ROM_FLASH_CMD_FSTRD4B_OIODTR_GD 0xFD 130 131 #define ROM_FLASH_CMD_PP_GD 0x02 132 #define ROM_FLASH_CMD_PP4B_GD 0x12 133 #define ROM_FLASH_CMD_PP_OOUT_GD 0x82 134 #define ROM_FLASH_CMD_PP4B_OOUT_GD 0x84 135 #define ROM_FLASH_CMD_PP_OIO_GD 0xC2 136 #define ROM_FLASH_CMD_PP4B_OIOSTR_GD 0x8E 137 138 #define ROM_FLASH_CMD_SE_GD 0x20 139 #define ROM_FLASH_CMD_SE4B_GD 0x21 140 #define ROM_FLASH_CMD_BE32K_GD 0x52 141 #define ROM_FLASH_CMD_BE32K4B_GD 0x5C 142 #define ROM_FLASH_CMD_BE64K_GD 0xD8 143 #define ROM_FLASH_CMD_BE64K4B_GD 0xDC 144 145 #define ROM_FLASH_CMD_EN4B_GD 0xB7 146 #define ROM_FLASH_CMD_DIS4B_GD 0xE9 147 148 extern const esp_rom_opiflash_def_t *rom_opiflash_cmd_def; 149 150 /** 151 * @brief init legacy driver for Octal Flash 152 */ 153 void esp_rom_opiflash_legacy_driver_init(const esp_rom_opiflash_def_t *flash_cmd_def); 154 155 // spi user mode command config 156 /** 157 * @brief Config the spi user command 158 * @param spi_num spi port 159 * @param pcmd pointer to accept the spi command struct 160 */ 161 void esp_rom_spi_cmd_config(int spi_num, esp_rom_spi_cmd_t* pcmd); 162 163 /** 164 * @brief Start a spi user command sequence 165 * @param spi_num spi port 166 * @param rx_buf buffer pointer to receive data 167 * @param rx_len receive data length in byte 168 * @param cs_en_mask decide which cs to use, 0 for cs0, 1 for cs1 169 * @param is_write_erase to indicate whether this is a write or erase operation, since the CPU would check permission 170 */ 171 void esp_rom_spi_cmd_start(int spi_num, uint8_t* rx_buf, uint16_t rx_len, uint8_t cs_en_mask, bool is_write_erase); 172 173 /** 174 * @brief Config opi flash pads according to efuse settings. 175 */ 176 void esp_rom_opiflash_pin_config(void); 177 178 // set SPI read/write mode 179 /** 180 * @brief Set SPI operation mode 181 * @param spi_num spi port 182 * @param mode Flash Read Mode 183 */ 184 void esp_rom_spi_set_op_mode(int spi_num, esp_rom_spiflash_read_mode_t mode); 185 186 /** 187 * @brief Set data swap mode in DTR(DDR) mode 188 * @param spi_num spi port 189 * @param wr_swap to decide whether to swap fifo data in dtr write operation 190 * @param rd_swap to decide whether to swap fifo data in dtr read operation 191 */ 192 void esp_rom_spi_set_dtr_swap_mode(int spi, bool wr_swap, bool rd_swap); 193 194 195 /** 196 * @brief to send reset command in spi/opi-str/opi-dtr mode(for MX25UM25645G) 197 * @param spi_num spi port 198 */ 199 void esp_rom_opiflash_mode_reset(int spi_num); 200 201 /** 202 * @brief To execute a flash operation command 203 * @param spi_num spi port 204 * @param mode Flash Read Mode 205 * @param cmd data to send in command field 206 * @param cmd_bit_len bit length of command field 207 * @param addr data to send in address field 208 * @param addr_bit_len bit length of address field 209 * @param dummy_bits bit length of dummy field 210 * @param mosi_data data buffer to be sent in mosi field 211 * @param mosi_bit_len bit length of data buffer to be sent in mosi field 212 * @param miso_data data buffer to accept data in miso field 213 * @param miso_bit_len bit length of data buffer to accept data in miso field 214 * @param cs_mark decide which cs pin to use. 0: cs0, 1: cs1 215 * @param is_write_erase_operation to indicate whether this a write or erase flash operation 216 */ 217 void esp_rom_opiflash_exec_cmd(int spi_num, esp_rom_spiflash_read_mode_t mode, 218 uint32_t cmd, int cmd_bit_len, 219 uint32_t addr, int addr_bit_len, 220 int dummy_bits, 221 uint8_t* mosi_data, int mosi_bit_len, 222 uint8_t* miso_data, int miso_bit_len, 223 uint32_t cs_mask, 224 bool is_write_erase_operation); 225 226 /** 227 * @brief send reset command to opi flash 228 * @param spi_num spi port 229 * @param mode Flash Operation Mode 230 */ 231 void esp_rom_opiflash_soft_reset(int spi_num, esp_rom_spiflash_read_mode_t mode); 232 233 234 /** 235 * @brief to read opi flash ID 236 * @note command format would be defined in initialization 237 * @param[out] out_id buffer to accept id 238 * @return flash operation result 239 */ 240 esp_rom_spiflash_result_t esp_rom_opiflash_read_id(uint8_t *out_id); 241 242 /** 243 * @brief to read opi flash status register 244 * @note command format would be defined in initialization 245 * @return opi flash status value 246 */ 247 uint8_t esp_rom_opiflash_rdsr(void); 248 249 /** 250 * @brief wait opi flash status register to be idle 251 * @note command format would be defined in initialization 252 * @return flash operation result 253 */ 254 esp_rom_spiflash_result_t esp_rom_opiflash_wait_idle(void); 255 256 /** 257 * @brief to erase flash sector 258 * @note command format would be defined in initialization 259 * @param sector_num the sector to be erased 260 * @return flash operation result 261 */ 262 esp_rom_spiflash_result_t esp_rom_opiflash_erase_sector(uint32_t sector_num); 263 264 /** 265 * @brief to erase flash block 266 * @note command format would be defined in initialization 267 * @param block_num the block to be erased 268 * @return flash operation result 269 */ 270 esp_rom_spiflash_result_t esp_rom_opiflash_erase_block_64k(uint32_t block_num); 271 272 /** 273 * @brief to erase a flash area define by start address and length 274 * @note command format would be defined in initialization 275 * @param start_addr the start address to be erased 276 * @param area_len the erea length to be erased 277 * @return flash operation result 278 */ 279 esp_rom_spiflash_result_t esp_rom_opiflash_erase_area(uint32_t start_addr, uint32_t area_len); 280 281 /** 282 * @brief to read data from opi flash 283 * @note command format would be defined in initialization 284 * @param flash_addr flash address to read data from 285 * @param data_addr data buffer to accept the data 286 * @param len data length to be read 287 * @return flash operation result 288 */ 289 esp_rom_spiflash_result_t esp_rom_opiflash_read(uint32_t flash_addr, void *data_addr, int len); 290 291 /** 292 * @brief to write data to opi flash 293 * @note command format would be defined in initialization 294 * @param flash_addr flash address to write data to 295 * @param data_addr data buffer to write to flash 296 * @param len data length to write 297 * @return flash operation result 298 */ 299 esp_rom_spiflash_result_t esp_rom_opiflash_write(uint32_t flash_addr, const uint32_t *data_addr, int len); 300 301 /** 302 * @brief send WREN command 303 * @note command format would be defined in initialization 304 * @param arg not used, set to NULL 305 * @return flash operation result 306 */ 307 esp_rom_spiflash_result_t esp_rom_opiflash_wren(void* arg); 308 309 /** 310 * @brief to configure SPI0 read flash command format for cache 311 * @note command format would be defined in initialization 312 * 313 */ 314 void esp_rom_opiflash_cache_mode_config(esp_rom_spiflash_read_mode_t mode, const esp_rom_opiflash_spi0rd_t *cache); 315 316 esp_rom_spiflash_result_t esp_rom_opiflash_read_raw(uint32_t flash_addr, uint8_t* buf, int len); 317 318 319 #ifdef __cplusplus 320 } 321 #endif 322 323 #endif 324