1/*
2 * Copyright (c) 2021 Espressif Systems (Shanghai) Co., Ltd.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6#include <mem.h>
7#include <xtensa/xtensa.dtsi>
8#include <zephyr/dt-bindings/adc/adc.h>
9#include <zephyr/dt-bindings/gpio/gpio.h>
10#include <zephyr/dt-bindings/i2c/i2c.h>
11#include <zephyr/dt-bindings/clock/esp32s2_clock.h>
12#include <zephyr/dt-bindings/interrupt-controller/esp32s2-xtensa-intmux.h>
13#include <dt-bindings/pinctrl/esp32-pinctrl.h>
14
15/ {
16	#address-cells = <1>;
17	#size-cells = <1>;
18
19	aliases {
20		die-temp0 = &coretemp;
21	};
22
23	chosen {
24		zephyr,canbus = &twai;
25		zephyr,entropy = &trng0;
26		zephyr,flash-controller = &flash;
27	};
28
29	cpus {
30		#address-cells = <1>;
31		#size-cells = <0>;
32
33		cpu0: cpu@0 {
34			device_type = "cpu";
35			compatible = "cdns,tensilica-xtensa-lx7";
36			reg = <0>;
37			cpu-power-states = <&light_sleep &deep_sleep>;
38		};
39
40		power-states {
41			light_sleep: light_sleep {
42				compatible = "zephyr,power-state";
43				power-state-name = "standby";
44				min-residency-us = <200>;
45				exit-latency-us = <60>;
46			};
47
48			deep_sleep: deep_sleep {
49				compatible = "zephyr,power-state";
50				power-state-name = "soft-off";
51				min-residency-us = <2000>;
52				exit-latency-us = <212>;
53			};
54		};
55	};
56
57	wifi: wifi {
58		compatible = "espressif,esp32-wifi";
59		status = "disabled";
60	};
61
62	pinctrl: pin-controller {
63		compatible = "espressif,esp32-pinctrl";
64		status = "okay";
65	};
66
67	soc {
68		#address-cells = <1>;
69		#size-cells = <1>;
70		compatible = "simple-bus";
71		ranges;
72
73		sram0: memory@3ffb0000 {
74			compatible = "mmio-sram";
75			reg = <0x3ffb0000 0x50000>;
76		};
77
78		intc: interrupt-controller@3f4c2000 {
79			#interrupt-cells = <1>;
80			compatible = "espressif,esp32-intc";
81			interrupt-controller;
82			reg = <0x3f4c2000 0x114>;
83			status = "okay";
84		};
85
86		rtc: rtc@3f408000 {
87			compatible = "espressif,esp32-rtc";
88			reg = <0x3f408000 0x0D8>;
89			xtal-freq = <ESP32_CLK_XTAL_40M>;
90			#clock-cells = <1>;
91			status = "okay";
92
93			rtc_timer: rtc_timer {
94				compatible = "espressif,esp32-rtc-timer";
95				slow-clk-freq = <ESP32_RTC_SLOW_CLK_FREQ_90K>;
96				interrupts = <RTC_CORE_INTR_SOURCE>;
97				interrupt-parent = <&intc>;
98				status = "okay";
99			};
100		};
101
102		flash: flash-controller@3f402000 {
103			compatible = "espressif,esp32-flash-controller";
104			reg = <0x3f402000 0x1000>;
105
106			#address-cells = <1>;
107			#size-cells = <1>;
108
109			flash0: flash@0 {
110				compatible = "soc-nv-flash";
111				erase-block-size = <4096>;
112				write-block-size = <4>;
113				/* Flash size is specified in SOC/SIP dtsi */
114			};
115		};
116
117		psram0: psram@3f500000 {
118			device_type = "memory";
119			compatible = "mmio-sram";
120			/* PSRAM size is specified in SOC/SIP dtsi */
121			reg = <0x3f500000 DT_SIZE_M(2)>;
122			status = "disabled";
123		};
124
125		uart0: uart@3f400000 {
126			compatible = "espressif,esp32-uart";
127			reg = <0x3f400000 0x400>;
128			status = "disabled";
129			interrupts = <UART0_INTR_SOURCE>;
130			interrupt-parent = <&intc>;
131			clocks = <&rtc ESP32_UART0_MODULE>;
132		};
133
134		uart1: uart@3f410000 {
135			compatible = "espressif,esp32-uart";
136			reg = <0x3f410000 0x400>;
137			status = "disabled";
138			interrupts = <UART1_INTR_SOURCE>;
139			interrupt-parent = <&intc>;
140			clocks = <&rtc ESP32_UART1_MODULE>;
141			current-speed = <115200>;
142		};
143
144		pcnt: pcnt@3f417000 {
145			compatible = "espressif,esp32-pcnt";
146			reg = <0x3f417000 0x1000>;
147			interrupts = <PCNT_INTR_SOURCE>;
148			interrupt-parent = <&intc>;
149			clocks = <&rtc ESP32_PCNT_MODULE>;
150			status = "disabled";
151		};
152
153		ledc0: ledc@3f419000 {
154			compatible = "espressif,esp32-ledc";
155			pwm-controller;
156			#pwm-cells = <3>;
157			reg = <0x3f419000 0x1000>;
158			clocks = <&rtc ESP32_LEDC_MODULE>;
159			status = "disabled";
160		};
161
162		gpio0: gpio@3f404000 {
163			compatible = "espressif,esp32-gpio";
164			gpio-controller;
165			#gpio-cells = <2>;
166			reg = <0x3f404000 0x800>;
167			interrupts = <GPIO_INTR_SOURCE>;
168			interrupt-parent = <&intc>;
169			/* Maximum available pins (per port)
170			 * Actual occupied pins are specified
171			 * on part number dtsi level, using
172			 * the `gpio-reserved-ranges` property.
173			 */
174			ngpios = <32>;   /* 0..31 */
175		};
176
177		gpio1: gpio@3f404800 {
178			compatible = "espressif,esp32-gpio";
179			gpio-controller;
180			#gpio-cells = <2>;
181			reg = <0x3f404800 0x800>;
182			interrupts = <GPIO_INTR_SOURCE>;
183			interrupt-parent = <&intc>;
184			ngpios = <22>;   /* 32..53 */
185		};
186
187		i2c0: i2c@3f413000 {
188			compatible = "espressif,esp32-i2c";
189			#address-cells = <1>;
190			#size-cells = <0>;
191			reg = <0x3f413000 0x1000>;
192			interrupts = <I2C_EXT0_INTR_SOURCE>;
193			interrupt-parent = <&intc>;
194			clocks = <&rtc ESP32_I2C0_MODULE>;
195			status = "disabled";
196		};
197
198		i2c1: i2c@3f427000 {
199			compatible = "espressif,esp32-i2c";
200			#address-cells = <1>;
201			#size-cells = <0>;
202			reg = <0x3f427000 0x1000>;
203			interrupts = <I2C_EXT1_INTR_SOURCE>;
204			interrupt-parent = <&intc>;
205			clocks = <&rtc ESP32_I2C1_MODULE>;
206			status = "disabled";
207		};
208
209		timer0: counter@3f41f000 {
210			compatible = "espressif,esp32-timer";
211			reg = <0x3f41f000 DT_SIZE_K(4)>;
212			group = <0>;
213			index = <0>;
214			interrupts = <TG0_T0_LEVEL_INTR_SOURCE>;
215			interrupt-parent = <&intc>;
216			status = "disabled";
217		};
218
219		timer1: counter@3f41f024 {
220			compatible = "espressif,esp32-timer";
221			reg = <0x3f41f024 DT_SIZE_K(4)>;
222			group = <0>;
223			index = <1>;
224			interrupts = <TG0_T1_LEVEL_INTR_SOURCE>;
225			interrupt-parent = <&intc>;
226			status = "disabled";
227		};
228
229		timer2: counter@3f420000 {
230			compatible = "espressif,esp32-timer";
231			reg = <0x3f420000 DT_SIZE_K(4)>;
232			group = <1>;
233			index = <0>;
234			interrupts = <TG1_T0_LEVEL_INTR_SOURCE>;
235			interrupt-parent = <&intc>;
236			status = "disabled";
237		};
238
239		timer3: counter@3f420024 {
240			compatible = "espressif,esp32-timer";
241			reg = <0x3f420024 DT_SIZE_K(4)>;
242			group = <1>;
243			index = <1>;
244			interrupts = <TG1_T1_LEVEL_INTR_SOURCE>;
245			interrupt-parent = <&intc>;
246		};
247
248		trng0: trng@3f435110 {
249			compatible = "espressif,esp32-trng";
250			reg = <0x3f435110 0x4>;
251			status = "disabled";
252		};
253
254		spi2: spi@3f424000 {
255			compatible = "espressif,esp32-spi";
256			reg = <0x3f424000 DT_SIZE_K(4)>;
257			interrupts = <SPI2_INTR_SOURCE>;
258			interrupt-parent = <&intc>;
259			clocks = <&rtc ESP32_FSPI_MODULE>;
260			dma-clk = <ESP32_SPI2_DMA_MODULE>;
261			dma-host = <0>;
262			status = "disabled";
263		};
264
265		spi3: spi@3f425000 {
266			compatible = "espressif,esp32-spi";
267			reg = <0x3f425000 DT_SIZE_K(4)>;
268			interrupts = <SPI3_INTR_SOURCE>;
269			interrupt-parent = <&intc>;
270			clocks = <&rtc ESP32_HSPI_MODULE>;
271			dma-clk = <ESP32_SPI3_DMA_MODULE>;
272			dma-host = <1>;
273			status = "disabled";
274		};
275
276		wdt0: watchdog@3f41f048 {
277			compatible = "espressif,esp32-watchdog";
278			reg = <0x3f41f048 0x20>;
279			interrupts = <TG0_WDT_LEVEL_INTR_SOURCE>;
280			interrupt-parent = <&intc>;
281			clocks = <&rtc ESP32_TIMG0_MODULE>;
282			status = "disabled";
283		};
284
285		wdt1: watchdog@3f42f048 {
286			compatible = "espressif,esp32-watchdog";
287			reg = <0x3f42f048 0x20>;
288			interrupts = <TG1_WDT_LEVEL_INTR_SOURCE>;
289			interrupt-parent = <&intc>;
290			clocks = <&rtc ESP32_TIMG1_MODULE>;
291			status = "disabled";
292		};
293
294		dac: dac@3f408800 {
295			compatible = "espressif,esp32-dac";
296			reg = <0x3f408800 0x100>;
297			interrupts = <RTC_CORE_INTR_SOURCE>;
298			interrupt-parent = <&intc>;
299			clocks = <&rtc ESP32_PERIPH_SARADC_MODULE>;
300			#io-channel-cells = <1>;
301		};
302
303		coretemp: coretemp@3f408800 {
304			compatible = "espressif,esp32-temp";
305			friendly-name = "coretemp";
306			reg = <0x3f408800 0x4>;
307			status = "disabled";
308		};
309
310		adc0: adc@3f440018 {
311			compatible = "espressif,esp32-adc";
312			reg = <0x3f440018 100>;
313			unit = <1>;
314			channel-count = <10>;
315			#io-channel-cells = <1>;
316			status = "disabled";
317		};
318
319		adc1: adc@3f440028 {
320			compatible = "espressif,esp32-adc";
321			reg = <0x3f440028 100>;
322			unit = <2>;
323			channel-count = <10>;
324			#io-channel-cells = <1>;
325			status = "disabled";
326		};
327
328		twai: can@3f42b000 {
329			compatible = "espressif,esp32-twai";
330			reg = <0x3f42b000 DT_SIZE_K(4)>;
331			interrupts = <TWAI_INTR_SOURCE>;
332			interrupt-parent = <&intc>;
333			clocks = <&rtc ESP32_TWAI_MODULE>;
334			sample-point = <875>;
335			status = "disabled";
336		};
337	};
338
339};
340