1 /*
2  * copyright (c) Espressif System 2019
3  *
4  */
5 
6 #ifndef _ROM_OPI_FLASH_H_
7 #define _ROM_OPI_FLASH_H_
8 #include <stdio.h>
9 #include <string.h>
10 #include <stdint.h>
11 #include "spi_flash.h"
12 
13 #ifdef __cplusplus
14 extern "C" {
15 #endif
16 
17 typedef struct {
18     uint16_t cmd;                /*!< Command value */
19     uint16_t cmdBitLen;          /*!< Command byte length*/
20     uint32_t *addr;              /*!< Point to address value*/
21     uint32_t addrBitLen;         /*!< Address byte length*/
22     uint32_t *txData;            /*!< Point to send data buffer*/
23     uint32_t txDataBitLen;       /*!< Send data byte length.*/
24     uint32_t *rxData;            /*!< Point to recevie data buffer*/
25     uint32_t rxDataBitLen;       /*!< Recevie Data byte length.*/
26     uint32_t dummyBitLen;
27 } esp_rom_spi_cmd_t;
28 
29 #define ESP_ROM_OPIFLASH_MUX_TAKE()
30 #define ESP_ROM_OPIFLASH_MUX_GIVE()
31 #define ESP_ROM_OPIFLASH_SEL_CS0     (BIT(0))
32 #define ESP_ROM_OPIFLASH_SEL_CS1     (BIT(1))
33 
34 // Definition of MX25UM25645G Octa Flash
35 // SPI status register
36 #define ESP_ROM_SPIFLASH_BUSY_FLAG     BIT0
37 #define ESP_ROM_SPIFLASH_WRENABLE_FLAG BIT1
38 #define ESP_ROM_SPIFLASH_BP0           BIT2
39 #define ESP_ROM_SPIFLASH_BP1           BIT3
40 #define ESP_ROM_SPIFLASH_BP2           BIT4
41 #define ESP_ROM_SPIFLASH_WR_PROTECT    (ESP_ROM_SPIFLASH_BP0|ESP_ROM_SPIFLASH_BP1|ESP_ROM_SPIFLASH_BP2)
42 #define ESP_ROM_SPIFLASH_QE            BIT9
43 
44 #define FLASH_OP_MODE_RDCMD_DOUT       0x3B
45 #define ESP_ROM_FLASH_SECTOR_SIZE      0x1000
46 #define ESP_ROM_FLASH_BLOCK_SIZE_64K   0x10000
47 #define ESP_ROM_FLASH_PAGE_SIZE        256
48 
49 // FLASH commands
50 #define ROM_FLASH_CMD_RDID             0x9F
51 #define ROM_FLASH_CMD_WRSR             0x01
52 #define ROM_FLASH_CMD_WRSR2            0x31 /* Not all SPI flash uses this command */
53 #define ROM_FLASH_CMD_WREN             0x06
54 #define ROM_FLASH_CMD_WRDI             0x04
55 #define ROM_FLASH_CMD_RDSR             0x05
56 #define ROM_FLASH_CMD_RDSR2            0x35 /* Not all SPI flash uses this command */
57 #define ROM_FLASH_CMD_ERASE_SEC        0x20
58 #define ROM_FLASH_CMD_ERASE_BLK_32K    0x52
59 #define ROM_FLASH_CMD_ERASE_BLK_64K    0xD8
60 #define ROM_FLASH_CMD_OTPEN            0x3A /* Enable OTP mode, not all SPI flash uses this command */
61 #define ROM_FLASH_CMD_RSTEN            0x66
62 #define ROM_FLASH_CMD_RST              0x99
63 
64 #define ROM_FLASH_CMD_SE4B             0x21
65 #define ROM_FLASH_CMD_SE4B_OCT         0xDE21
66 #define ROM_FLASH_CMD_BE4B             0xDC
67 #define ROM_FLASH_CMD_BE4B_OCT         0x23DC
68 #define ROM_FLASH_CMD_RSTEN_OCT        0x9966
69 #define ROM_FLASH_CMD_RST_OCT          0x6699
70 
71 #define ROM_FLASH_CMD_FSTRD4B_STR      0x13EC
72 #define ROM_FLASH_CMD_FSTRD4B_DTR      0x11EE
73 #define ROM_FLASH_CMD_FSTRD4B          0x0C
74 #define ROM_FLASH_CMD_PP4B             0x12
75 #define ROM_FLASH_CMD_PP4B_OCT         0xED12
76 
77 #define ROM_FLASH_CMD_RDID_OCT         0x609F
78 #define ROM_FLASH_CMD_WREN_OCT         0xF906
79 #define ROM_FLASH_CMD_RDSR_OCT         0xFA05
80 #define ROM_FLASH_CMD_RDCR2            0x71
81 #define ROM_FLASH_CMD_RDCR2_OCT        0x8E71
82 #define ROM_FLASH_CMD_WRCR2            0x72
83 #define ROM_FLASH_CMD_WRCR2_OCT        0x8D72
84 
85 // Definitions for GigaDevice GD25LX256E Flash
86 #define ROM_FLASH_CMD_RDFSR_GD            0x70
87 #define ROM_FLASH_CMD_RD_GD               0x03
88 #define ROM_FLASH_CMD_RD4B_GD             0x13
89 #define ROM_FLASH_CMD_FSTRD_GD            0x0B
90 #define ROM_FLASH_CMD_FSTRD4B_GD          0x0C
91 #define ROM_FLASH_CMD_FSTRD_OOUT_GD       0x8B
92 #define ROM_FLASH_CMD_FSTRD4B_OOUT_GD     0x7C
93 #define ROM_FLASH_CMD_FSTRD_OIOSTR_GD     0xCB
94 #define ROM_FLASH_CMD_FSTRD4B_OIOSTR_GD   0xCC
95 #define ROM_FLASH_CMD_FSTRD4B_OIODTR_GD   0xFD
96 
97 #define ROM_FLASH_CMD_PP_GD               0x02
98 #define ROM_FLASH_CMD_PP4B_GD             0x12
99 #define ROM_FLASH_CMD_PP_OOUT_GD          0x82
100 #define ROM_FLASH_CMD_PP4B_OOUT_GD        0x84
101 #define ROM_FLASH_CMD_PP_OIO_GD           0xC2
102 #define ROM_FLASH_CMD_PP4B_OIOSTR_GD      0x8E
103 
104 #define ROM_FLASH_CMD_SE_GD               0x20
105 #define ROM_FLASH_CMD_SE4B_GD             0x21
106 #define ROM_FLASH_CMD_BE32K_GD            0x52
107 #define ROM_FLASH_CMD_BE32K4B_GD          0x5C
108 #define ROM_FLASH_CMD_BE64K_GD            0xD8
109 #define ROM_FLASH_CMD_BE64K4B_GD          0xDC
110 
111 #define ROM_FLASH_CMD_EN4B_GD             0xB7
112 #define ROM_FLASH_CMD_DIS4B_GD            0xE9
113 
114 // spi user mode command config
115 
116 /**
117  * @brief Config the spi user command
118  * @param spi_num spi port
119  * @param pcmd pointer to accept the spi command struct
120  */
121 void esp_rom_spi_cmd_config(int spi_num, esp_rom_spi_cmd_t* pcmd);
122 
123 /**
124  * @brief Start a spi user command sequence
125  * @param spi_num spi port
126  * @param rx_buf buffer pointer to receive data
127  * @param rx_len receive data length in byte
128  * @param cs_en_mask decide which cs to use, 0 for cs0, 1 for cs1
129  * @param is_write_erase to indicate whether this is a write or erase operation, since the CPU would check permission
130  */
131 void esp_rom_spi_cmd_start(int spi_num, uint8_t* rx_buf, uint16_t rx_len, uint8_t cs_en_mask, bool is_write_erase);
132 
133 /**
134  * @brief Config opi flash pads according to efuse settings.
135  */
136 void esp_rom_opiflash_pin_config(void);
137 
138 // set SPI read/write mode
139 /**
140  * @brief Set SPI operation mode
141  * @param spi_num spi port
142  * @param mode Flash Read Mode
143  */
144 void esp_rom_spi_set_op_mode(int spi_num, esp_rom_spiflash_read_mode_t mode);
145 
146 /**
147  * @brief Set data swap mode in DTR(DDR) mode
148  * @param spi_num spi port
149  * @param wr_swap to decide whether to swap fifo data in dtr write operation
150  * @param rd_swap to decide whether to swap fifo data in dtr read operation
151  */
152 void esp_rom_spi_set_dtr_swap_mode(int spi, bool wr_swap, bool rd_swap);
153 
154 
155 /**
156  * @brief to send reset command in spi/opi-str/opi-dtr mode(for MX25UM25645G)
157  * @param spi_num spi port
158  */
159 void esp_rom_opiflash_mode_reset(int spi_num);
160 
161 #if 0
162 // MX25UM25645G opi flash interface
163 /**
164  * @brief To execute a flash operation command
165  * @param spi_num spi port
166  * @param mode Flash Read Mode
167  * @param cmd data to send in command field
168  * @param cmd_bit_len bit length of command field
169  * @param addr data to send in address field
170  * @param addr_bit_len bit length of address field
171  * @param dummy_bits bit length of dummy field
172  * @param mosi_data data buffer to be sent in mosi field
173  * @param mosi_bit_len bit length of data buffer to be sent in mosi field
174  * @param miso_data data buffer to accept data in miso field
175  * @param miso_bit_len bit length of data buffer to accept data in miso field
176  * @param cs_mark decide which cs pin to use. 0: cs0, 1: cs1
177  * @param is_write_erase_operation to indicate whether this a write or erase flash operation
178  */
179 void esp_rom_opiflash_exec_cmd(int spi_num, esp_rom_spiflash_read_mode_t mode,
180                                   uint32_t cmd, int cmd_bit_len,
181                                   uint32_t addr, int addr_bit_len,
182                                   int dummy_bits,
183                                   uint8_t* mosi_data, int mosi_bit_len,
184                                   uint8_t* miso_data, int miso_bit_len,
185                                   uint32_t cs_mask,
186                                   bool is_write_erase_operation);
187 
188 /**
189  * @brief send reset command to opi flash
190  * @param spi_num spi port
191  * @param mode Flash Operation Mode
192  */
193 void esp_rom_opiflash_soft_reset(int spi_num, esp_rom_spiflash_read_mode_t mode);
194 
195 #endif
196 
197 #ifdef __cplusplus
198 }
199 #endif
200 
201 #endif
202