1 // Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD 2 // 3 // Licensed under the Apache License, Version 2.0 (the "License"); 4 // you may not use this file except in compliance with the License. 5 // You may obtain a copy of the License at 6 7 // http://www.apache.org/licenses/LICENSE-2.0 8 // 9 // Unless required by applicable law or agreed to in writing, software 10 // distributed under the License is distributed on an "AS IS" BASIS, 11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 // See the License for the specific language governing permissions and 13 // limitations under the License. 14 15 #ifndef _ROM_CACHE_H_ 16 #define _ROM_CACHE_H_ 17 18 19 #ifdef __cplusplus 20 extern "C" { 21 #endif 22 23 /** \defgroup cache_apis, cache operation related apis 24 * @brief cache apis 25 */ 26 27 /** @addtogroup cache_apis 28 * @{ 29 */ 30 31 #define MIN_CACHE_SIZE 8192 32 #define MAX_CACHE_SIZE 16384 33 #define MIN_CACHE_WAYS 4 34 #define MAX_CACHE_WAYS 4 35 #define MIN_CACHE_LINE_SIZE 16 36 //normally should be (MAX_CACHE_SIZE / MIN_CACHE_WAYS / MIN_CACHE_LINE_SIZE), however, the items not all in one tag memory block. 37 #define MAX_TAG_BLOCK_ITEMS (MAX_CACHE_SIZE / 8 / MIN_CACHE_LINE_SIZE) 38 #define TAG_SIZE 4 39 #define MAX_TAG_BLOCK_SIZE (MAX_TAG_BLOCK_ITEMS * TAG_SIZE) 40 41 #define INVALID_PHY_PAGE 0xffff 42 #define ESP_CACHE_TEMP_ADDR DROM0_ADDRESS_LOW 43 #define CACHE_MAX_OPERATION_SIZE BUS_ADDR_SIZE 44 45 46 typedef enum { 47 CACHE_DCACHE = 0, 48 CACHE_ICACHE = 1, 49 } cache_t; 50 51 typedef enum { 52 CACHE_MEMORY_INVALID = 0, 53 CACHE_MEMORY_ICACHE_LOW = 1<<0, 54 CACHE_MEMORY_ICACHE_HIGH = 1<<1, 55 CACHE_MEMORY_DCACHE_LOW = 1<<2, 56 CACHE_MEMORY_DCACHE_HIGH = 1<<3, 57 } cache_layout_t; 58 59 #define CACHE_SIZE_8KB CACHE_SIZE_HALF 60 #define CACHE_SIZE_16KB CACHE_SIZE_FULL 61 typedef enum { 62 CACHE_SIZE_HALF = 0, /*!< 8KB for icache and dcache */ 63 CACHE_SIZE_FULL = 1, /*!< 16KB for icache and dcache */ 64 } cache_size_t; 65 66 typedef enum { 67 CACHE_4WAYS_ASSOC = 0, /*!< 4 way associated cache */ 68 } cache_ways_t; 69 70 typedef enum { 71 CACHE_LINE_SIZE_16B = 0, /*!< 16 Byte cache line size */ 72 CACHE_LINE_SIZE_32B = 1, /*!< 32 Byte cache line size */ 73 } cache_line_size_t; 74 75 typedef enum { 76 CACHE_AUTOLOAD_POSITIVE = 0, /*!< cache autoload step is positive */ 77 CACHE_AUTOLOAD_NEGATIVE = 1, /*!< cache autoload step is negative */ 78 } cache_autoload_order_t; 79 80 #define CACHE_AUTOLOAD_STEP(i) ((i) - 1) 81 82 typedef enum { 83 CACHE_AUTOLOAD_MISS_TRIGGER = 0, /*!< autoload only triggered by cache miss */ 84 CACHE_AUTOLOAD_HIT_TRIGGER = 1, /*!< autoload only triggered by cache hit */ 85 CACHE_AUTOLOAD_BOTH_TRIGGER = 2, /*!< autoload triggered both by cache miss and hit */ 86 } cache_autoload_trigger_t; 87 88 struct cache_mode { 89 uint32_t cache_size; /*!< cache size in byte */ 90 uint16_t cache_line_size; /*!< cache line size in byte */ 91 uint8_t cache_ways; /*!< cache ways, always 4 */ 92 uint8_t icache; /*!< the cache index, 0 for dcache, 1 for icache */ 93 }; 94 95 struct tag_item { 96 uint32_t dirty:1; /*!< the cache line value is dirty or not */ 97 uint32_t tag:14; /*!< the tag is the high part of the cache address, however is only 16MB range, and with out low part */ 98 uint32_t valid:1; /*!< the tag item is valid or not */ 99 uint32_t fifo_cnt:3; /*!< fifo cnt, 0 ~ 3 for 4 ways cache, 0 ~ 7 for 8 ways cache */ 100 uint32_t lock:1; /*!< the cache line is locked or not */ 101 uint32_t attr:3; /*!< the attribute of the external memory physical address */ 102 uint32_t access:1; /*!< software accessable, used by hardware */ 103 uint32_t reserved:8; 104 }; 105 106 struct autoload_config { 107 uint8_t order; /*!< autoload step is positive or negative */ 108 uint8_t trigger; /*!< autoload trigger */ 109 uint8_t ena0; /*!< autoload region0 enable */ 110 uint8_t ena1; /*!< autoload region1 enable */ 111 uint32_t addr0; /*!< autoload region0 start address */ 112 uint32_t size0; /*!< autoload region0 size */ 113 uint32_t addr1; /*!< autoload region1 start address */ 114 uint32_t size1; /*!< autoload region1 size */ 115 }; 116 117 struct tag_group_info { 118 struct cache_mode mode; /*!< cache and cache mode */ 119 uint32_t filter_addr; /*!< the address that used to generate the struct */ 120 uint32_t vaddr_offset; /*!< virtual address offset of the cache ways */ 121 uint32_t tag_addr[MAX_CACHE_WAYS]; /*!< tag memory address, only [0~mode.ways-1] is valid to use */ 122 uint32_t cache_memory_offset[MAX_CACHE_WAYS]; /*!< cache memory address, only [0~mode.ways-1] is valid to use */ 123 }; 124 125 struct lock_config { 126 uint32_t addr; /*!< manual lock address*/ 127 uint16_t size; /*!< manual lock size*/ 128 uint16_t group; /*!< manual lock group, 0 or 1*/ 129 }; 130 131 #define ESP_ROM_ERR_INVALID_ARG 1 132 #define MMU_SET_ADDR_ALIGNED_ERROR 2 133 #define MMU_SET_PASE_SIZE_ERROR 3 134 #define MMU_SET_VADDR_OUT_RANGE 4 135 136 /** 137 * @brief Initialise cache mmu, mark all entries as invalid. 138 * Please do not call this function in your SDK application. 139 * 140 * @param None 141 * 142 * @return None 143 */ 144 void Cache_MMU_Init(void); 145 146 /** 147 * @brief Set ICache mmu mapping. 148 * Please do not call this function in your SDK application. 149 * 150 * @param uint32_t ext_ram : DPORT_MMU_ACCESS_FLASH for flash, DPORT_MMU_ACCESS_SPIRAM for spiram, DPORT_MMU_INVALID for invalid. 151 * 152 * @param uint32_t vaddr : virtual address in CPU address space. 153 * Can be Iram0,Iram1,Irom0,Drom0 and AHB buses address. 154 * Should be aligned by psize. 155 * 156 * @param uint32_t paddr : physical address in external memory. 157 * Should be aligned by psize. 158 * 159 * @param uint32_t psize : page size of ICache, in kilobytes. Should be 64 here. 160 * 161 * @param uint32_t num : pages to be set. 162 * 163 * @param uint32_t fixed : 0 for physical pages grow with virtual pages, other for virtual pages map to same physical page. 164 * 165 * @return uint32_t: error status 166 * 0 : mmu set success 167 * 2 : vaddr or paddr is not aligned 168 * 3 : psize error 169 * 4 : vaddr is out of range 170 */ 171 int Cache_Ibus_MMU_Set(uint32_t ext_ram, uint32_t vaddr, uint32_t paddr, uint32_t psize, uint32_t num, uint32_t fixed); 172 173 /** 174 * @brief Set DCache mmu mapping. 175 * Please do not call this function in your SDK application. 176 * 177 * @param uint32_t ext_ram : DPORT_MMU_ACCESS_FLASH for flash, DPORT_MMU_ACCESS_SPIRAM for spiram, DPORT_MMU_INVALID for invalid. 178 * 179 * @param uint32_t vaddr : virtual address in CPU address space. 180 * Can be DRam0, DRam1, DRom0, DPort and AHB buses address. 181 * Should be aligned by psize. 182 * 183 * @param uint32_t paddr : physical address in external memory. 184 * Should be aligned by psize. 185 * 186 * @param uint32_t psize : page size of DCache, in kilobytes. Should be 64 here. 187 * 188 * @param uint32_t num : pages to be set. 189 190 * @param uint32_t fixed : 0 for physical pages grow with virtual pages, other for virtual pages map to same physical page. 191 * 192 * @return uint32_t: error status 193 * 0 : mmu set success 194 * 2 : vaddr or paddr is not aligned 195 * 3 : psize error 196 * 4 : vaddr is out of range 197 */ 198 int Cache_Dbus_MMU_Set(uint32_t ext_ram, uint32_t vaddr, uint32_t paddr, uint32_t psize, uint32_t num, uint32_t fixed); 199 200 /** 201 * @brief Count the pages in the bus room address which map to Flash. 202 * Please do not call this function in your SDK application. 203 * 204 * @param uint32_t bus : the bus to count with. 205 * 206 * @param uint32_t * page0_mapped : value should be initial by user, 0 for not mapped, other for mapped count. 207 * 208 * return uint32_t : the number of pages which map to Flash. 209 */ 210 uint32_t Cache_Count_Flash_Pages(uint32_t bus, uint32_t * page0_mapped); 211 212 /** 213 * @brief Copy Instruction or rodata from Flash to SPIRAM, and remap to SPIRAM. 214 * Please do not call this function in your SDK application. 215 * 216 * @param uint32_t bus : the bus which need to copy to SPIRAM. 217 * 218 * @param uint32_t bus_start_addr : the start virtual address for the bus. 219 * 220 * @param uint32_t start_page : the start (64KB) page number in SPIRAM. 221 * 222 * @param uint32_t * page0_page : the flash page0 in SPIRAM page number, 0xffff for invalid. 223 * 224 * return uint32_t : the next start page number for SPIRAM not mapped. 225 */ 226 uint32_t Cache_Flash_To_SPIRAM_Copy(uint32_t bus, uint32_t bus_start_addr, uint32_t start_page, uint32_t * page0_page); 227 228 229 /** 230 * @brief allocate memory to used by ICache and DCache. 231 * Please do not call this function in your SDK application. 232 * 233 * @param cache_layout_t sram0_layout : the usage of first 8KB internal memory block, can be CACHE_MEMORY_INVALID, CACHE_MEMORY_ICACHE_LOW, CACHE_MEMORY_ICACHE_HIGH, CACHE_MEMORY_DCACHE_LOW and CACHE_MEMORY_DCACHE_HIGH 234 * 235 * @param cache_layout_t sram1_layout : the usage of second 8KB internal memory block 236 * 237 * @param cache_layout_t sram2_layout : the usage of third 8KB internal memory block 238 * 239 * @param cache_layout_t sram3_layout : the usage of forth 8KB internal memory block 240 * 241 * return none 242 */ 243 void Cache_Allocate_SRAM(cache_layout_t sram0_layout, cache_layout_t sram1_layout, cache_layout_t sram2_layout, cache_layout_t sram3_layout); 244 245 /** 246 * @brief Get cache mode of ICache or DCache. 247 * Please do not call this function in your SDK application. 248 * 249 * @param struct cache_mode * mode : the pointer of cache mode struct, caller should set the icache field 250 * 251 * return none 252 */ 253 void Cache_Get_Mode(struct cache_mode * mode); 254 255 /** 256 * @brief set ICache modes: cache size, associate ways and cache line size. 257 * Please do not call this function in your SDK application. 258 * 259 * @param cache_size_t cache_size : the cache size, can be CACHE_SIZE_HALF and CACHE_SIZE_FULL 260 * 261 * @param cache_ways_t ways : the associate ways of cache, can only be CACHE_4WAYS_ASSOC 262 * 263 * @param cache_line_size_t cache_line_size : the cache line size, can be CACHE_LINE_SIZE_16B, CACHE_LINE_SIZE_32B 264 * 265 * return none 266 */ 267 void Cache_Set_ICache_Mode(cache_size_t cache_size, cache_ways_t ways, cache_line_size_t cache_line_size); 268 269 /** 270 * @brief set DCache modes: cache size, associate ways and cache line size. 271 * Please do not call this function in your SDK application. 272 * 273 * @param cache_size_t cache_size : the cache size, can be CACHE_SIZE_HALF and CACHE_SIZE_FULL 274 * 275 * @param cache_ways_t ways : the associate ways of cache, can only be CACHE_4WAYS_ASSOC 276 * 277 * @param cache_line_size_t cache_line_size : the cache line size, can be CACHE_LINE_SIZE_16B, CACHE_LINE_SIZE_32B 278 * 279 * return none 280 */ 281 void Cache_Set_DCache_Mode(cache_size_t cache_size, cache_ways_t ways, cache_line_size_t cache_line_size); 282 283 /** 284 * @brief check if the address is accessed through ICache. 285 * Please do not call this function in your SDK application. 286 * 287 * @param uint32_t addr : the address to check. 288 * 289 * @return 1 if the address is accessed through ICache, 0 if not. 290 */ 291 uint32_t Cache_Address_Through_ICache(uint32_t addr); 292 293 /** 294 * @brief check if the address is accessed through DCache. 295 * Please do not call this function in your SDK application. 296 * 297 * @param uint32_t addr : the address to check. 298 * 299 * @return 1 if the address is accessed through DCache, 0 if not. 300 */ 301 uint32_t Cache_Address_Through_DCache(uint32_t addr); 302 303 /** 304 * @brief Invalidate the cache items for ICache. 305 * Operation will be done CACHE_LINE_SIZE aligned. 306 * If the region is not in ICache addr room, nothing will be done. 307 * Please do not call this function in your SDK application. 308 * 309 * @param uint32_t addr: start address to invalidate 310 * 311 * @param uint32_t items: cache lines to invalidate, items * cache_line_size should not exceed the bus address size(4MB) 312 * 313 * @return None 314 */ 315 void Cache_Invalidate_ICache_Items(uint32_t addr, uint32_t items); 316 317 /** 318 * @brief Invalidate the cache items for DCache. 319 * Operation will be done CACHE_LINE_SIZE aligned. 320 * If the region is not in DCache addr room, nothing will be done. 321 * Please do not call this function in your SDK application. 322 * 323 * @param uint32_t addr: start address to invalidate 324 * 325 * @param uint32_t items: cache lines to invalidate, items * cache_line_size should not exceed the bus address size(4MB) 326 * 327 * @return None 328 */ 329 void Cache_Invalidate_DCache_Items(uint32_t addr, uint32_t items); 330 331 /** 332 * @brief Clean the dirty bit of cache Items of DCache. 333 * Operation will be done CACHE_LINE_SIZE aligned. 334 * If the region is not in DCache addr room, nothing will be done. 335 * Please do not call this function in your SDK application. 336 * 337 * @param uint32_t addr: start address to Clean 338 * 339 * @param uint32_t items: cache lines to invalidate, items * cache_line_size should not exceed the bus address size(4MB) 340 * 341 * @return None 342 */ 343 void Cache_Clean_Items(uint32_t addr, uint32_t items); 344 345 /** 346 * @brief Write back the cache items of DCache. 347 * Operation will be done CACHE_LINE_SIZE aligned. 348 * If the region is not in DCache addr room, nothing will be done. 349 * Please do not call this function in your SDK application. 350 * 351 * @param uint32_t addr: start address to write back 352 * 353 * @param uint32_t items: cache lines to invalidate, items * cache_line_size should not exceed the bus address size(4MB) 354 * 355 * @return None 356 */ 357 void Cache_WriteBack_Items(uint32_t addr, uint32_t items); 358 359 /** 360 * @brief Invalidate the Cache items in the region from ICache or DCache. 361 * If the region is not in Cache addr room, nothing will be done. 362 * Please do not call this function in your SDK application. 363 * 364 * @param uint32_t addr : invalidated region start address. 365 * 366 * @param uint32_t size : invalidated region size. 367 * 368 * @return 0 for success 369 * 1 for invalid argument 370 */ 371 int Cache_Invalidate_Addr(uint32_t addr, uint32_t size); 372 373 /** 374 * @brief Clean the dirty bit of Cache items in the region from DCache. 375 * If the region is not in DCache addr room, nothing will be done. 376 * Please do not call this function in your SDK application. 377 * 378 * @param uint32_t addr : cleaned region start address. 379 * 380 * @param uint32_t size : cleaned region size. 381 * 382 * @return 0 for success 383 * 1 for invalid argument 384 */ 385 int Cache_Clean_Addr(uint32_t addr, uint32_t size); 386 387 /** 388 * @brief Writeback the Cache items(also clean the dirty bit) in the region from DCache. 389 * If the region is not in DCache addr room, nothing will be done. 390 * Please do not call this function in your SDK application. 391 * 392 * @param uint32_t addr : writeback region start address. 393 * 394 * @param uint32_t size : writeback region size. 395 * 396 * @return 0 for success 397 * 1 for invalid argument 398 */ 399 int Cache_WriteBack_Addr(uint32_t addr, uint32_t size); 400 401 402 /** 403 * @brief Invalidate all cache items in ICache. 404 * Please do not call this function in your SDK application. 405 * 406 * @param None 407 * 408 * @return None 409 */ 410 void Cache_Invalidate_ICache_All(void); 411 412 /** 413 * @brief Invalidate all cache items in DCache. 414 * Please do not call this function in your SDK application. 415 * 416 * @param None 417 * 418 * @return None 419 */ 420 void Cache_Invalidate_DCache_All(void); 421 422 /** 423 * @brief Clean the dirty bit of all cache items in DCache. 424 * Please do not call this function in your SDK application. 425 * 426 * @param None 427 * 428 * @return None 429 */ 430 void Cache_Clean_All(void); 431 432 /** 433 * @brief WriteBack all cache items in DCache. 434 * Please do not call this function in your SDK application. 435 * 436 * @param None 437 * 438 * @return None 439 */ 440 void Cache_WriteBack_All(void); 441 442 /** 443 * @brief Mask all buses through ICache and DCache. 444 * Please do not call this function in your SDK application. 445 * 446 * @param None 447 * 448 * @return None 449 */ 450 void Cache_Mask_All(void); 451 452 /** 453 * @brief UnMask DRom0 bus through ICache. 454 * Please do not call this function in your SDK application. 455 * 456 * @param None 457 * 458 * @return None 459 */ 460 void Cache_UnMask_Drom0(void); 461 462 /** 463 * @brief Suspend ICache auto preload operation, then you can resume it after some ICache operations. 464 * Please do not call this function in your SDK application. 465 * 466 * @param None 467 * 468 * @return uint32_t : 0 for ICache not auto preload before suspend. 469 */ 470 uint32_t Cache_Suspend_ICache_Autoload(void); 471 472 /** 473 * @brief Resume ICache auto preload operation after some ICache operations. 474 * Please do not call this function in your SDK application. 475 * 476 * @param uint32_t autoload : 0 for ICache not auto preload before suspend. 477 * 478 * @return None. 479 */ 480 void Cache_Resume_ICache_Autoload(uint32_t autoload); 481 482 /** 483 * @brief Suspend DCache auto preload operation, then you can resume it after some DCache operations. 484 * Please do not call this function in your SDK application. 485 * 486 * @param None 487 * 488 * @return uint32_t : 0 for DCache not auto preload before suspend. 489 */ 490 uint32_t Cache_Suspend_DCache_Autoload(void); 491 492 /** 493 * @brief Resume DCache auto preload operation after some DCache operations. 494 * Please do not call this function in your SDK application. 495 * 496 * @param uint32_t autoload : 0 for DCache not auto preload before suspend. 497 * 498 * @return None. 499 */ 500 void Cache_Resume_DCache_Autoload(uint32_t autoload); 501 502 /** 503 * @brief Start an ICache manual preload, will suspend auto preload of ICache. 504 * Please do not call this function in your SDK application. 505 * 506 * @param uint32_t addr : start address of the preload region. 507 * 508 * @param uint32_t size : size of the preload region, should not exceed the size of ICache. 509 * 510 * @param uint32_t order : the preload order, 0 for positive, other for negative 511 * 512 * @return uint32_t : 0 for ICache not auto preload before manual preload. 513 */ 514 uint32_t Cache_Start_ICache_Preload(uint32_t addr, uint32_t size, uint32_t order); 515 516 /** 517 * @brief Return if the ICache manual preload done. 518 * Please do not call this function in your SDK application. 519 * 520 * @param None 521 * 522 * @return uint32_t : 0 for ICache manual preload not done. 523 */ 524 uint32_t Cache_ICache_Preload_Done(void); 525 526 /** 527 * @brief End the ICache manual preload to resume auto preload of ICache. 528 * Please do not call this function in your SDK application. 529 * 530 * @param uint32_t autoload : 0 for ICache not auto preload before manual preload. 531 * 532 * @return None 533 */ 534 void Cache_End_ICache_Preload(uint32_t autoload); 535 536 /** 537 * @brief Start an DCache manual preload, will suspend auto preload of DCache. 538 * Please do not call this function in your SDK application. 539 * 540 * @param uint32_t addr : start address of the preload region. 541 * 542 * @param uint32_t size : size of the preload region, should not exceed the size of DCache. 543 * 544 * @param uint32_t order : the preload order, 0 for positive, other for negative 545 * 546 * @return uint32_t : 0 for DCache not auto preload before manual preload. 547 */ 548 uint32_t Cache_Start_DCache_Preload(uint32_t addr, uint32_t size, uint32_t order); 549 550 /** 551 * @brief Return if the DCache manual preload done. 552 * Please do not call this function in your SDK application. 553 * 554 * @param None 555 * 556 * @return uint32_t : 0 for DCache manual preload not done. 557 */ 558 uint32_t Cache_DCache_Preload_Done(void); 559 560 /** 561 * @brief End the DCache manual preload to resume auto preload of DCache. 562 * Please do not call this function in your SDK application. 563 * 564 * @param uint32_t autoload : 0 for DCache not auto preload before manual preload. 565 * 566 * @return None 567 */ 568 void Cache_End_DCache_Preload(uint32_t autoload); 569 570 /** 571 * @brief Config autoload parameters of ICache. 572 * Please do not call this function in your SDK application. 573 * 574 * @param struct autoload_config * config : autoload parameters. 575 * 576 * @return None 577 */ 578 void Cache_Config_ICache_Autoload(const struct autoload_config * config); 579 580 /** 581 * @brief Enable auto preload for ICache. 582 * Please do not call this function in your SDK application. 583 * 584 * @param None 585 * 586 * @return None 587 */ 588 void Cache_Enable_ICache_Autoload(void); 589 590 /** 591 * @brief Disable auto preload for ICache. 592 * Please do not call this function in your SDK application. 593 * 594 * @param None 595 * 596 * @return None 597 */ 598 void Cache_Disable_ICache_Autoload(void); 599 600 /** 601 * @brief Config autoload parameters of DCache. 602 * Please do not call this function in your SDK application. 603 * 604 * @param struct autoload_config * config : autoload parameters. 605 * 606 * @return None 607 */ 608 void Cache_Config_DCache_Autoload(const struct autoload_config * config); 609 610 /** 611 * @brief Enable auto preload for DCache. 612 * Please do not call this function in your SDK application. 613 * 614 * @param None 615 * 616 * @return None 617 */ 618 void Cache_Enable_DCache_Autoload(void); 619 620 /** 621 * @brief Disable auto preload for DCache. 622 * Please do not call this function in your SDK application. 623 * 624 * @param None 625 * 626 * @return None 627 */ 628 void Cache_Disable_DCache_Autoload(void); 629 630 /** 631 * @brief Config a group of prelock parameters of ICache. 632 * Please do not call this function in your SDK application. 633 * 634 * @param struct lock_config * config : a group of lock parameters. 635 * 636 * @return None 637 */ 638 639 void Cache_Enable_ICache_PreLock(const struct lock_config *config); 640 641 /** 642 * @brief Disable a group of prelock parameters for ICache. 643 * However, the locked data will not be released. 644 * Please do not call this function in your SDK application. 645 * 646 * @param uint16_t group : 0 for group0, 1 for group1. 647 * 648 * @return None 649 */ 650 void Cache_Disable_ICache_PreLock(uint16_t group); 651 652 /** 653 * @brief Lock the cache items for ICache. 654 * Operation will be done CACHE_LINE_SIZE aligned. 655 * If the region is not in ICache addr room, nothing will be done. 656 * Please do not call this function in your SDK application. 657 * 658 * @param uint32_t addr: start address to lock 659 * 660 * @param uint32_t items: cache lines to lock, items * cache_line_size should not exceed the bus address size(4MB) 661 * 662 * @return None 663 */ 664 void Cache_Lock_ICache_Items(uint32_t addr, uint32_t items); 665 666 /** 667 * @brief Unlock the cache items for ICache. 668 * Operation will be done CACHE_LINE_SIZE aligned. 669 * If the region is not in ICache addr room, nothing will be done. 670 * Please do not call this function in your SDK application. 671 * 672 * @param uint32_t addr: start address to unlock 673 * 674 * @param uint32_t items: cache lines to unlock, items * cache_line_size should not exceed the bus address size(4MB) 675 * 676 * @return None 677 */ 678 void Cache_Unlock_ICache_Items(uint32_t addr, uint32_t items); 679 680 /** 681 * @brief Config a group of prelock parameters of DCache. 682 * Please do not call this function in your SDK application. 683 * 684 * @param struct lock_config * config : a group of lock parameters. 685 * 686 * @return None 687 */ 688 void Cache_Enable_DCache_PreLock(const struct lock_config *config); 689 690 /** 691 * @brief Disable a group of prelock parameters for DCache. 692 * However, the locked data will not be released. 693 * Please do not call this function in your SDK application. 694 * 695 * @param uint16_t group : 0 for group0, 1 for group1. 696 * 697 * @return None 698 */ 699 void Cache_Disable_DCache_PreLock(uint16_t group); 700 701 /** 702 * @brief Lock the cache items for DCache. 703 * Operation will be done CACHE_LINE_SIZE aligned. 704 * If the region is not in DCache addr room, nothing will be done. 705 * Please do not call this function in your SDK application. 706 * 707 * @param uint32_t addr: start address to lock 708 * 709 * @param uint32_t items: cache lines to lock, items * cache_line_size should not exceed the bus address size(4MB) 710 * 711 * @return None 712 */ 713 void Cache_Lock_DCache_Items(uint32_t addr, uint32_t items); 714 715 /** 716 * @brief Unlock the cache items for DCache. 717 * Operation will be done CACHE_LINE_SIZE aligned. 718 * If the region is not in DCache addr room, nothing will be done. 719 * Please do not call this function in your SDK application. 720 * 721 * @param uint32_t addr: start address to unlock 722 * 723 * @param uint32_t items: cache lines to unlock, items * cache_line_size should not exceed the bus address size(4MB) 724 * 725 * @return None 726 */ 727 void Cache_Unlock_DCache_Items(uint32_t addr, uint32_t items); 728 729 /** 730 * @brief Lock the cache items in tag memory for ICache or DCache. 731 * Please do not call this function in your SDK application. 732 * 733 * @param uint32_t addr : start address of lock region. 734 * 735 * @param uint32_t size : size of lock region. 736 * 737 * @return 0 for success 738 * 1 for invalid argument 739 */ 740 int Cache_Lock_Addr(uint32_t addr, uint32_t size); 741 742 /** 743 * @brief Unlock the cache items in tag memory for ICache or DCache. 744 * Please do not call this function in your SDK application. 745 * 746 * @param uint32_t addr : start address of unlock region. 747 * 748 * @param uint32_t size : size of unlock region. 749 * 750 * @return 0 for success 751 * 1 for invalid argument 752 */ 753 int Cache_Unlock_Addr(uint32_t addr, uint32_t size); 754 755 /** 756 * @brief Disable ICache access for the cpu. 757 * This operation will make all ICache tag memory invalid, CPU can't access ICache, ICache will keep idle. 758 * Please do not call this function in your SDK application. 759 * 760 * @return uint32_t : auto preload enabled before 761 */ 762 uint32_t Cache_Disable_ICache(void); 763 764 /** 765 * @brief Enable ICache access for the cpu. 766 * Please do not call this function in your SDK application. 767 * 768 * @param uint32_t autoload : ICache will preload then. 769 * 770 * @return None 771 */ 772 void Cache_Enable_ICache(uint32_t autoload); 773 774 /** 775 * @brief Disable DCache access for the cpu. 776 * This operation will make all DCache tag memory invalid, CPU can't access DCache, DCache will keep idle 777 * Please do not call this function in your SDK application. 778 * 779 * @return uint32_t : auto preload enabled before 780 */ 781 uint32_t Cache_Disable_DCache(void); 782 783 /** 784 * @brief Enable DCache access for the cpu. 785 * Please do not call this function in your SDK application. 786 * 787 * @param uint32_t autoload : DCache will preload then. 788 * 789 * @return None 790 */ 791 void Cache_Enable_DCache(uint32_t autoload); 792 793 /** 794 * @brief Suspend ICache access for the cpu. 795 * The ICache tag memory is still there, CPU can't access ICache, ICache will keep idle. 796 * Please do not change MMU, cache mode or tag memory(tag memory can be changed in some special case). 797 * Please do not call this function in your SDK application. 798 * 799 * @param None 800 * 801 * @return uint32_t : auto preload enabled before 802 */ 803 uint32_t Cache_Suspend_ICache(void); 804 805 /** 806 * @brief Resume ICache access for the cpu. 807 * Please do not call this function in your SDK application. 808 * 809 * @param uint32_t autoload : ICache will preload then. 810 * 811 * @return None 812 */ 813 void Cache_Resume_ICache(uint32_t autoload); 814 815 /** 816 * @brief Suspend DCache access for the cpu. 817 * The ICache tag memory is still there, CPU can't access DCache, DCache will keep idle. 818 × Please do not change MMU, cache mode or tag memory(tag memory can be changed in some special case). 819 * Please do not call this function in your SDK application. 820 * 821 * @param None 822 * 823 * @return uint32_t : auto preload enabled before 824 */ 825 uint32_t Cache_Suspend_DCache(void); 826 827 /** 828 * @brief Resume DCache access for the cpu. 829 * Please do not call this function in your SDK application. 830 * 831 * @param uint32_t autoload : DCache will preload then. 832 * 833 * @return None 834 */ 835 void Cache_Resume_DCache(uint32_t autoload); 836 837 /** 838 * @brief Get ICache cache line size 839 * 840 * @param None 841 * 842 * @return uint32_t: 16, 32 Byte 843 */ 844 uint32_t Cache_Get_ICache_Line_Size(void); 845 846 /** 847 * @brief Get DCache cache line size 848 * 849 * @param None 850 * 851 * @return uint32_t: 16, 32 Byte 852 */ 853 uint32_t Cache_Get_DCache_Line_Size(void); 854 855 /** 856 * @brief Set default mode from boot, 8KB ICache, 16Byte cache line size. 857 * 858 * @param None 859 * 860 * @return None 861 */ 862 void Cache_Set_Default_Mode(void); 863 864 /** 865 * @brief Set default mode from boot, 8KB DCache, 16Byte cache line size. 866 * 867 * @param None 868 * 869 * @return None 870 */ 871 void Cache_Enable_Defalut_DCache_Mode(void); 872 873 /** 874 * @brief Travel tag memory to run a call back function. 875 * ICache and DCache are suspend when doing this. 876 * The callback will get the parameter tag_group_info, which will include a group of tag memory addresses and cache memory addresses. 877 * Please do not call this function in your SDK application. 878 * 879 * @param struct cache_mode * mode : the cache to check and the cache mode. 880 * 881 * @param uint32_t filter_addr : only the cache lines which may include the filter_address will be returned to the call back function. 882 * 0 for do not filter, all cache lines will be returned. 883 * 884 * @param void (* process)(struct tag_group_info *) : call back function, which may be called many times, a group(the addresses in the group are in the same position in the cache ways) a time. 885 * 886 * @return None 887 */ 888 void Cache_Travel_Tag_Memory(struct cache_mode * mode, uint32_t filter_addr, void (* process)(struct tag_group_info *)); 889 890 /** 891 * @brief Get the virtual address from cache mode, cache tag and the virtual address offset of cache ways. 892 * Please do not call this function in your SDK application. 893 * 894 * @param struct cache_mode * mode : the cache to calculate the virtual address and the cache mode. 895 * 896 * @param uint32_t tag : the tag part fo a tag item, 12-14 bits. 897 * 898 * @param uint32_t addr_offset : the virtual address offset of the cache ways. 899 * 900 * @return uint32_t : the virtual address. 901 */ 902 uint32_t Cache_Get_Virtual_Addr(struct cache_mode *mode, uint32_t tag, uint32_t vaddr_offset); 903 904 /** 905 * @brief Get cache memory block base address. 906 * Please do not call this function in your SDK application. 907 * 908 * @param uint32_t icache : 0 for dcache, other for icache. 909 * 910 * @param uint32_t high : 0 for low part block, 1 for high part block. 911 * 912 * @return uint32_t : the cache memory block base address, 0 if the block not used. 913 */ 914 uint32_t Cache_Get_Memory_BaseAddr(uint32_t icache, uint32_t high); 915 916 /** 917 * @brief Get the cache memory address from cache mode, cache memory offset and the virtual address offset of cache ways. 918 * Please do not call this function in your SDK application. 919 * 920 * @param struct cache_mode * mode : the cache to calculate the virtual address and the cache mode. 921 * 922 * @param uint32_t cache_memory_offset : the cache memory offset of the whole cache (ICache or DCache) for the cache line. 923 * 924 * @param uint32_t addr_offset : the virtual address offset of the cache ways. 925 * 926 * @return uint32_t : the virtual address. 927 */ 928 uint32_t Cache_Get_Memory_Addr(struct cache_mode *mode, uint32_t cache_memory_offset, uint32_t vaddr_offset); 929 930 /** 931 * @brief Get the cache memory value by DRAM address. 932 * Please do not call this function in your SDK application. 933 * 934 * @param uint32_t cache_memory_addr : DRAM address for the cache memory. 935 * 936 * @return uint32_t : the word value of the address. 937 */ 938 uint32_t Cache_Get_Memory_value(uint32_t cache_memory_addr); 939 /** 940 * @} 941 */ 942 943 #ifdef __cplusplus 944 } 945 #endif 946 947 #endif /* _ROM_CACHE_H_ */ 948
