1 // Copyright 2020 Espressif Systems (Shanghai) PTE LTD 2 // 3 // Licensed under the Apache License, Version 2.0 (the "License"); 4 // you may not use this file except in compliance with the License. 5 // You may obtain a copy of the License at 6 7 // http://www.apache.org/licenses/LICENSE-2.0 8 // 9 // Unless required by applicable law or agreed to in writing, software 10 // distributed under the License is distributed on an "AS IS" BASIS, 11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 // See the License for the specific language governing permissions and 13 // limitations under the License. 14 15 #ifndef _ROM_CACHE_H_ 16 #define _ROM_CACHE_H_ 17 18 #include <stdint.h> 19 #include "esp_bit_defs.h" 20 21 #ifdef __cplusplus 22 extern "C" { 23 #endif 24 25 /** \defgroup cache_apis, cache operation related apis 26 * @brief cache apis 27 */ 28 29 /** @addtogroup cache_apis 30 * @{ 31 */ 32 #define MIN_ICACHE_SIZE 16384 33 #define MAX_ICACHE_SIZE 16384 34 #define MIN_ICACHE_WAYS 8 35 #define MAX_ICACHE_WAYS 8 36 #define MAX_CACHE_WAYS 8 37 #define MIN_CACHE_LINE_SIZE 32 38 #define TAG_SIZE 4 39 #define MIN_ICACHE_BANK_NUM 1 40 #define MAX_ICACHE_BANK_NUM 1 41 #define CACHE_MEMORY_BANK_NUM 1 42 #define CACHE_MEMORY_IBANK_SIZE 0x4000 43 44 #define MAX_ITAG_BANK_ITEMS (MAX_ICACHE_SIZE / MAX_ICACHE_BANK_NUM / MIN_CACHE_LINE_SIZE) 45 #define MAX_ITAG_BLOCK_ITEMS (MAX_ICACHE_SIZE / MAX_ICACHE_BANK_NUM / MAX_ICACHE_WAYS / MIN_CACHE_LINE_SIZE) 46 #define MAX_ITAG_BANK_SIZE (MAX_ITAG_BANK_ITEMS * TAG_SIZE) 47 #define MAX_ITAG_BLOCK_SIZE (MAX_ITAG_BLOCK_ITEMS * TAG_SIZE) 48 49 typedef enum { 50 CACHE_DCACHE = 0, 51 CACHE_ICACHE0 = 1, 52 CACHE_ICACHE1 = 2, 53 } cache_t; 54 55 typedef enum { 56 CACHE_MEMORY_INVALID = 0, 57 CACHE_MEMORY_IBANK0 = BIT(0), 58 CACHE_MEMORY_IBANK1 = BIT(1), 59 CACHE_MEMORY_IBANK2 = BIT(2), 60 CACHE_MEMORY_IBANK3 = BIT(3), 61 CACHE_MEMORY_DBANK0 = BIT(0), 62 CACHE_MEMORY_DBANK1 = BIT(1), 63 CACHE_MEMORY_DBANK2 = BIT(2), 64 CACHE_MEMORY_DBANK3 = BIT(3), 65 } cache_array_t; 66 67 #define ICACHE_SIZE_16KB CACHE_SIZE_HALF 68 #define ICACHE_SIZE_32KB CACHE_SIZE_FULL 69 #define DCACHE_SIZE_32KB CACHE_SIZE_HALF 70 #define DCACHE_SIZE_64KB CACHE_SIZE_FULL 71 72 typedef enum { 73 CACHE_SIZE_HALF = 0, /*!< 8KB for icache and dcache */ 74 CACHE_SIZE_FULL = 1, /*!< 16KB for icache and dcache */ 75 } cache_size_t; 76 77 typedef enum { 78 CACHE_4WAYS_ASSOC = 0, /*!< 4 way associated cache */ 79 CACHE_8WAYS_ASSOC = 1, /*!< 8 way associated cache */ 80 } cache_ways_t; 81 82 typedef enum { 83 CACHE_LINE_SIZE_16B = 0, /*!< 16 Byte cache line size */ 84 CACHE_LINE_SIZE_32B = 1, /*!< 32 Byte cache line size */ 85 CACHE_LINE_SIZE_64B = 2, /*!< 64 Byte cache line size */ 86 } cache_line_size_t; 87 88 typedef enum { 89 CACHE_AUTOLOAD_POSITIVE = 0, /*!< cache autoload step is positive */ 90 CACHE_AUTOLOAD_NEGATIVE = 1, /*!< cache autoload step is negative */ 91 } cache_autoload_order_t; 92 93 #define CACHE_AUTOLOAD_STEP(i) ((i) - 1) 94 95 typedef enum { 96 CACHE_AUTOLOAD_MISS_TRIGGER = 0, /*!< autoload only triggered by cache miss */ 97 CACHE_AUTOLOAD_HIT_TRIGGER = 1, /*!< autoload only triggered by cache hit */ 98 CACHE_AUTOLOAD_BOTH_TRIGGER = 2, /*!< autoload triggered both by cache miss and hit */ 99 } cache_autoload_trigger_t; 100 101 typedef enum { 102 CACHE_FREEZE_ACK_BUSY = 0, /*!< in this mode, cache ack busy to CPU if a cache miss happens*/ 103 CACHE_FREEZE_ACK_ERROR = 1, /*!< in this mode, cache ack wrong data to CPU and trigger an error if a cache miss happens */ 104 } cache_freeze_mode_t; 105 106 struct cache_mode { 107 uint32_t cache_size; /*!< cache size in byte */ 108 uint16_t cache_line_size; /*!< cache line size in byte */ 109 uint8_t cache_ways; /*!< cache ways, always 4 */ 110 uint8_t ibus; /*!< the cache index, 0 for dcache, 1 for icache */ 111 }; 112 113 struct icache_tag_item { 114 uint32_t valid:1; /*!< the tag item is valid or not */ 115 uint32_t lock:1; /*!< the cache line is locked or not */ 116 uint32_t fifo_cnt:3; /*!< fifo cnt, 0 ~ 3 for 4 ways cache */ 117 uint32_t tag:13; /*!< the tag is the high part of the cache address, however is only 16MB (8MB Ibus + 8MB Dbus) range, and without low part */ 118 uint32_t reserved:14; 119 }; 120 121 struct autoload_config { 122 uint8_t order; /*!< autoload step is positive or negative */ 123 uint8_t trigger; /*!< autoload trigger */ 124 uint8_t ena0; /*!< autoload region0 enable */ 125 uint8_t ena1; /*!< autoload region1 enable */ 126 uint32_t addr0; /*!< autoload region0 start address */ 127 uint32_t size0; /*!< autoload region0 size */ 128 uint32_t addr1; /*!< autoload region1 start address */ 129 uint32_t size1; /*!< autoload region1 size */ 130 }; 131 132 struct tag_group_info { 133 struct cache_mode mode; /*!< cache and cache mode */ 134 uint32_t filter_addr; /*!< the address that used to generate the struct */ 135 uint32_t vaddr_offset; /*!< virtual address offset of the cache ways */ 136 uint32_t tag_addr[MAX_CACHE_WAYS]; /*!< tag memory address, only [0~mode.ways-1] is valid to use */ 137 uint32_t cache_memory_offset[MAX_CACHE_WAYS]; /*!< cache memory address, only [0~mode.ways-1] is valid to use */ 138 }; 139 140 struct lock_config { 141 uint32_t addr; /*!< manual lock address*/ 142 uint16_t size; /*!< manual lock size*/ 143 uint16_t group; /*!< manual lock group, 0 or 1*/ 144 }; 145 146 struct cache_internal_stub_table { 147 uint32_t (* icache_line_size)(void); 148 uint32_t (* icache_addr)(uint32_t addr); 149 uint32_t (* dcache_addr)(uint32_t addr); 150 void (* invalidate_icache_items)(uint32_t addr, uint32_t items); 151 void (* lock_icache_items)(uint32_t addr, uint32_t items); 152 void (* unlock_icache_items)(uint32_t addr, uint32_t items); 153 uint32_t (* suspend_icache_autoload)(void); 154 void (* resume_icache_autoload)(uint32_t autoload); 155 void (* freeze_icache_enable)(cache_freeze_mode_t mode); 156 void (* freeze_icache_disable)(void); 157 int (* op_addr)(uint32_t start_addr, uint32_t size, uint32_t cache_line_size, uint32_t max_sync_num, void(* cache_Iop)(uint32_t, uint32_t)); 158 }; 159 160 /* Defined in the interface file, default value is rom_default_cache_internal_table */ 161 extern const struct cache_internal_stub_table* rom_cache_internal_table_ptr; 162 163 typedef void (* cache_op_start)(void); 164 typedef void (* cache_op_end)(void); 165 166 typedef struct { 167 cache_op_start start; 168 cache_op_end end; 169 } cache_op_cb_t; 170 171 /* Defined in the interface file, default value is NULL */ 172 extern const cache_op_cb_t* rom_cache_op_cb; 173 174 #define ESP_ROM_ERR_INVALID_ARG 1 175 #define MMU_SET_ADDR_ALIGNED_ERROR 2 176 #define MMU_SET_PASE_SIZE_ERROR 3 177 #define MMU_SET_VADDR_OUT_RANGE 4 178 179 #define CACHE_OP_ICACHE_Y 1 180 #define CACHE_OP_ICACHE_N 0 181 182 /** 183 * @brief Initialise cache mmu, mark all entries as invalid. 184 * Please do not call this function in your SDK application. 185 * 186 * @param None 187 * 188 * @return None 189 */ 190 void Cache_MMU_Init(void); 191 192 /** 193 * @brief Set ICache mmu mapping. 194 * Please do not call this function in your SDK application. 195 * 196 * @param uint32_t ext_ram : DPORT_MMU_ACCESS_FLASH for flash, DPORT_MMU_INVALID for invalid. In 197 * esp32h2, external memory is always flash 198 * 199 * @param uint32_t vaddr : virtual address in CPU address space. 200 * Can be Iram0,Iram1,Irom0,Drom0 and AHB buses address. 201 * Should be aligned by psize. 202 * 203 * @param uint32_t paddr : physical address in external memory. 204 * Should be aligned by psize. 205 * 206 * @param uint32_t psize : page size of ICache, in kilobytes. Should be 64 here. 207 * 208 * @param uint32_t num : pages to be set. 209 * 210 * @param uint32_t fixed : 0 for physical pages grow with virtual pages, other for virtual pages map to same physical page. 211 * 212 * @return uint32_t: error status 213 * 0 : mmu set success 214 * 2 : vaddr or paddr is not aligned 215 * 3 : psize error 216 * 4 : vaddr is out of range 217 */ 218 int Cache_Ibus_MMU_Set(uint32_t ext_ram, uint32_t vaddr, uint32_t paddr, uint32_t psize, uint32_t num, uint32_t fixed); 219 220 /** 221 * @brief Set DCache mmu mapping. 222 * Please do not call this function in your SDK application. 223 * 224 * @param uint32_t ext_ram : DPORT_MMU_ACCESS_FLASH for flash, DPORT_MMU_INVALID for invalid. In 225 * esp32h2, external memory is always flash 226 * 227 * @param uint32_t vaddr : virtual address in CPU address space. 228 * Can be DRam0, DRam1, DRom0, DPort and AHB buses address. 229 * Should be aligned by psize. 230 * 231 * @param uint32_t paddr : physical address in external memory. 232 * Should be aligned by psize. 233 * 234 * @param uint32_t psize : page size of DCache, in kilobytes. Should be 64 here. 235 * 236 * @param uint32_t num : pages to be set. 237 238 * @param uint32_t fixed : 0 for physical pages grow with virtual pages, other for virtual pages map to same physical page. 239 * 240 * @return uint32_t: error status 241 * 0 : mmu set success 242 * 2 : vaddr or paddr is not aligned 243 * 3 : psize error 244 * 4 : vaddr is out of range 245 */ 246 int Cache_Dbus_MMU_Set(uint32_t ext_ram, uint32_t vaddr, uint32_t paddr, uint32_t psize, uint32_t num, uint32_t fixed); 247 248 /** 249 * @brief Count the pages in the bus room address which map to Flash. 250 * Please do not call this function in your SDK application. 251 * 252 * @param uint32_t bus : the bus to count with. 253 * 254 * @param uint32_t * page0_mapped : value should be initial by user, 0 for not mapped, other for mapped count. 255 * 256 * return uint32_t : the number of pages which map to Flash. 257 */ 258 uint32_t Cache_Count_Flash_Pages(uint32_t bus, uint32_t * page0_mapped); 259 260 /** 261 * @brief allocate memory to used by ICache. 262 * Please do not call this function in your SDK application. 263 * 264 * @param cache_array_t icache_low : the data array bank used by icache low part. Due to timing constraint, can only be CACHE_MEMORY_INVALID, CACHE_MEMORY_IBANK0 265 * 266 * return none 267 */ 268 void Cache_Occupy_ICache_MEMORY(cache_array_t icache_low); 269 270 /** 271 * @brief Get cache mode of ICache or DCache. 272 * Please do not call this function in your SDK application. 273 * 274 * @param struct cache_mode * mode : the pointer of cache mode struct, caller should set the icache field 275 * 276 * return none 277 */ 278 void Cache_Get_Mode(struct cache_mode * mode); 279 280 /** 281 * @brief set ICache modes: cache size, associate ways and cache line size. 282 * Please do not call this function in your SDK application. 283 * 284 * @param cache_size_t cache_size : the cache size, can be CACHE_SIZE_HALF and CACHE_SIZE_FULL 285 * 286 * @param cache_ways_t ways : the associate ways of cache, can be CACHE_4WAYS_ASSOC and CACHE_8WAYS_ASSOC 287 * 288 * @param cache_line_size_t cache_line_size : the cache line size, can be CACHE_LINE_SIZE_16B, CACHE_LINE_SIZE_32B and CACHE_LINE_SIZE_64B 289 * 290 * return none 291 */ 292 void Cache_Set_ICache_Mode(cache_size_t cache_size, cache_ways_t ways, cache_line_size_t cache_line_size); 293 294 /** 295 * @brief set DCache modes: cache size, associate ways and cache line size. 296 * Please do not call this function in your SDK application. 297 * 298 * @param cache_size_t cache_size : the cache size, can be CACHE_SIZE_8KB and CACHE_SIZE_16KB 299 * 300 * @param cache_ways_t ways : the associate ways of cache, can be CACHE_4WAYS_ASSOC and CACHE_8WAYS_ASSOC 301 * 302 * @param cache_line_size_t cache_line_size : the cache line size, can be CACHE_LINE_SIZE_16B, CACHE_LINE_SIZE_32B and CACHE_LINE_SIZE_64B 303 * 304 * return none 305 */ 306 void Cache_Set_DCache_Mode(cache_size_t cache_size, cache_ways_t ways, cache_line_size_t cache_line_size); 307 308 /** 309 * @brief check if the address is accessed through ICache. 310 * Please do not call this function in your SDK application. 311 * 312 * @param uint32_t addr : the address to check. 313 * 314 * @return 1 if the address is accessed through ICache, 0 if not. 315 */ 316 uint32_t Cache_Address_Through_ICache(uint32_t addr); 317 318 /** 319 * @brief check if the address is accessed through DCache. 320 * Please do not call this function in your SDK application. 321 * 322 * @param uint32_t addr : the address to check. 323 * 324 * @return 1 if the address is accessed through DCache, 0 if not. 325 */ 326 uint32_t Cache_Address_Through_DCache(uint32_t addr); 327 328 /** 329 * @brief Init mmu owner register to make i/d cache use half mmu entries. 330 * 331 * @param None 332 * 333 * @return None 334 */ 335 void Cache_Owner_Init(void); 336 337 /** 338 * @brief Invalidate the cache items for ICache. 339 * Operation will be done CACHE_LINE_SIZE aligned. 340 * If the region is not in ICache addr room, nothing will be done. 341 * Please do not call this function in your SDK application. 342 * 343 * @param uint32_t addr: start address to invalidate 344 * 345 * @param uint32_t items: cache lines to invalidate, items * cache_line_size should not exceed the bus address size(16MB/32MB/64MB) 346 * 347 * @return None 348 */ 349 void Cache_Invalidate_ICache_Items(uint32_t addr, uint32_t items); 350 351 /** 352 * @brief Invalidate the Cache items in the region from ICache or DCache. 353 * If the region is not in Cache addr room, nothing will be done. 354 * Please do not call this function in your SDK application. 355 * 356 * @param uint32_t addr : invalidated region start address. 357 * 358 * @param uint32_t size : invalidated region size. 359 * 360 * @return 0 for success 361 * 1 for invalid argument 362 */ 363 int Cache_Invalidate_Addr(uint32_t addr, uint32_t size); 364 365 /** 366 * @brief Invalidate all cache items in ICache. 367 * Please do not call this function in your SDK application. 368 * 369 * @param None 370 * 371 * @return None 372 */ 373 void Cache_Invalidate_ICache_All(void); 374 375 /** 376 * @brief Mask all buses through ICache and DCache. 377 * Please do not call this function in your SDK application. 378 * 379 * @param None 380 * 381 * @return None 382 */ 383 void Cache_Mask_All(void); 384 385 /** 386 * @brief Suspend ICache auto preload operation, then you can resume it after some ICache operations. 387 * Please do not call this function in your SDK application. 388 * 389 * @param None 390 * 391 * @return uint32_t : 0 for ICache not auto preload before suspend. 392 */ 393 uint32_t Cache_Suspend_ICache_Autoload(void); 394 395 /** 396 * @brief Resume ICache auto preload operation after some ICache operations. 397 * Please do not call this function in your SDK application. 398 * 399 * @param uint32_t autoload : 0 for ICache not auto preload before suspend. 400 * 401 * @return None. 402 */ 403 void Cache_Resume_ICache_Autoload(uint32_t autoload); 404 405 /** 406 * @brief Start an ICache manual preload, will suspend auto preload of ICache. 407 * Please do not call this function in your SDK application. 408 * 409 * @param uint32_t addr : start address of the preload region. 410 * 411 * @param uint32_t size : size of the preload region, should not exceed the size of ICache. 412 * 413 * @param uint32_t order : the preload order, 0 for positive, other for negative 414 * 415 * @return uint32_t : 0 for ICache not auto preload before manual preload. 416 */ 417 uint32_t Cache_Start_ICache_Preload(uint32_t addr, uint32_t size, uint32_t order); 418 419 /** 420 * @brief Return if the ICache manual preload done. 421 * Please do not call this function in your SDK application. 422 * 423 * @param None 424 * 425 * @return uint32_t : 0 for ICache manual preload not done. 426 */ 427 uint32_t Cache_ICache_Preload_Done(void); 428 429 /** 430 * @brief End the ICache manual preload to resume auto preload of ICache. 431 * Please do not call this function in your SDK application. 432 * 433 * @param uint32_t autoload : 0 for ICache not auto preload before manual preload. 434 * 435 * @return None 436 */ 437 void Cache_End_ICache_Preload(uint32_t autoload); 438 439 /** 440 * @brief Config autoload parameters of ICache. 441 * Please do not call this function in your SDK application. 442 * 443 * @param struct autoload_config * config : autoload parameters. 444 * 445 * @return None 446 */ 447 void Cache_Config_ICache_Autoload(const struct autoload_config * config); 448 449 /** 450 * @brief Enable auto preload for ICache. 451 * Please do not call this function in your SDK application. 452 * 453 * @param None 454 * 455 * @return None 456 */ 457 void Cache_Enable_ICache_Autoload(void); 458 459 /** 460 * @brief Disable auto preload for ICache. 461 * Please do not call this function in your SDK application. 462 * 463 * @param None 464 * 465 * @return None 466 */ 467 void Cache_Disable_ICache_Autoload(void); 468 469 /** 470 * @brief Config a group of prelock parameters of ICache. 471 * Please do not call this function in your SDK application. 472 * 473 * @param struct lock_config * config : a group of lock parameters. 474 * 475 * @return None 476 */ 477 478 void Cache_Enable_ICache_PreLock(const struct lock_config *config); 479 480 /** 481 * @brief Disable a group of prelock parameters for ICache. 482 * However, the locked data will not be released. 483 * Please do not call this function in your SDK application. 484 * 485 * @param uint16_t group : 0 for group0, 1 for group1. 486 * 487 * @return None 488 */ 489 void Cache_Disable_ICache_PreLock(uint16_t group); 490 491 /** 492 * @brief Lock the cache items for ICache. 493 * Operation will be done CACHE_LINE_SIZE aligned. 494 * If the region is not in ICache addr room, nothing will be done. 495 * Please do not call this function in your SDK application. 496 * 497 * @param uint32_t addr: start address to lock 498 * 499 * @param uint32_t items: cache lines to lock, items * cache_line_size should not exceed the bus address size(16MB/32MB/64MB) 500 * 501 * @return None 502 */ 503 void Cache_Lock_ICache_Items(uint32_t addr, uint32_t items); 504 505 /** 506 * @brief Unlock the cache items for ICache. 507 * Operation will be done CACHE_LINE_SIZE aligned. 508 * If the region is not in ICache addr room, nothing will be done. 509 * Please do not call this function in your SDK application. 510 * 511 * @param uint32_t addr: start address to unlock 512 * 513 * @param uint32_t items: cache lines to unlock, items * cache_line_size should not exceed the bus address size(16MB/32MB/64MB) 514 * 515 * @return None 516 */ 517 void Cache_Unlock_ICache_Items(uint32_t addr, uint32_t items); 518 519 /** 520 * @brief Lock the cache items in tag memory for ICache or DCache. 521 * Please do not call this function in your SDK application. 522 * 523 * @param uint32_t addr : start address of lock region. 524 * 525 * @param uint32_t size : size of lock region. 526 * 527 * @return 0 for success 528 * 1 for invalid argument 529 */ 530 int Cache_Lock_Addr(uint32_t addr, uint32_t size); 531 532 /** 533 * @brief Unlock the cache items in tag memory for ICache or DCache. 534 * Please do not call this function in your SDK application. 535 * 536 * @param uint32_t addr : start address of unlock region. 537 * 538 * @param uint32_t size : size of unlock region. 539 * 540 * @return 0 for success 541 * 1 for invalid argument 542 */ 543 int Cache_Unlock_Addr(uint32_t addr, uint32_t size); 544 545 /** 546 * @brief Disable ICache access for the cpu. 547 * This operation will make all ICache tag memory invalid, CPU can't access ICache, ICache will keep idle. 548 * Please do not call this function in your SDK application. 549 * 550 * @return uint32_t : auto preload enabled before 551 */ 552 uint32_t Cache_Disable_ICache(void); 553 554 /** 555 * @brief Enable ICache access for the cpu. 556 * Please do not call this function in your SDK application. 557 * 558 * @param uint32_t autoload : ICache will preload then. 559 * 560 * @return None 561 */ 562 void Cache_Enable_ICache(uint32_t autoload); 563 564 /** 565 * @brief Suspend ICache access for the cpu. 566 * The ICache tag memory is still there, CPU can't access ICache, ICache will keep idle. 567 * Please do not change MMU, cache mode or tag memory(tag memory can be changed in some special case). 568 * Please do not call this function in your SDK application. 569 * 570 * @param None 571 * 572 * @return uint32_t : auto preload enabled before 573 */ 574 uint32_t Cache_Suspend_ICache(void); 575 576 /** 577 * @brief Resume ICache access for the cpu. 578 * Please do not call this function in your SDK application. 579 * 580 * @param uint32_t autoload : ICache will preload then. 581 * 582 * @return None 583 */ 584 void Cache_Resume_ICache(uint32_t autoload); 585 586 /** 587 * @brief Get ICache cache line size 588 * 589 * @param None 590 * 591 * @return uint32_t: 16, 32, 64 Byte 592 */ 593 uint32_t Cache_Get_ICache_Line_Size(void); 594 595 /** 596 * @brief Set default mode from boot, 8KB ICache, 16Byte cache line size. 597 * 598 * @param None 599 * 600 * @return None 601 */ 602 void Cache_Set_Default_Mode(void); 603 604 /** 605 * @brief Set default mode from boot, 8KB ICache, 16Byte cache line size. 606 * 607 * @param None 608 * 609 * @return None 610 */ 611 void Cache_Enable_Defalut_ICache_Mode(void); 612 613 /** 614 * @brief Enable freeze for ICache. 615 * Any miss request will be rejected, including cpu miss and preload/autoload miss. 616 * Please do not call this function in your SDK application. 617 * 618 * @param cache_freeze_mode_t mode : 0 for assert busy 1 for assert hit 619 * 620 * @return None 621 */ 622 void Cache_Freeze_ICache_Enable(cache_freeze_mode_t mode); 623 624 /** 625 * @brief Disable freeze for ICache. 626 * Please do not call this function in your SDK application. 627 * 628 * @return None 629 */ 630 void Cache_Freeze_ICache_Disable(void); 631 632 /** 633 * @brief Travel tag memory to run a call back function. 634 * ICache and DCache are suspend when doing this. 635 * The callback will get the parameter tag_group_info, which will include a group of tag memory addresses and cache memory addresses. 636 * Please do not call this function in your SDK application. 637 * 638 * @param struct cache_mode * mode : the cache to check and the cache mode. 639 * 640 * @param uint32_t filter_addr : only the cache lines which may include the filter_address will be returned to the call back function. 641 * 0 for do not filter, all cache lines will be returned. 642 * 643 * @param void (* process)(struct tag_group_info *) : call back function, which may be called many times, a group(the addresses in the group are in the same position in the cache ways) a time. 644 * 645 * @return None 646 */ 647 void Cache_Travel_Tag_Memory(struct cache_mode * mode, uint32_t filter_addr, void (* process)(struct tag_group_info *)); 648 649 /** 650 * @brief Get the virtual address from cache mode, cache tag and the virtual address offset of cache ways. 651 * Please do not call this function in your SDK application. 652 * 653 * @param struct cache_mode * mode : the cache to calculate the virtual address and the cache mode. 654 * 655 * @param uint32_t tag : the tag part fo a tag item, 12-14 bits. 656 * 657 * @param uint32_t addr_offset : the virtual address offset of the cache ways. 658 * 659 * @return uint32_t : the virtual address. 660 */ 661 uint32_t Cache_Get_Virtual_Addr(struct cache_mode *mode, uint32_t tag, uint32_t vaddr_offset); 662 663 /** 664 * @brief Get cache memory block base address. 665 * Please do not call this function in your SDK application. 666 * 667 * @param uint32_t icache : 0 for dcache, other for icache. 668 * 669 * @param uint32_t bank_no : 0 ~ 3 bank. 670 * 671 * @return uint32_t : the cache memory block base address, 0 if the block not used. 672 */ 673 uint32_t Cache_Get_Memory_BaseAddr(uint32_t icache, uint32_t bank_no); 674 675 /** 676 * @brief Get the cache memory address from cache mode, cache memory offset and the virtual address offset of cache ways. 677 * Please do not call this function in your SDK application. 678 * 679 * @param struct cache_mode * mode : the cache to calculate the virtual address and the cache mode. 680 * 681 * @param uint32_t cache_memory_offset : the cache memory offset of the whole cache (ICache or DCache) for the cache line. 682 * 683 * @param uint32_t addr_offset : the virtual address offset of the cache ways. 684 * 685 * @return uint32_t : the virtual address. 686 */ 687 uint32_t Cache_Get_Memory_Addr(struct cache_mode *mode, uint32_t cache_memory_offset, uint32_t vaddr_offset); 688 689 /** 690 * @brief Get the cache memory value by DRAM address. 691 * Please do not call this function in your SDK application. 692 * 693 * @param uint32_t cache_memory_addr : DRAM address for the cache memory, should be 4 byte aligned for IBus address. 694 * 695 * @return uint32_t : the word value of the address. 696 */ 697 uint32_t Cache_Get_Memory_value(uint32_t cache_memory_addr); 698 /** 699 * @} 700 */ 701 702 /** 703 * @brief Get the cache MMU IROM end address. 704 * Please do not call this function in your SDK application. 705 * 706 * @param void 707 * 708 * @return uint32_t : the word value of the address. 709 */ 710 uint32_t Cache_Get_IROM_MMU_End(void); 711 712 /** 713 * @brief Get the cache MMU DROM end address. 714 * Please do not call this function in your SDK application. 715 * 716 * @param void 717 * 718 * @return uint32_t : the word value of the address. 719 */ 720 uint32_t Cache_Get_DROM_MMU_End(void); 721 722 /** 723 * @brief Lock the permission control section configuration. After lock, any 724 * configuration modification will be bypass. Digital reset will clear the lock! 725 * Please do not call this function in your SDK application. 726 * 727 * @param int ibus : 1 for lock ibus pms, 0 for lock dbus pms 728 * 729 * @return None 730 */ 731 void Cache_Pms_Lock(int ibus); 732 733 /** 734 * @brief Set three ibus pms boundary address, which will determine pms reject section and section 1/2. 735 * Please do not call this function in your SDK application. 736 * 737 * @param uint32_t ibus_boundary0_addr : vaddress for split line0 738 * 739 * @param uint32_t ibus_boundary1_addr : vaddress for split line1 740 * 741 * @param uint32_t ibus_boundary2_addr : vaddress for split line2 742 * 743 * @return int : ESP_ROM_ERR_INVALID_ARG for invalid address, 0 for success 744 */ 745 int Cache_Ibus_Pms_Set_Addr(uint32_t ibus_boundary0_addr, uint32_t ibus_boundary1_addr, uint32_t ibus_boundary2_addr); 746 747 /** 748 * @brief Set three ibus pms attribute, which will determine pms in different section and world. 749 * Please do not call this function in your SDK application. 750 * 751 * @param uint32_t ibus_pms_sct2_attr : attr for section2 752 * 753 * @param uint32_t ibus_pms_sct1_attr : attr for section1 754 * 755 * @return None 756 */ 757 void Cache_Ibus_Pms_Set_Attr(uint32_t ibus_pms_sct2_attr, uint32_t ibus_pms_sct1_attr); 758 759 /** 760 * @brief Set three dbus pms boundary address, which will determine pms reject section and section 1/2. 761 * Please do not call this function in your SDK application. 762 * 763 * @param uint32_t dbus_boundary0_addr : vaddress for split line0 764 * 765 * @param uint32_t dbus_boundary1_addr : vaddress for split line1 766 * 767 * @param uint32_t dbus_boundary2_addr : vaddress for split line2 768 * 769 * @return int : ESP_ROM_ERR_INVALID_ARG for invalid address, 0 for success 770 */ 771 int Cache_Dbus_Pms_Set_Addr(uint32_t dbus_boundary0_addr, uint32_t dbus_boundary1_addr, uint32_t dbus_boundary2_addr); 772 773 /** 774 * @brief Set three dbus pms attribute, which will determine pms in different section and world. 775 * Please do not call this function in your SDK application. 776 * 777 * @param uint32_t dbus_pms_sct2_attr : attr for section2 778 * 779 * @param uint32_t dbus_pms_sct1_attr : attr for section1 780 * 781 * @return None 782 */ 783 void Cache_Dbus_Pms_Set_Attr(uint32_t dbus_pms_sct2_attr, uint32_t dbus_pms_sct1_attr); 784 785 /** 786 * @brief Used by SPI flash mmap 787 * 788 */ 789 uint32_t flash_instr_rodata_start_page(uint32_t bus); 790 uint32_t flash_instr_rodata_end_page(uint32_t bus); 791 792 #ifdef __cplusplus 793 } 794 #endif 795 796 #endif /* _ROM_CACHE_H_ */ 797
