1/*
2 * Copyright (c) 2021 Espressif Systems (Shanghai) Co., Ltd.
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6#include <mem.h>
7#include <freq.h>
8#include <zephyr/dt-bindings/adc/adc.h>
9#include <zephyr/dt-bindings/gpio/gpio.h>
10#include <zephyr/dt-bindings/i2c/i2c.h>
11#include <zephyr/dt-bindings/interrupt-controller/esp-esp32c3-intmux.h>
12#include <zephyr/dt-bindings/clock/esp32c3_clock.h>
13#include <dt-bindings/pinctrl/esp32-pinctrl.h>
14
15/ {
16	#address-cells = <1>;
17	#size-cells = <1>;
18
19	aliases {
20		die-temp0 = &coretemp;
21	};
22
23	chosen {
24		zephyr,canbus = &twai;
25		zephyr,entropy = &trng0;
26		zephyr,flash-controller = &flash;
27		zephyr,bt-hci = &esp32_bt_hci;
28	};
29
30	cpus {
31		#address-cells = <1>;
32		#size-cells = <0>;
33
34		cpu0: cpu@0 {
35			device_type = "cpu";
36			compatible = "espressif,riscv", "riscv";
37			riscv,isa = "rv32imc_zicsr";
38			reg = <0>;
39			cpu-power-states = <&light_sleep &deep_sleep>;
40			clock-source = <ESP32_CPU_CLK_SRC_PLL>;
41			clock-frequency = <DT_FREQ_M(160)>;
42			xtal-freq = <DT_FREQ_M(40)>;
43		};
44
45		power-states {
46			light_sleep: light_sleep {
47				compatible = "zephyr,power-state";
48				power-state-name = "standby";
49				min-residency-us = <200>;
50				exit-latency-us = <60>;
51			};
52
53			deep_sleep: deep_sleep {
54				compatible = "zephyr,power-state";
55				power-state-name = "soft-off";
56				min-residency-us = <660>;
57				exit-latency-us = <105>;
58			};
59		};
60	};
61
62	pinctrl: pin-controller {
63		compatible = "espressif,esp32-pinctrl";
64		status = "okay";
65	};
66
67	wifi: wifi {
68		compatible = "espressif,esp32-wifi";
69		status = "disabled";
70	};
71
72	esp32_bt_hci: esp32_bt_hci {
73		compatible = "espressif,esp32-bt-hci";
74		status = "disabled";
75	};
76
77	soc {
78		#address-cells = <1>;
79		#size-cells = <1>;
80		compatible = "simple-bus";
81		ranges;
82
83		sram0: memory@4037c000 {
84			compatible = "zephyr,memory-region", "mmio-sram";
85			reg = <0x4037c000 DT_SIZE_K(16)>;
86			zephyr,memory-region = "SRAM0";
87		};
88
89		sram1: memory@3fc80000 {
90			compatible = "zephyr,memory-region", "mmio-sram";
91			reg = <0x3fc80000 DT_SIZE_K(384)>;
92			zephyr,memory-region = "SRAM1";
93		};
94
95		intc: interrupt-controller@600c2000 {
96			compatible = "espressif,esp32-intc";
97			#address-cells = <0>;
98			#interrupt-cells = <3>;
99			interrupt-controller;
100			reg = <0x600c2000 0x198>;
101			status = "okay";
102		};
103
104		systimer0: systimer@60023000 {
105			compatible = "espressif,esp32-systimer";
106			reg = <0x60023000 0x80>;
107			interrupts = <SYSTIMER_TARGET0_EDGE_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
108			interrupt-parent = <&intc>;
109			status = "okay";
110		};
111
112		rtc: rtc@60008000 {
113			compatible = "espressif,esp32-rtc";
114			reg = <0x60008000 0x1000>;
115			fast-clk-src = <ESP32_RTC_FAST_CLK_SRC_RC_FAST>;
116			slow-clk-src = <ESP32_RTC_SLOW_CLK_SRC_RC_SLOW>;
117			#clock-cells = <1>;
118			status = "okay";
119		};
120
121		xt_wdt: xt_wdt@60008004 {
122			compatible = "espressif,esp32-xt-wdt";
123			reg = <0x60008004 0x4>;
124			clocks = <&rtc ESP32_MODULE_MAX>;
125			interrupts = <RTC_CORE_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
126			interrupt-parent = <&intc>;
127			status = "disabled";
128		};
129
130		rtc_timer: rtc_timer@60008004 {
131			reg = <0x60008004 0xC>;
132			compatible = "espressif,esp32-rtc-timer";
133			clocks = <&rtc ESP32_MODULE_MAX>;
134			interrupts = <RTC_CORE_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
135			interrupt-parent = <&intc>;
136			status = "okay";
137		};
138
139		flash: flash-controller@60002000 {
140			compatible = "espressif,esp32-flash-controller";
141			reg = <0x60002000 0x1000>;
142
143			#address-cells = <1>;
144			#size-cells = <1>;
145
146			flash0: flash@0 {
147				compatible = "soc-nv-flash";
148				erase-block-size = <4096>;
149				write-block-size = <4>;
150				/* Flash size is specified in SOC/SIP dtsi */
151			};
152		};
153
154		gpio0: gpio@60004000 {
155			compatible = "espressif,esp32-gpio";
156			gpio-controller;
157			#gpio-cells = <2>;
158			reg = <0x60004000 0x800>;
159			interrupts = <GPIO_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
160			interrupt-parent = <&intc>;
161			/* Maximum available pins (per port)
162			 * Actual occupied pins are specified
163			 * on part number dtsi level, using
164			 * the `gpio-reserved-ranges` property.
165			 */
166			ngpios = <26>;   /* 0..25 */
167		};
168
169		i2c0: i2c@60013000 {
170			compatible = "espressif,esp32-i2c";
171			#address-cells = <1>;
172			#size-cells = <0>;
173			reg = <0x60013000 0x1000>;
174			interrupts = <I2C_EXT0_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
175			interrupt-parent = <&intc>;
176			clocks = <&rtc ESP32_I2C0_MODULE>;
177			status = "disabled";
178		};
179
180		i2s: i2s@6002d000 {
181			compatible = "espressif,esp32-i2s";
182			#address-cells = <1>;
183			#size-cells = <0>;
184			reg = <0x6002d000 0x1000>;
185			interrupts = <I2S1_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
186			interrupt-parent = <&intc>;
187			clocks = <&rtc ESP32_I2S1_MODULE>;
188			dmas = <&dma 2>, <&dma 3>;
189			dma-names = "rx", "tx";
190			unit = <0>;
191			status = "disabled";
192		};
193
194		uart0: uart@60000000 {
195			compatible = "espressif,esp32-uart";
196			reg = <0x60000000 0x400>;
197			status = "disabled";
198			interrupts = <UART0_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
199			interrupt-parent = <&intc>;
200			clocks = <&rtc ESP32_UART0_MODULE>;
201		};
202
203		uart1: uart@60010000 {
204			compatible = "espressif,esp32-uart";
205			reg = <0x60010000 0x400>;
206			status = "disabled";
207			interrupts = <UART1_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
208			interrupt-parent = <&intc>;
209			clocks = <&rtc ESP32_UART1_MODULE>;
210			current-speed = <115200>;
211		};
212
213		ledc0: ledc@60019000 {
214			compatible = "espressif,esp32-ledc";
215			pwm-controller;
216			#pwm-cells = <3>;
217			reg = <0x60019000 0x1000>;
218			clocks = <&rtc ESP32_LEDC_MODULE>;
219			status = "disabled";
220		};
221
222		usb_serial: uart@60043000 {
223			compatible = "espressif,esp32-usb-serial";
224			reg = <0x60043000 0x400>;
225			status = "disabled";
226			interrupts = <USB_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
227			interrupt-parent = <&intc>;
228			clocks = <&rtc ESP32_USB_MODULE>;
229		};
230
231		timer0: counter@6001f000 {
232			compatible = "espressif,esp32-timer";
233			reg = <0x6001F000 DT_SIZE_K(4)>;
234			clocks = <&rtc ESP32_TIMG0_MODULE>;
235			group = <0>;
236			index = <0>;
237			interrupts = <TG0_T0_LEVEL_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
238			interrupt-parent = <&intc>;
239			status = "disabled";
240		};
241
242		timer1: counter@60020000 {
243			compatible = "espressif,esp32-timer";
244			reg = <0x60020000 DT_SIZE_K(4)>;
245			clocks = <&rtc ESP32_TIMG1_MODULE>;
246			group = <1>;
247			index = <0>;
248			interrupts = <TG1_T0_LEVEL_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
249			interrupt-parent = <&intc>;
250			status = "disabled";
251		};
252
253		trng0: trng@3ff700b0 {
254			compatible = "espressif,esp32-trng";
255			reg = <0x3FF700B0 0x4>;
256			status = "disabled";
257		};
258
259		twai: can@6002b000 {
260			compatible = "espressif,esp32-twai";
261			reg = <0x6002b000 DT_SIZE_K(4)>;
262			interrupts = <TWAI_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
263			interrupt-parent = <&intc>;
264			clocks = <&rtc ESP32_TWAI_MODULE>;
265			status = "disabled";
266		};
267
268		spi2: spi@60024000 {
269			compatible = "espressif,esp32-spi";
270			reg = <0x60024000 DT_SIZE_K(4)>;
271			interrupts = <SPI2_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
272			interrupt-parent = <&intc>;
273			clocks = <&rtc ESP32_SPI2_MODULE>;
274			dma-clk = <ESP32_GDMA_MODULE>;
275			dma-host = <0>;
276			status = "disabled";
277		};
278
279		wdt0: watchdog@6001f048  {
280			compatible = "espressif,esp32-watchdog";
281			reg = <0x6001f048 0x20>;
282			interrupts = <TG0_WDT_LEVEL_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
283			interrupt-parent = <&intc>;
284			clocks = <&rtc ESP32_TIMG0_MODULE>;
285			status = "disabled";
286		};
287
288		wdt1: watchdog@60020048 {
289			compatible = "espressif,esp32-watchdog";
290			reg = <0x60020048 0x20>;
291			interrupts = <TG1_WDT_LEVEL_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
292			interrupt-parent = <&intc>;
293			clocks = <&rtc ESP32_TIMG1_MODULE>;
294			status = "disabled";
295		};
296
297		coretemp: coretemp@60040058 {
298			compatible = "espressif,esp32-temp";
299			friendly-name = "coretemp";
300			reg = <0x60040058 0x4>;
301			status = "disabled";
302		};
303
304		adc0: adc@60040000 {
305			compatible = "espressif,esp32-adc";
306			reg = <0x60040000 4>;
307			unit = <1>;
308			channel-count = <5>;
309			#io-channel-cells = <1>;
310			status = "disabled";
311		};
312
313		adc1: adc@60040004 {
314			compatible = "espressif,esp32-adc";
315			reg = <0x60040004 4>;
316			unit = <2>;
317			channel-count = <2>;
318			#io-channel-cells = <1>;
319			status = "disabled";
320		};
321
322		dma: dma@6003f000 {
323			compatible = "espressif,esp32-gdma";
324			reg = <0x6003f000 DT_SIZE_K(4)>;
325			#dma-cells = <1>;
326			interrupts =
327				<DMA_CH0_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>,
328				<DMA_CH1_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>,
329				<DMA_CH2_INTR_SOURCE IRQ_DEFAULT_PRIORITY 0>;
330			interrupt-parent = <&intc>;
331			clocks = <&rtc ESP32_GDMA_MODULE>;
332			dma-channels = <6>;
333			dma-buf-addr-alignment = <4>;
334			status = "disabled";
335		};
336
337	};
338
339};
340