1 /* 2 * SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #ifndef _ROM_CACHE_H_ 8 #define _ROM_CACHE_H_ 9 10 #include <stdint.h> 11 #include "esp_bit_defs.h" 12 13 #ifdef __cplusplus 14 extern "C" { 15 #endif 16 17 /** \defgroup cache_apis, cache operation related apis 18 * @brief cache apis 19 */ 20 21 /** @addtogroup cache_apis 22 * @{ 23 */ 24 #define MIN_ICACHE_SIZE 16384 25 #define MAX_ICACHE_SIZE 16384 26 #define MIN_ICACHE_WAYS 8 27 #define MAX_ICACHE_WAYS 8 28 #define MAX_CACHE_WAYS 8 29 #define MIN_CACHE_LINE_SIZE 32 30 #define TAG_SIZE 4 31 #define MIN_ICACHE_BANK_NUM 1 32 #define MAX_ICACHE_BANK_NUM 1 33 #define CACHE_MEMORY_BANK_NUM 1 34 #define CACHE_MEMORY_IBANK_SIZE 0x4000 35 36 #define MAX_ITAG_BANK_ITEMS (MAX_ICACHE_SIZE / MAX_ICACHE_BANK_NUM / MIN_CACHE_LINE_SIZE) 37 #define MAX_ITAG_BLOCK_ITEMS (MAX_ICACHE_SIZE / MAX_ICACHE_BANK_NUM / MAX_ICACHE_WAYS / MIN_CACHE_LINE_SIZE) 38 #define MAX_ITAG_BANK_SIZE (MAX_ITAG_BANK_ITEMS * TAG_SIZE) 39 #define MAX_ITAG_BLOCK_SIZE (MAX_ITAG_BLOCK_ITEMS * TAG_SIZE) 40 41 typedef enum { 42 CACHE_DCACHE = 0, 43 CACHE_ICACHE0 = 1, 44 CACHE_ICACHE1 = 2, 45 } cache_t; 46 47 typedef enum { 48 CACHE_MEMORY_INVALID = 0, 49 CACHE_MEMORY_IBANK0 = BIT(0), 50 CACHE_MEMORY_IBANK1 = BIT(1), 51 CACHE_MEMORY_IBANK2 = BIT(2), 52 CACHE_MEMORY_IBANK3 = BIT(3), 53 CACHE_MEMORY_DBANK0 = BIT(0), 54 CACHE_MEMORY_DBANK1 = BIT(1), 55 CACHE_MEMORY_DBANK2 = BIT(2), 56 CACHE_MEMORY_DBANK3 = BIT(3), 57 } cache_array_t; 58 59 #define ICACHE_SIZE_16KB CACHE_SIZE_HALF 60 #define ICACHE_SIZE_32KB CACHE_SIZE_FULL 61 #define DCACHE_SIZE_32KB CACHE_SIZE_HALF 62 #define DCACHE_SIZE_64KB CACHE_SIZE_FULL 63 64 typedef enum { 65 CACHE_SIZE_HALF = 0, /*!< 8KB for icache and dcache */ 66 CACHE_SIZE_FULL = 1, /*!< 16KB for icache and dcache */ 67 } cache_size_t; 68 69 typedef enum { 70 CACHE_4WAYS_ASSOC = 0, /*!< 4 way associated cache */ 71 CACHE_8WAYS_ASSOC = 1, /*!< 8 way associated cache */ 72 } cache_ways_t; 73 74 typedef enum { 75 CACHE_LINE_SIZE_16B = 0, /*!< 16 Byte cache line size */ 76 CACHE_LINE_SIZE_32B = 1, /*!< 32 Byte cache line size */ 77 CACHE_LINE_SIZE_64B = 2, /*!< 64 Byte cache line size */ 78 } cache_line_size_t; 79 80 typedef enum { 81 CACHE_AUTOLOAD_POSITIVE = 0, /*!< cache autoload step is positive */ 82 CACHE_AUTOLOAD_NEGATIVE = 1, /*!< cache autoload step is negative */ 83 } cache_autoload_order_t; 84 85 #define CACHE_AUTOLOAD_STEP(i) ((i) - 1) 86 87 typedef enum { 88 CACHE_AUTOLOAD_MISS_TRIGGER = 0, /*!< autoload only triggered by cache miss */ 89 CACHE_AUTOLOAD_HIT_TRIGGER = 1, /*!< autoload only triggered by cache hit */ 90 CACHE_AUTOLOAD_BOTH_TRIGGER = 2, /*!< autoload triggered both by cache miss and hit */ 91 } cache_autoload_trigger_t; 92 93 typedef enum { 94 CACHE_FREEZE_ACK_BUSY = 0, /*!< in this mode, cache ack busy to CPU if a cache miss happens*/ 95 CACHE_FREEZE_ACK_ERROR = 1, /*!< in this mode, cache ack wrong data to CPU and trigger an error if a cache miss happens */ 96 } cache_freeze_mode_t; 97 98 struct cache_mode { 99 uint32_t cache_size; /*!< cache size in byte */ 100 uint16_t cache_line_size; /*!< cache line size in byte */ 101 uint8_t cache_ways; /*!< cache ways, always 4 */ 102 uint8_t ibus; /*!< the cache index, 0 for dcache, 1 for icache */ 103 }; 104 105 struct icache_tag_item { 106 uint32_t valid:1; /*!< the tag item is valid or not */ 107 uint32_t lock:1; /*!< the cache line is locked or not */ 108 uint32_t fifo_cnt:3; /*!< fifo cnt, 0 ~ 3 for 4 ways cache */ 109 uint32_t tag:13; /*!< the tag is the high part of the cache address, however is only 16MB (8MB Ibus + 8MB Dbus) range, and without low part */ 110 uint32_t reserved:14; 111 }; 112 113 struct autoload_config { 114 uint8_t order; /*!< autoload step is positive or negative */ 115 uint8_t trigger; /*!< autoload trigger */ 116 uint8_t ena0; /*!< autoload region0 enable */ 117 uint8_t ena1; /*!< autoload region1 enable */ 118 uint32_t addr0; /*!< autoload region0 start address */ 119 uint32_t size0; /*!< autoload region0 size */ 120 uint32_t addr1; /*!< autoload region1 start address */ 121 uint32_t size1; /*!< autoload region1 size */ 122 }; 123 124 struct tag_group_info { 125 struct cache_mode mode; /*!< cache and cache mode */ 126 uint32_t filter_addr; /*!< the address that used to generate the struct */ 127 uint32_t vaddr_offset; /*!< virtual address offset of the cache ways */ 128 uint32_t tag_addr[MAX_CACHE_WAYS]; /*!< tag memory address, only [0~mode.ways-1] is valid to use */ 129 uint32_t cache_memory_offset[MAX_CACHE_WAYS]; /*!< cache memory address, only [0~mode.ways-1] is valid to use */ 130 }; 131 132 struct lock_config { 133 uint32_t addr; /*!< manual lock address*/ 134 uint16_t size; /*!< manual lock size*/ 135 uint16_t group; /*!< manual lock group, 0 or 1*/ 136 }; 137 138 struct cache_internal_stub_table { 139 uint32_t (* icache_line_size)(void); 140 uint32_t (* icache_addr)(uint32_t addr); 141 uint32_t (* dcache_addr)(uint32_t addr); 142 void (* invalidate_icache_items)(uint32_t addr, uint32_t items); 143 void (* lock_icache_items)(uint32_t addr, uint32_t items); 144 void (* unlock_icache_items)(uint32_t addr, uint32_t items); 145 uint32_t (* suspend_icache_autoload)(void); 146 void (* resume_icache_autoload)(uint32_t autoload); 147 void (* freeze_icache_enable)(cache_freeze_mode_t mode); 148 void (* freeze_icache_disable)(void); 149 int (* op_addr)(uint32_t start_addr, uint32_t size, uint32_t cache_line_size, uint32_t max_sync_num, void(* cache_Iop)(uint32_t, uint32_t)); 150 }; 151 152 /* Defined in the interface file, default value is rom_default_cache_internal_table */ 153 extern const struct cache_internal_stub_table* rom_cache_internal_table_ptr; 154 155 typedef void (* cache_op_start)(void); 156 typedef void (* cache_op_end)(void); 157 158 typedef struct { 159 cache_op_start start; 160 cache_op_end end; 161 } cache_op_cb_t; 162 163 /* Defined in the interface file, default value is NULL */ 164 extern const cache_op_cb_t* rom_cache_op_cb; 165 166 #define ESP_ROM_ERR_INVALID_ARG 1 167 #define MMU_SET_ADDR_ALIGNED_ERROR 2 168 #define MMU_SET_PASE_SIZE_ERROR 3 169 #define MMU_SET_VADDR_OUT_RANGE 4 170 171 #define CACHE_OP_ICACHE_Y 1 172 #define CACHE_OP_ICACHE_N 0 173 174 /** 175 * @brief Initialise cache mmu, mark all entries as invalid. 176 * Please do not call this function in your SDK application. 177 * 178 * @param None 179 * 180 * @return None 181 */ 182 void Cache_MMU_Init(void); 183 184 /** 185 * @brief Set ICache mmu mapping. 186 * Please do not call this function in your SDK application. 187 * 188 * @param uint32_t ext_ram : DPORT_MMU_ACCESS_FLASH for flash, DPORT_MMU_INVALID for invalid. In 189 * esp32c3, external memory is always flash 190 * 191 * @param uint32_t vaddr : virtual address in CPU address space. 192 * Can be Iram0,Iram1,Irom0,Drom0 and AHB buses address. 193 * Should be aligned by psize. 194 * 195 * @param uint32_t paddr : physical address in external memory. 196 * Should be aligned by psize. 197 * 198 * @param uint32_t psize : page size of ICache, in kilobytes. Should be 64 here. 199 * 200 * @param uint32_t num : pages to be set. 201 * 202 * @param uint32_t fixed : 0 for physical pages grow with virtual pages, other for virtual pages map to same physical page. 203 * 204 * @return uint32_t: error status 205 * 0 : mmu set success 206 * 2 : vaddr or paddr is not aligned 207 * 3 : psize error 208 * 4 : vaddr is out of range 209 */ 210 int Cache_Ibus_MMU_Set(uint32_t ext_ram, uint32_t vaddr, uint32_t paddr, uint32_t psize, uint32_t num, uint32_t fixed); 211 212 /** 213 * @brief Set DCache mmu mapping. 214 * Please do not call this function in your SDK application. 215 * 216 * @param uint32_t ext_ram : DPORT_MMU_ACCESS_FLASH for flash, DPORT_MMU_INVALID for invalid. In 217 * esp32c3, external memory is always flash 218 * 219 * @param uint32_t vaddr : virtual address in CPU address space. 220 * Can be DRam0, DRam1, DRom0, DPort and AHB buses address. 221 * Should be aligned by psize. 222 * 223 * @param uint32_t paddr : physical address in external memory. 224 * Should be aligned by psize. 225 * 226 * @param uint32_t psize : page size of DCache, in kilobytes. Should be 64 here. 227 * 228 * @param uint32_t num : pages to be set. 229 230 * @param uint32_t fixed : 0 for physical pages grow with virtual pages, other for virtual pages map to same physical page. 231 * 232 * @return uint32_t: error status 233 * 0 : mmu set success 234 * 2 : vaddr or paddr is not aligned 235 * 3 : psize error 236 * 4 : vaddr is out of range 237 */ 238 int Cache_Dbus_MMU_Set(uint32_t ext_ram, uint32_t vaddr, uint32_t paddr, uint32_t psize, uint32_t num, uint32_t fixed); 239 240 /** 241 * @brief Count the pages in the bus room address which map to Flash. 242 * Please do not call this function in your SDK application. 243 * 244 * @param uint32_t bus : the bus to count with. 245 * 246 * @param uint32_t * page0_mapped : value should be initial by user, 0 for not mapped, other for mapped count. 247 * 248 * return uint32_t : the number of pages which map to Flash. 249 */ 250 uint32_t Cache_Count_Flash_Pages(uint32_t bus, uint32_t * page0_mapped); 251 252 /** 253 * @brief allocate memory to used by ICache. 254 * Please do not call this function in your SDK application. 255 * 256 * @param cache_array_t icache_low : the data array bank used by icache low part. Due to timing constraint, can only be CACHE_MEMORY_INVALID, CACHE_MEMORY_IBANK0 257 * 258 * return none 259 */ 260 void Cache_Occupy_ICache_MEMORY(cache_array_t icache_low); 261 262 /** 263 * @brief Get cache mode of ICache or DCache. 264 * Please do not call this function in your SDK application. 265 * 266 * @param struct cache_mode * mode : the pointer of cache mode struct, caller should set the icache field 267 * 268 * return none 269 */ 270 void Cache_Get_Mode(struct cache_mode * mode); 271 272 /** 273 * @brief Init Cache for ROM boot, including resetting the Icache, initializing Owner, MMU, setting ICache mode, Enabling ICache, unmasking bus. 274 * 275 * @param None 276 * 277 * @return None 278 */ 279 void ROM_Boot_Cache_Init(void); 280 281 /** 282 * @brief Init mmu owner register to make i/d cache use half mmu entries. 283 * 284 * @param None 285 * 286 * @return None 287 */ 288 void Cache_Owner_Init(void); 289 290 /** 291 * @brief Invalidate the cache items for ICache. 292 * Operation will be done CACHE_LINE_SIZE aligned. 293 * If the region is not in ICache addr room, nothing will be done. 294 * Please do not call this function in your SDK application. 295 * 296 * @param uint32_t addr: start address to invalidate 297 * 298 * @param uint32_t items: cache lines to invalidate, items * cache_line_size should not exceed the bus address size(16MB/32MB/64MB) 299 * 300 * @return None 301 */ 302 void Cache_Invalidate_ICache_Items(uint32_t addr, uint32_t items); 303 304 /** 305 * @brief Invalidate the Cache items in the region from ICache or DCache. 306 * If the region is not in Cache addr room, nothing will be done. 307 * Please do not call this function in your SDK application. 308 * 309 * @param uint32_t addr : invalidated region start address. 310 * 311 * @param uint32_t size : invalidated region size. 312 * 313 * @return 0 for success 314 * 1 for invalid argument 315 */ 316 int Cache_Invalidate_Addr(uint32_t addr, uint32_t size); 317 318 /** 319 * @brief Invalidate all cache items in ICache. 320 * Please do not call this function in your SDK application. 321 * 322 * @param None 323 * 324 * @return None 325 */ 326 void Cache_Invalidate_ICache_All(void); 327 328 /** 329 * @brief Mask all buses through ICache and DCache. 330 * Please do not call this function in your SDK application. 331 * 332 * @param None 333 * 334 * @return None 335 */ 336 void Cache_Mask_All(void); 337 338 /** 339 * @brief Suspend ICache auto preload operation, then you can resume it after some ICache operations. 340 * Please do not call this function in your SDK application. 341 * 342 * @param None 343 * 344 * @return uint32_t : 0 for ICache not auto preload before suspend. 345 */ 346 uint32_t Cache_Suspend_ICache_Autoload(void); 347 348 /** 349 * @brief Resume ICache auto preload operation after some ICache operations. 350 * Please do not call this function in your SDK application. 351 * 352 * @param uint32_t autoload : 0 for ICache not auto preload before suspend. 353 * 354 * @return None. 355 */ 356 void Cache_Resume_ICache_Autoload(uint32_t autoload); 357 358 /** 359 * @brief Start an ICache manual preload, will suspend auto preload of ICache. 360 * Please do not call this function in your SDK application. 361 * 362 * @param uint32_t addr : start address of the preload region. 363 * 364 * @param uint32_t size : size of the preload region, should not exceed the size of ICache. 365 * 366 * @param uint32_t order : the preload order, 0 for positive, other for negative 367 * 368 * @return uint32_t : 0 for ICache not auto preload before manual preload. 369 */ 370 uint32_t Cache_Start_ICache_Preload(uint32_t addr, uint32_t size, uint32_t order); 371 372 /** 373 * @brief Return if the ICache manual preload done. 374 * Please do not call this function in your SDK application. 375 * 376 * @param None 377 * 378 * @return uint32_t : 0 for ICache manual preload not done. 379 */ 380 uint32_t Cache_ICache_Preload_Done(void); 381 382 /** 383 * @brief End the ICache manual preload to resume auto preload of ICache. 384 * Please do not call this function in your SDK application. 385 * 386 * @param uint32_t autoload : 0 for ICache not auto preload before manual preload. 387 * 388 * @return None 389 */ 390 void Cache_End_ICache_Preload(uint32_t autoload); 391 392 /** 393 * @brief Config autoload parameters of ICache. 394 * Please do not call this function in your SDK application. 395 * 396 * @param struct autoload_config * config : autoload parameters. 397 * 398 * @return None 399 */ 400 void Cache_Config_ICache_Autoload(const struct autoload_config * config); 401 402 /** 403 * @brief Enable auto preload for ICache. 404 * Please do not call this function in your SDK application. 405 * 406 * @param None 407 * 408 * @return None 409 */ 410 void Cache_Enable_ICache_Autoload(void); 411 412 /** 413 * @brief Disable auto preload for ICache. 414 * Please do not call this function in your SDK application. 415 * 416 * @param None 417 * 418 * @return None 419 */ 420 void Cache_Disable_ICache_Autoload(void); 421 422 /** 423 * @brief Config a group of prelock parameters of ICache. 424 * Please do not call this function in your SDK application. 425 * 426 * @param struct lock_config * config : a group of lock parameters. 427 * 428 * @return None 429 */ 430 431 void Cache_Enable_ICache_PreLock(const struct lock_config *config); 432 433 /** 434 * @brief Disable a group of prelock parameters for ICache. 435 * However, the locked data will not be released. 436 * Please do not call this function in your SDK application. 437 * 438 * @param uint16_t group : 0 for group0, 1 for group1. 439 * 440 * @return None 441 */ 442 void Cache_Disable_ICache_PreLock(uint16_t group); 443 444 /** 445 * @brief Lock the cache items for ICache. 446 * Operation will be done CACHE_LINE_SIZE aligned. 447 * If the region is not in ICache addr room, nothing will be done. 448 * Please do not call this function in your SDK application. 449 * 450 * @param uint32_t addr: start address to lock 451 * 452 * @param uint32_t items: cache lines to lock, items * cache_line_size should not exceed the bus address size(16MB/32MB/64MB) 453 * 454 * @return None 455 */ 456 void Cache_Lock_ICache_Items(uint32_t addr, uint32_t items); 457 458 /** 459 * @brief Unlock the cache items for ICache. 460 * Operation will be done CACHE_LINE_SIZE aligned. 461 * If the region is not in ICache addr room, nothing will be done. 462 * Please do not call this function in your SDK application. 463 * 464 * @param uint32_t addr: start address to unlock 465 * 466 * @param uint32_t items: cache lines to unlock, items * cache_line_size should not exceed the bus address size(16MB/32MB/64MB) 467 * 468 * @return None 469 */ 470 void Cache_Unlock_ICache_Items(uint32_t addr, uint32_t items); 471 472 /** 473 * @brief Lock the cache items in tag memory for ICache or DCache. 474 * Please do not call this function in your SDK application. 475 * 476 * @param uint32_t addr : start address of lock region. 477 * 478 * @param uint32_t size : size of lock region. 479 * 480 * @return 0 for success 481 * 1 for invalid argument 482 */ 483 int Cache_Lock_Addr(uint32_t addr, uint32_t size); 484 485 /** 486 * @brief Unlock the cache items in tag memory for ICache or DCache. 487 * Please do not call this function in your SDK application. 488 * 489 * @param uint32_t addr : start address of unlock region. 490 * 491 * @param uint32_t size : size of unlock region. 492 * 493 * @return 0 for success 494 * 1 for invalid argument 495 */ 496 int Cache_Unlock_Addr(uint32_t addr, uint32_t size); 497 498 /** 499 * @brief Disable ICache access for the cpu. 500 * This operation will make all ICache tag memory invalid, CPU can't access ICache, ICache will keep idle. 501 * Please do not call this function in your SDK application. 502 * 503 * @return uint32_t : auto preload enabled before 504 */ 505 uint32_t Cache_Disable_ICache(void); 506 507 /** 508 * @brief Enable ICache access for the cpu. 509 * Please do not call this function in your SDK application. 510 * 511 * @param uint32_t autoload : ICache will preload then. 512 * 513 * @return None 514 */ 515 void Cache_Enable_ICache(uint32_t autoload); 516 517 /** 518 * @brief Suspend ICache access for the cpu. 519 * The ICache tag memory is still there, CPU can't access ICache, ICache will keep idle. 520 * Please do not change MMU, cache mode or tag memory(tag memory can be changed in some special case). 521 * Please do not call this function in your SDK application. 522 * 523 * @param None 524 * 525 * @return uint32_t : auto preload enabled before 526 */ 527 uint32_t Cache_Suspend_ICache(void); 528 529 /** 530 * @brief Resume ICache access for the cpu. 531 * Please do not call this function in your SDK application. 532 * 533 * @param uint32_t autoload : ICache will preload then. 534 * 535 * @return None 536 */ 537 void Cache_Resume_ICache(uint32_t autoload); 538 539 /** 540 * @brief Get ICache cache line size 541 * 542 * @param None 543 * 544 * @return uint32_t: 16, 32, 64 Byte 545 */ 546 uint32_t Cache_Get_ICache_Line_Size(void); 547 548 /** 549 * @brief Set default mode from boot, 8KB ICache, 16Byte cache line size. 550 * 551 * @param None 552 * 553 * @return None 554 */ 555 void Cache_Set_Default_Mode(void); 556 557 /** 558 * @brief Set default mode from boot, 8KB ICache, 16Byte cache line size. 559 * 560 * @param None 561 * 562 * @return None 563 */ 564 void Cache_Enable_Defalut_ICache_Mode(void); 565 566 /** 567 * @brief Enable freeze for ICache. 568 * Any miss request will be rejected, including cpu miss and preload/autoload miss. 569 * Please do not call this function in your SDK application. 570 * 571 * @param cache_freeze_mode_t mode : 0 for assert busy 1 for assert hit 572 * 573 * @return None 574 */ 575 void Cache_Freeze_ICache_Enable(cache_freeze_mode_t mode); 576 577 /** 578 * @brief Disable freeze for ICache. 579 * Please do not call this function in your SDK application. 580 * 581 * @return None 582 */ 583 void Cache_Freeze_ICache_Disable(void); 584 585 /** 586 * @brief Travel tag memory to run a call back function. 587 * ICache and DCache are suspend when doing this. 588 * The callback will get the parameter tag_group_info, which will include a group of tag memory addresses and cache memory addresses. 589 * Please do not call this function in your SDK application. 590 * 591 * @param struct cache_mode * mode : the cache to check and the cache mode. 592 * 593 * @param uint32_t filter_addr : only the cache lines which may include the filter_address will be returned to the call back function. 594 * 0 for do not filter, all cache lines will be returned. 595 * 596 * @param void (* process)(struct tag_group_info *) : call back function, which may be called many times, a group(the addresses in the group are in the same position in the cache ways) a time. 597 * 598 * @return None 599 */ 600 void Cache_Travel_Tag_Memory(struct cache_mode * mode, uint32_t filter_addr, void (* process)(struct tag_group_info *)); 601 602 /** 603 * @brief Get the virtual address from cache mode, cache tag and the virtual address offset of cache ways. 604 * Please do not call this function in your SDK application. 605 * 606 * @param struct cache_mode * mode : the cache to calculate the virtual address and the cache mode. 607 * 608 * @param uint32_t tag : the tag part fo a tag item, 12-14 bits. 609 * 610 * @param uint32_t addr_offset : the virtual address offset of the cache ways. 611 * 612 * @return uint32_t : the virtual address. 613 */ 614 uint32_t Cache_Get_Virtual_Addr(struct cache_mode *mode, uint32_t tag, uint32_t vaddr_offset); 615 616 /** 617 * @brief Get cache memory block base address. 618 * Please do not call this function in your SDK application. 619 * 620 * @param uint32_t icache : 0 for dcache, other for icache. 621 * 622 * @param uint32_t bank_no : 0 ~ 3 bank. 623 * 624 * @return uint32_t : the cache memory block base address, 0 if the block not used. 625 */ 626 uint32_t Cache_Get_Memory_BaseAddr(uint32_t icache, uint32_t bank_no); 627 628 /** 629 * @brief Get the cache memory address from cache mode, cache memory offset and the virtual address offset of cache ways. 630 * Please do not call this function in your SDK application. 631 * 632 * @param struct cache_mode * mode : the cache to calculate the virtual address and the cache mode. 633 * 634 * @param uint32_t cache_memory_offset : the cache memory offset of the whole cache (ICache or DCache) for the cache line. 635 * 636 * @param uint32_t addr_offset : the virtual address offset of the cache ways. 637 * 638 * @return uint32_t : the virtual address. 639 */ 640 uint32_t Cache_Get_Memory_Addr(struct cache_mode *mode, uint32_t cache_memory_offset, uint32_t vaddr_offset); 641 642 /** 643 * @brief Get the cache memory value by DRAM address. 644 * Please do not call this function in your SDK application. 645 * 646 * @param uint32_t cache_memory_addr : DRAM address for the cache memory, should be 4 byte aligned for IBus address. 647 * 648 * @return uint32_t : the word value of the address. 649 */ 650 uint32_t Cache_Get_Memory_value(uint32_t cache_memory_addr); 651 /** 652 * @} 653 */ 654 655 /** 656 * @brief Get the cache MMU IROM end address. 657 * Please do not call this function in your SDK application. 658 * 659 * @param void 660 * 661 * @return uint32_t : the word value of the address. 662 */ 663 uint32_t Cache_Get_IROM_MMU_End(void); 664 665 /** 666 * @brief Get the cache MMU DROM end address. 667 * Please do not call this function in your SDK application. 668 * 669 * @param void 670 * 671 * @return uint32_t : the word value of the address. 672 */ 673 uint32_t Cache_Get_DROM_MMU_End(void); 674 675 /** 676 * @brief Configure cache MMU page size according to instruction and rodata size 677 * 678 * @param irom_size The instruction cache MMU page size 679 * @param drom_size The rodata data cache MMU page size 680 */ 681 void Cache_Set_IDROM_MMU_Size(uint32_t irom_size, uint32_t drom_size); 682 683 /** 684 * @brief Lock the permission control section configuration. After lock, any 685 * configuration modification will be bypass. Digital reset will clear the lock! 686 * Please do not call this function in your SDK application. 687 * 688 * @param int ibus : 1 for lock ibus pms, 0 for lock dbus pms 689 * 690 * @return None 691 */ 692 void Cache_Pms_Lock(int ibus); 693 694 /** 695 * @brief Set three ibus pms boundary address, which will determine pms reject section and section 1/2. 696 * Please do not call this function in your SDK application. 697 * 698 * @param uint32_t ibus_boundary0_addr : vaddress for split line0 699 * 700 * @param uint32_t ibus_boundary1_addr : vaddress for split line1 701 * 702 * @param uint32_t ibus_boundary2_addr : vaddress for split line2 703 * 704 * @return int : ESP_ROM_ERR_INVALID_ARG for invalid address, 0 for success 705 */ 706 int Cache_Ibus_Pms_Set_Addr(uint32_t ibus_boundary0_addr, uint32_t ibus_boundary1_addr, uint32_t ibus_boundary2_addr); 707 708 /** 709 * @brief Set three ibus pms attribute, which will determine pms in different section and world. 710 * Please do not call this function in your SDK application. 711 * 712 * @param uint32_t ibus_pms_sct2_attr : attr for section2 713 * 714 * @param uint32_t ibus_pms_sct1_attr : attr for section1 715 * 716 * @return None 717 */ 718 void Cache_Ibus_Pms_Set_Attr(uint32_t ibus_pms_sct2_attr, uint32_t ibus_pms_sct1_attr); 719 720 /** 721 * @brief Set three dbus pms boundary address, which will determine pms reject section and section 1/2. 722 * Please do not call this function in your SDK application. 723 * 724 * @param uint32_t dbus_boundary0_addr : vaddress for split line0 725 * 726 * @param uint32_t dbus_boundary1_addr : vaddress for split line1 727 * 728 * @param uint32_t dbus_boundary2_addr : vaddress for split line2 729 * 730 * @return int : ESP_ROM_ERR_INVALID_ARG for invalid address, 0 for success 731 */ 732 int Cache_Dbus_Pms_Set_Addr(uint32_t dbus_boundary0_addr, uint32_t dbus_boundary1_addr, uint32_t dbus_boundary2_addr); 733 734 /** 735 * @brief Set three dbus pms attribute, which will determine pms in different section and world. 736 * Please do not call this function in your SDK application. 737 * 738 * @param uint32_t dbus_pms_sct2_attr : attr for section2 739 * 740 * @param uint32_t dbus_pms_sct1_attr : attr for section1 741 * 742 * @return None 743 */ 744 void Cache_Dbus_Pms_Set_Attr(uint32_t dbus_pms_sct2_attr, uint32_t dbus_pms_sct1_attr); 745 746 #ifdef __cplusplus 747 } 748 #endif 749 750 #endif /* _ROM_CACHE_H_ */ 751
