1 /*
2 * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #ifndef _ROM_RTC_H_
8 #define _ROM_RTC_H_
9
10 #include "ets_sys.h"
11
12 #include <stdbool.h>
13 #include <stdint.h>
14 #include "esp_assert.h"
15
16 #include "soc/soc.h"
17 #include "soc/rtc_cntl_reg.h"
18 #include "soc/reset_reasons.h"
19
20 #ifdef __cplusplus
21 extern "C" {
22 #endif
23
24 /** \defgroup rtc_apis, rtc registers and memory related apis
25 * @brief rtc apis
26 */
27
28 /** @addtogroup rtc_apis
29 * @{
30 */
31
32 /**************************************************************************************
33 * Note: *
34 * Some Rtc memory and registers are used, in ROM or in internal library. *
35 * Please do not use reserved or used rtc memory or registers. *
36 * *
37 *************************************************************************************
38 * RTC Memory & Store Register usage
39 *************************************************************************************
40 * rtc memory addr type size usage
41 * 0x3f421000(0x50000000) Slow SIZE_CP Co-Processor code/Reset Entry
42 * 0x3f421000+SIZE_CP Slow 8192-SIZE_CP
43 *
44 * 0x3ff80000(0x40070000) Fast 8192 deep sleep entry code
45 *
46 *************************************************************************************
47 * RTC store registers usage
48 * RTC_CNTL_STORE0_REG RTC fix us, high 32 bits
49 * RTC_CNTL_STORE1_REG RTC_SLOW_CLK calibration value
50 * RTC_CNTL_STORE2_REG Boot time, low word
51 * RTC_CNTL_STORE3_REG Boot time, high word
52 * RTC_CNTL_STORE4_REG External XTAL frequency
53 * RTC_CNTL_STORE5_REG APB bus frequency
54 * RTC_CNTL_STORE6_REG rtc reset cause
55 * RTC_CNTL_STORE7_REG RTC fix us, low 32 bits
56 *************************************************************************************
57 *
58 * Since esp32c2 does not support RTC fast mem, so use RTC store regs to record rtc time:
59 *
60 * |------------------------|----------------------------------------|
61 * | RTC_CNTL_STORE0_REG | RTC_CNTL_STORE7_REG |
62 * | rtc_fix_us(MSB) | rtc_fix_us(LSB) |
63 * |------------------------|----------------------------------------|
64 */
65
66 #define RTC_FIX_US_HIGH_REG RTC_CNTL_STORE0_REG
67 #define RTC_SLOW_CLK_CAL_REG RTC_CNTL_STORE1_REG
68 #define RTC_BOOT_TIME_LOW_REG RTC_CNTL_STORE2_REG
69 #define RTC_BOOT_TIME_HIGH_REG RTC_CNTL_STORE3_REG
70 #define RTC_XTAL_FREQ_REG RTC_CNTL_STORE4_REG
71 #define RTC_APB_FREQ_REG RTC_CNTL_STORE5_REG
72 #define RTC_RESET_CAUSE_REG RTC_CNTL_STORE6_REG
73 #define RTC_FIX_US_LOW_REG RTC_CNTL_STORE7_REG
74
75 #define RTC_DISABLE_ROM_LOG ((1 << 0) | (1 << 16)) //!< Disable logging from the ROM code.
76
77 typedef enum {
78 AWAKE = 0, //<CPU ON
79 LIGHT_SLEEP = BIT0, //CPU waiti, PLL ON. We don't need explicitly set this mode.
80 DEEP_SLEEP = BIT1 //CPU OFF, PLL OFF, only specific timer could wake up
81 } SLEEP_MODE;
82
83 typedef enum {
84 NO_MEAN = 0,
85 POWERON_RESET = 1, /**<1, Vbat power on reset*/
86 RTC_SW_SYS_RESET = 3, /**<3, Software reset digital core*/
87 DEEPSLEEP_RESET = 5, /**<3, Deep Sleep reset digital core*/
88 TG0WDT_SYS_RESET = 7, /**<7, Timer Group0 Watch dog reset digital core*/
89 RTCWDT_SYS_RESET = 9, /**<9, RTC Watch dog Reset digital core*/
90 INTRUSION_RESET = 10, /**<10, Instrusion tested to reset CPU*/
91 TG0WDT_CPU_RESET = 11, /**<11, Time Group0 reset CPU*/
92 RTC_SW_CPU_RESET = 12, /**<12, Software reset CPU*/
93 RTCWDT_CPU_RESET = 13, /**<13, RTC Watch dog Reset CPU*/
94 RTCWDT_BROWN_OUT_RESET = 15, /**<15, Reset when the vdd voltage is not stable*/
95 RTCWDT_RTC_RESET = 16, /**<16, RTC Watch dog reset digital core and rtc module*/
96 SUPER_WDT_RESET = 18, /**<11, super watchdog reset digital core and rtc module*/
97 GLITCH_RTC_RESET = 19, /**<19, glitch reset digital core and rtc module*/
98 EFUSE_RESET = 20, /**<20, efuse reset digital core*/
99 JTAG_RESET = 24, /**<24, jtag reset CPU*/
100 } RESET_REASON;
101
102 // Check if the reset reason defined in ROM is compatible with soc/reset_reasons.h
103 ESP_STATIC_ASSERT((soc_reset_reason_t)POWERON_RESET == RESET_REASON_CHIP_POWER_ON, "POWERON_RESET != RESET_REASON_CHIP_POWER_ON");
104 ESP_STATIC_ASSERT((soc_reset_reason_t)RTC_SW_SYS_RESET == RESET_REASON_CORE_SW, "RTC_SW_SYS_RESET != RESET_REASON_CORE_SW");
105 ESP_STATIC_ASSERT((soc_reset_reason_t)DEEPSLEEP_RESET == RESET_REASON_CORE_DEEP_SLEEP, "DEEPSLEEP_RESET != RESET_REASON_CORE_DEEP_SLEEP");
106 ESP_STATIC_ASSERT((soc_reset_reason_t)TG0WDT_SYS_RESET == RESET_REASON_CORE_MWDT0, "TG0WDT_SYS_RESET != RESET_REASON_CORE_MWDT0");
107 ESP_STATIC_ASSERT((soc_reset_reason_t)RTCWDT_SYS_RESET == RESET_REASON_CORE_RTC_WDT, "RTCWDT_SYS_RESET != RESET_REASON_CORE_RTC_WDT");
108 ESP_STATIC_ASSERT((soc_reset_reason_t)TG0WDT_CPU_RESET == RESET_REASON_CPU0_MWDT0, "TG0WDT_CPU_RESET != RESET_REASON_CPU0_MWDT0");
109 ESP_STATIC_ASSERT((soc_reset_reason_t)RTC_SW_CPU_RESET == RESET_REASON_CPU0_SW, "RTC_SW_CPU_RESET != RESET_REASON_CPU0_SW");
110 ESP_STATIC_ASSERT((soc_reset_reason_t)RTCWDT_CPU_RESET == RESET_REASON_CPU0_RTC_WDT, "RTCWDT_CPU_RESET != RESET_REASON_CPU0_RTC_WDT");
111 ESP_STATIC_ASSERT((soc_reset_reason_t)RTCWDT_BROWN_OUT_RESET == RESET_REASON_SYS_BROWN_OUT, "RTCWDT_BROWN_OUT_RESET != RESET_REASON_SYS_BROWN_OUT");
112 ESP_STATIC_ASSERT((soc_reset_reason_t)RTCWDT_RTC_RESET == RESET_REASON_SYS_RTC_WDT, "RTCWDT_RTC_RESET != RESET_REASON_SYS_RTC_WDT");
113 ESP_STATIC_ASSERT((soc_reset_reason_t)SUPER_WDT_RESET == RESET_REASON_SYS_SUPER_WDT, "SUPER_WDT_RESET != RESET_REASON_SYS_SUPER_WDT");
114 ESP_STATIC_ASSERT((soc_reset_reason_t)GLITCH_RTC_RESET == RESET_REASON_SYS_CLK_GLITCH, "GLITCH_RTC_RESET != RESET_REASON_SYS_CLK_GLITCH");
115 ESP_STATIC_ASSERT((soc_reset_reason_t)EFUSE_RESET == RESET_REASON_CORE_EFUSE_CRC, "EFUSE_RESET != RESET_REASON_CORE_EFUSE_CRC");
116 ESP_STATIC_ASSERT((soc_reset_reason_t)JTAG_RESET == RESET_REASON_CPU0_JTAG, "JTAG_RESET != RESET_REASON_CPU0_JTAG");
117
118 typedef enum {
119 NO_SLEEP = 0,
120 EXT_EVENT0_TRIG = BIT0,
121 EXT_EVENT1_TRIG = BIT1,
122 GPIO_TRIG = BIT2,
123 TIMER_EXPIRE = BIT3,
124 SDIO_TRIG = BIT4,
125 MAC_TRIG = BIT5,
126 UART0_TRIG = BIT6,
127 UART1_TRIG = BIT7,
128 SAR_TRIG = BIT9,
129 BT_TRIG = BIT10,
130 RISCV_TRIG = BIT11,
131 XTAL_DEAD_TRIG = BIT12,
132 RISCV_TRAP_TRIG = BIT13
133 } WAKEUP_REASON;
134
135 typedef enum {
136 DISEN_WAKEUP = NO_SLEEP,
137 EXT_EVENT0_TRIG_EN = EXT_EVENT0_TRIG,
138 EXT_EVENT1_TRIG_EN = EXT_EVENT1_TRIG,
139 GPIO_TRIG_EN = GPIO_TRIG,
140 TIMER_EXPIRE_EN = TIMER_EXPIRE,
141 SDIO_TRIG_EN = SDIO_TRIG,
142 MAC_TRIG_EN = MAC_TRIG,
143 UART0_TRIG_EN = UART0_TRIG,
144 UART1_TRIG_EN = UART1_TRIG,
145 SAR_TRIG_EN = SAR_TRIG,
146 BT_TRIG_EN = BT_TRIG,
147 RISCV_TRIG_EN = RISCV_TRIG,
148 XTAL_DEAD_TRIG_EN = XTAL_DEAD_TRIG,
149 RISCV_TRAP_TRIG_EN = RISCV_TRAP_TRIG
150 } WAKEUP_ENABLE;
151
152 /**
153 * @brief Get the reset reason for CPU.
154 *
155 * @param int cpu_no : CPU no.
156 *
157 * @return RESET_REASON
158 */
159 RESET_REASON rtc_get_reset_reason(int cpu_no);
160
161 /**
162 * @brief Get the wakeup cause for CPU.
163 *
164 * @param int cpu_no : CPU no.
165 *
166 * @return WAKEUP_REASON
167 */
168 WAKEUP_REASON rtc_get_wakeup_cause(void);
169
170 /**
171 * @brief Suppress ROM log by setting specific RTC control register.
172 * @note This is not a permanent disable of ROM logging since the RTC register can not retain after chip reset.
173 *
174 * @param None
175 *
176 * @return None
177 */
rtc_suppress_rom_log(void)178 static inline void rtc_suppress_rom_log(void)
179 {
180 /* To disable logging in the ROM, only the least significant bit of the register is used,
181 * but since this register is also used to store the frequency of the main crystal (RTC_XTAL_FREQ_REG),
182 * you need to write to this register in the same format.
183 * Namely, the upper 16 bits and lower should be the same.
184 */
185 REG_SET_BIT(RTC_CNTL_STORE4_REG, RTC_DISABLE_ROM_LOG);
186 }
187
188 /**
189 * @brief Software Reset digital core.
190 *
191 * It is not recommended to use this function in esp-idf, use
192 * esp_restart() instead.
193 *
194 * @param None
195 *
196 * @return None
197 */
198 void software_reset(void);
199
200 /**
201 * @brief Software Reset digital core.
202 *
203 * It is not recommended to use this function in esp-idf, use
204 * esp_restart() instead.
205 *
206 * @param int cpu_no : The CPU to reset, 0 for PRO CPU, 1 for APP CPU.
207 *
208 * @return None
209 */
210 void software_reset_cpu(int cpu_no);
211
212 /**
213 * @}
214 */
215
216 #ifdef __cplusplus
217 }
218 #endif
219
220 #endif /* _ROM_RTC_H_ */
221
