1 /*
2  * SPDX-FileCopyrightText: 2010-2022 Espressif Systems (Shanghai) CO LTD
3  *
4  * SPDX-License-Identifier: Apache-2.0
5  */
6 #pragma once
7 
8 #include "ets_sys.h"
9 
10 #include <stdbool.h>
11 #include <stdint.h>
12 #include "esp_assert.h"
13 
14 #include "soc/soc.h"
15 #include "soc/rtc_cntl_reg.h"
16 #include "soc/reset_reasons.h"
17 
18 #ifdef __cplusplus
19 extern "C" {
20 #endif
21 
22 /** \defgroup rtc_apis, rtc registers and memory related apis
23   * @brief rtc apis
24   */
25 
26 /** @addtogroup rtc_apis
27   * @{
28   */
29 
30 /**************************************************************************************
31   *                                       Note:                                       *
32   *       Some Rtc memory and registers are used, in ROM or in internal library.      *
33   *          Please do not use reserved or used rtc memory or registers.              *
34   *                                                                                   *
35   *************************************************************************************
36   *                          RTC  Memory & Store Register usage
37   *************************************************************************************
38   *     rtc memory addr         type    size            usage
39   *     0x3ff61000(0x50000000)  Slow    SIZE_CP         Co-Processor code/Reset Entry
40   *     0x3ff61000+SIZE_CP      Slow    8192-SIZE_CP
41   *
42   *     0x3ff80000(0x400c0000)  Fast    8192            deep sleep entry code
43   *
44   *************************************************************************************
45   *     RTC store registers     usage
46   *     RTC_CNTL_STORE0_REG     Reserved
47   *     RTC_CNTL_STORE1_REG     RTC_SLOW_CLK calibration value
48   *     RTC_CNTL_STORE2_REG     Boot time, low word
49   *     RTC_CNTL_STORE3_REG     Boot time, high word
50   *     RTC_CNTL_STORE4_REG     External XTAL frequency. The frequency must necessarily be even, otherwise there will be a conflict with the low bit, which is used to disable logs in the ROM code.
51   *     RTC_CNTL_STORE5_REG     APB bus frequency
52   *     RTC_CNTL_STORE6_REG     FAST_RTC_MEMORY_ENTRY
53   *     RTC_CNTL_STORE7_REG     FAST_RTC_MEMORY_CRC
54   *************************************************************************************
55   */
56 
57 // #define MHZ (1000000)
58 
59 #define RTC_SLOW_CLK_CAL_REG    RTC_CNTL_STORE1_REG
60 #define RTC_BOOT_TIME_LOW_REG   RTC_CNTL_STORE2_REG
61 #define RTC_BOOT_TIME_HIGH_REG  RTC_CNTL_STORE3_REG
62 #define RTC_XTAL_FREQ_REG       RTC_CNTL_STORE4_REG
63 #define RTC_APB_FREQ_REG        RTC_CNTL_STORE5_REG
64 #define RTC_ENTRY_ADDR_REG      RTC_CNTL_STORE6_REG
65 #define RTC_RESET_CAUSE_REG     RTC_CNTL_STORE6_REG
66 #define RTC_MEMORY_CRC_REG      RTC_CNTL_STORE7_REG
67 
68 #define RTC_DISABLE_ROM_LOG ((1 << 0) | (1 << 16)) //!< Disable logging from the ROM code.
69 
70 typedef enum {
71     AWAKE = 0,             //<CPU ON
72     LIGHT_SLEEP = BIT0,    //CPU waiti, PLL ON.  We don't need explicitly set this mode.
73     DEEP_SLEEP  = BIT1     //CPU OFF, PLL OFF, only specific timer could wake up
74 } SLEEP_MODE;
75 
76 typedef enum {
77     NO_MEAN                =  0,
78     POWERON_RESET          =  1,    /**<1, Vbat power on reset*/
79     SW_RESET               =  3,    /**<3, Software reset digital core*/
80     OWDT_RESET             =  4,    /**<4, Legacy watch dog reset digital core*/
81     DEEPSLEEP_RESET        =  5,    /**<3, Deep Sleep reset digital core*/
82     SDIO_RESET             =  6,    /**<6, Reset by SLC module, reset digital core*/
83     TG0WDT_SYS_RESET       =  7,    /**<7, Timer Group0 Watch dog reset digital core*/
84     TG1WDT_SYS_RESET       =  8,    /**<8, Timer Group1 Watch dog reset digital core*/
85     RTCWDT_SYS_RESET       =  9,    /**<9, RTC Watch dog Reset digital core*/
86     INTRUSION_RESET        = 10,    /**<10, Instrusion tested to reset CPU*/
87     TGWDT_CPU_RESET        = 11,    /**<11, Time Group reset CPU*/
88     SW_CPU_RESET           = 12,    /**<12, Software reset CPU*/
89     RTCWDT_CPU_RESET       = 13,    /**<13, RTC Watch dog Reset CPU*/
90     EXT_CPU_RESET          = 14,    /**<14, for APP CPU, reseted by PRO CPU*/
91     RTCWDT_BROWN_OUT_RESET = 15,    /**<15, Reset when the vdd voltage is not stable*/
92     RTCWDT_RTC_RESET       = 16     /**<16, RTC Watch dog reset digital core and rtc module*/
93 } RESET_REASON;
94 
95 // Check if the reset reason defined in ROM is compatible with soc/reset_reasons.h
96 ESP_STATIC_ASSERT((soc_reset_reason_t)POWERON_RESET == RESET_REASON_CHIP_POWER_ON, "POWERON_RESET != RESET_REASON_CHIP_POWER_ON");
97 ESP_STATIC_ASSERT((soc_reset_reason_t)SW_RESET == RESET_REASON_CORE_SW, "SW_RESET != RESET_REASON_CORE_SW");
98 ESP_STATIC_ASSERT((soc_reset_reason_t)DEEPSLEEP_RESET == RESET_REASON_CORE_DEEP_SLEEP, "DEEPSLEEP_RESET != RESET_REASON_CORE_DEEP_SLEEP");
99 ESP_STATIC_ASSERT((soc_reset_reason_t)TG0WDT_SYS_RESET == RESET_REASON_CORE_MWDT0, "TG0WDT_SYS_RESET != RESET_REASON_CORE_MWDT0");
100 ESP_STATIC_ASSERT((soc_reset_reason_t)TG1WDT_SYS_RESET == RESET_REASON_CORE_MWDT1, "TG1WDT_SYS_RESET != RESET_REASON_CORE_MWDT1");
101 ESP_STATIC_ASSERT((soc_reset_reason_t)RTCWDT_SYS_RESET == RESET_REASON_CORE_RTC_WDT, "RTCWDT_SYS_RESET != RESET_REASON_CORE_RTC_WDT");
102 ESP_STATIC_ASSERT((soc_reset_reason_t)TGWDT_CPU_RESET == RESET_REASON_CPU0_MWDT0, "TGWDT_CPU_RESET != RESET_REASON_CPU0_MWDT0");
103 ESP_STATIC_ASSERT((soc_reset_reason_t)SW_CPU_RESET == RESET_REASON_CPU0_SW, "SW_CPU_RESET != RESET_REASON_CPU0_SW");
104 ESP_STATIC_ASSERT((soc_reset_reason_t)RTCWDT_CPU_RESET == RESET_REASON_CPU0_RTC_WDT, "RTCWDT_CPU_RESET != RESET_REASON_CPU0_RTC_WDT");
105 ESP_STATIC_ASSERT((soc_reset_reason_t)RTCWDT_BROWN_OUT_RESET == RESET_REASON_SYS_BROWN_OUT, "RTCWDT_BROWN_OUT_RESET != RESET_REASON_SYS_BROWN_OUT");
106 ESP_STATIC_ASSERT((soc_reset_reason_t)RTCWDT_RTC_RESET == RESET_REASON_SYS_RTC_WDT, "RTCWDT_RTC_RESET != RESET_REASON_SYS_RTC_WDT");
107 
108 typedef enum {
109     NO_SLEEP        = 0,
110     EXT_EVENT0_TRIG = BIT0,
111     EXT_EVENT1_TRIG = BIT1,
112     GPIO_TRIG       = BIT2,
113     TIMER_EXPIRE    = BIT3,
114     SDIO_TRIG       = BIT4,
115     MAC_TRIG        = BIT5,
116     UART0_TRIG      = BIT6,
117     UART1_TRIG      = BIT7,
118     TOUCH_TRIG      = BIT8,
119     SAR_TRIG        = BIT9,
120     BT_TRIG         = BIT10
121 } WAKEUP_REASON;
122 
123 typedef enum {
124     DISEN_WAKEUP       = NO_SLEEP,
125     EXT_EVENT0_TRIG_EN = EXT_EVENT0_TRIG,
126     EXT_EVENT1_TRIG_EN = EXT_EVENT1_TRIG,
127     GPIO_TRIG_EN       = GPIO_TRIG,
128     TIMER_EXPIRE_EN    = TIMER_EXPIRE,
129     SDIO_TRIG_EN       = SDIO_TRIG,
130     MAC_TRIG_EN        = MAC_TRIG,
131     UART0_TRIG_EN      = UART0_TRIG,
132     UART1_TRIG_EN      = UART1_TRIG,
133     TOUCH_TRIG_EN      = TOUCH_TRIG,
134     SAR_TRIG_EN        = SAR_TRIG,
135     BT_TRIG_EN         = BT_TRIG
136 } WAKEUP_ENABLE;
137 
138 typedef enum {
139     NO_INT             = 0,
140     WAKEUP_INT         = BIT0,
141     REJECT_INT         = BIT1,
142     SDIO_IDLE_INT      = BIT2,
143     RTC_WDT_INT        = BIT3,
144     RTC_TIME_VALID_INT = BIT4
145 } RTC_INT_REASON;
146 
147 typedef enum {
148     DISEN_INT             = 0,
149     WAKEUP_INT_EN         = WAKEUP_INT,
150     REJECT_INT_EN         = REJECT_INT,
151     SDIO_IDLE_INT_EN      = SDIO_IDLE_INT,
152     RTC_WDT_INT_EN        = RTC_WDT_INT,
153     RTC_TIME_VALID_INT_EN = RTC_TIME_VALID_INT
154 } RTC_INT_EN;
155 
156 /**
157   * @brief  Get the reset reason for CPU.
158   *
159   * @param  int cpu_no : CPU no.
160   *
161   * @return RESET_REASON
162   */
163 RESET_REASON rtc_get_reset_reason(int cpu_no);
164 
165 /**
166   * @brief  Get the wakeup cause for CPU.
167   *
168   * @param  int cpu_no : CPU no.
169   *
170   * @return WAKEUP_REASON
171   */
172 WAKEUP_REASON rtc_get_wakeup_cause(void);
173 
174 /**
175   * @brief Get CRC for Fast RTC Memory.
176   *
177   * @param  uint32_t start_addr : 0 - 0x7ff for Fast RTC Memory.
178   *
179   * @param  uint32_t crc_len : 0 - 0x7ff, 0 for 4 byte, 0x7ff for 0x2000 byte.
180   *
181   * @return uint32_t : CRC32 result
182   */
183 uint32_t calc_rtc_memory_crc(uint32_t start_addr, uint32_t crc_len);
184 
185 /**
186   * @brief Set CRC of Fast RTC memory 0-0x7ff into RTC STORE7.
187   *
188   * @param  None
189   *
190   * @return None
191   */
192 void set_rtc_memory_crc(void);
193 
194 /**
195   * @brief Suppress ROM log by setting specific RTC control register.
196   * @note This is not a permanent disable of ROM logging since the RTC register can not retain after chip reset.
197   *
198   * @param  None
199   *
200   * @return None
201   */
rtc_suppress_rom_log(void)202 static inline void rtc_suppress_rom_log(void)
203 {
204     /* To disable logging in the ROM, only the least significant bit of the register is used,
205      * but since this register is also used to store the frequency of the main crystal (RTC_XTAL_FREQ_REG),
206      * you need to write to this register in the same format.
207      * Namely, the upper 16 bits and lower should be the same.
208      */
209     REG_SET_BIT(RTC_CNTL_STORE4_REG, RTC_DISABLE_ROM_LOG);
210 }
211 
212 /**
213   * @brief Software Reset digital core.
214   *
215   * It is not recommended to use this function in esp-idf, use
216   * esp_restart() instead.
217   *
218   * @param  None
219   *
220   * @return None
221   */
222 void __attribute__((__noreturn__)) software_reset(void);
223 
224 /**
225   * @brief Software Reset digital core.
226   *
227   * It is not recommended to use this function in esp-idf, use
228   * esp_restart() instead.
229   *
230   * @param  int cpu_no : The CPU to reset, 0 for PRO CPU, 1 for APP CPU.
231   *
232   * @return None
233   */
234 void software_reset_cpu(int cpu_no);
235 
236 /**
237   * @}
238   */
239 
240 #ifdef __cplusplus
241 }
242 #endif
243