1 /*
2 * SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #ifndef _ROM_CACHE_H_
8 #define _ROM_CACHE_H_
9
10 #include "esp_attr.h"
11 #if __has_include("dport_access.h")
12 #include "dport_access.h"
13 #else
14 #pragma message("For ESP32 with ECO version < 2, you need to use a DPORT workaround that stalls the other CPU")
15 #define DPORT_STALL_OTHER_CPU_START()
16 #define DPORT_STALL_OTHER_CPU_END()
17 #endif
18
19 #ifdef __cplusplus
20 extern "C" {
21 #endif
22
23 /** \defgroup uart_apis, uart configuration and communication related apis
24 * @brief uart apis
25 */
26
27 /** @addtogroup uart_apis
28 * @{
29 */
30
31 /**
32 * @brief Initialise cache mmu, mark all entries as invalid.
33 * Please do not call this function in your SDK application.
34 *
35 * @param int cpu_no : 0 for PRO cpu, 1 for APP cpu.
36 *
37 * @return None
38 */
39 void mmu_init(int cpu_no);
40
41 /**
42 * @brief Set Flash-Cache mmu mapping.
43 * Please do not call this function in your SDK application.
44 *
45 * @param int cpu_no : CPU number, 0 for PRO cpu, 1 for APP cpu.
46 *
47 * @param int pod : process identifier. Range 0~7.
48 *
49 * @param unsigned int vaddr : virtual address in CPU address space.
50 * Can be IRam0, IRam1, IRom0 and DRom0 memory address.
51 * Should be aligned by psize.
52 *
53 * @param unsigned int paddr : physical address in Flash.
54 * Should be aligned by psize.
55 *
56 * @param int psize : page size of flash, in kilobytes. Should be 64 here.
57 *
58 * @param int num : pages to be set.
59 *
60 * @return unsigned int: error status
61 * 0 : mmu set success
62 * 1 : vaddr or paddr is not aligned
63 * 2 : pid error
64 * 3 : psize error
65 * 4 : mmu table to be written is out of range
66 * 5 : vaddr is out of range
67 */
cache_flash_mmu_set(int cpu_no,int pid,unsigned int vaddr,unsigned int paddr,int psize,int num)68 static inline __attribute__((always_inline)) unsigned int IRAM_ATTR cache_flash_mmu_set(int cpu_no, int pid, unsigned int vaddr, unsigned int paddr, int psize, int num)
69 {
70 extern unsigned int cache_flash_mmu_set_rom(int cpu_no, int pid, unsigned int vaddr, unsigned int paddr, int psize, int num);
71
72 unsigned int ret;
73
74 DPORT_STALL_OTHER_CPU_START();
75 ret = cache_flash_mmu_set_rom(cpu_no, pid, vaddr, paddr, psize, num);
76 DPORT_STALL_OTHER_CPU_END();
77
78 return ret;
79 }
80
81 /**
82 * @brief Set Ext-SRAM-Cache mmu mapping.
83 * Please do not call this function in your SDK application.
84 *
85 * Note that this code lives in IRAM and has a bugfix in respect to the ROM version
86 * of this function (which erroneously refused a vaddr > 2MiB
87 *
88 * @param int cpu_no : CPU number, 0 for PRO cpu, 1 for APP cpu.
89 *
90 * @param int pod : process identifier. Range 0~7.
91 *
92 * @param unsigned int vaddr : virtual address in CPU address space.
93 * Can be IRam0, IRam1, IRom0 and DRom0 memory address.
94 * Should be aligned by psize.
95 *
96 * @param unsigned int paddr : physical address in Ext-SRAM.
97 * Should be aligned by psize.
98 *
99 * @param int psize : page size of flash, in kilobytes. Should be 32 here.
100 *
101 * @param int num : pages to be set.
102 *
103 * @return unsigned int: error status
104 * 0 : mmu set success
105 * 1 : vaddr or paddr is not aligned
106 * 2 : pid error
107 * 3 : psize error
108 * 4 : mmu table to be written is out of range
109 * 5 : vaddr is out of range
110 */
111 unsigned int IRAM_ATTR cache_sram_mmu_set(int cpu_no, int pid, unsigned int vaddr, unsigned int paddr, int psize, int num);
112
113 /**
114 * @brief Initialise cache access for the cpu.
115 * Please do not call this function in your SDK application.
116 *
117 * @param int cpu_no : 0 for PRO cpu, 1 for APP cpu.
118 *
119 * @return None
120 */
Cache_Read_Init(int cpu_no)121 static inline __attribute__((always_inline)) void IRAM_ATTR Cache_Read_Init(int cpu_no)
122 {
123 extern void Cache_Read_Init_rom(int cpu_no);
124 DPORT_STALL_OTHER_CPU_START();
125 Cache_Read_Init_rom(cpu_no);
126 DPORT_STALL_OTHER_CPU_END();
127 }
128
129 /**
130 * @brief Flush the cache value for the cpu.
131 * Please do not call this function in your SDK application.
132 *
133 * @param int cpu_no : 0 for PRO cpu, 1 for APP cpu.
134 *
135 * @return None
136 */
Cache_Flush(int cpu_no)137 static inline __attribute__((always_inline)) void IRAM_ATTR Cache_Flush(int cpu_no)
138 {
139 extern void Cache_Flush_rom(int cpu_no);
140 DPORT_STALL_OTHER_CPU_START();
141 Cache_Flush_rom(cpu_no);
142 DPORT_STALL_OTHER_CPU_END();
143 }
144
145 /**
146 * @brief Disable Cache access for the cpu.
147 * Please do not call this function in your SDK application.
148 *
149 * @param int cpu_no : 0 for PRO cpu, 1 for APP cpu.
150 *
151 * @return None
152 */
Cache_Read_Disable(int cpu_no)153 static inline __attribute__((always_inline)) void IRAM_ATTR Cache_Read_Disable(int cpu_no)
154 {
155 extern void Cache_Read_Disable_rom(int cpu_no);
156 DPORT_STALL_OTHER_CPU_START();
157 Cache_Read_Disable_rom(cpu_no);
158 DPORT_STALL_OTHER_CPU_END();
159 }
160
161 /**
162 * @brief Enable Cache access for the cpu.
163 * Please do not call this function in your SDK application.
164 *
165 * @param int cpu_no : 0 for PRO cpu, 1 for APP cpu.
166 *
167 * @return None
168 */
Cache_Read_Enable(int cpu_no)169 static inline __attribute__((always_inline)) void IRAM_ATTR Cache_Read_Enable(int cpu_no)
170 {
171 extern void Cache_Read_Enable_rom(int cpu_no);
172 DPORT_STALL_OTHER_CPU_START();
173 Cache_Read_Enable_rom(cpu_no);
174 DPORT_STALL_OTHER_CPU_END();
175 }
176
177 /**
178 * @}
179 */
180
181 #ifdef __cplusplus
182 }
183 #endif
184
185 #endif /* _ROM_CACHE_H_ */
186
