1/*
2 * Copyright (c) 2021 Tokita, Hiroshi <tokita.hiroshi@gmail.com>
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <zephyr/toolchain.h>
8#include <zephyr/arch/riscv/csr.h>
9#include <nuclei/nuclei_csr.h>
10
11GTEXT(__nuclei_start)
12SECTION_FUNC(vectors, __nuclei_start)
13	/* Disable Global Interrupt */
14	csrc mstatus, MSTATUS_MIE
15	/* Jump to logical address first to ensure correct operation of RAM region  */
16	la	a0, __nuclei_start
17	li	a1, 1
18	slli	a1, a1, 29
19	bleu	a1, a0, _start0800
20	srli	a1, a1, 2
21	bleu	a1, a0, _start0800
22	la	a0, _start0800
23	add	a0, a0, a1
24	jr	a0
25
26_start0800:
27
28#if defined(CONFIG_RISCV_GP)
29	/* Initialize global pointer */
30	.option push
31	.option norelax
32	la	gp, __global_pointer$
33	.option pop
34#endif
35
36	.option norvc;
37
38	/* Set the the NMI base to share with mtvec by setting CSR_MMISC_CTL */
39	li	t0, 0x200
40	csrs	CSR_MMISC_CTL, t0
41
42	/* Initial the CSR MTVEC for the Trap ane NMI base addr */
43	la	t0, trap_entry
44	csrw	mtvec, t0
45
46	/* Direct Mode: All exceptions set pc to BASE. */
47	csrc	mtvec, 0x3
48
49	/* Disable performance counter */
50	csrsi	mcountinhibit, 0x5
51
52	/* Jump to __reset */
53	tail __reset
54
551:
56	j 1b
57
58.align 6
59trap_entry:
60	tail _isr_wrapper
61