1 /** 2 * @file emac_reva_regs.h 3 * @brief Registers, Bit Masks and Bit Positions for the EMAC_REVA Peripheral Module. 4 */ 5 6 /****************************************************************************** 7 * 8 * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by 9 * Analog Devices, Inc.), 10 * Copyright (C) 2023-2024 Analog Devices, Inc. 11 * 12 * Licensed under the Apache License, Version 2.0 (the "License"); 13 * you may not use this file except in compliance with the License. 14 * You may obtain a copy of the License at 15 * 16 * http://www.apache.org/licenses/LICENSE-2.0 17 * 18 * Unless required by applicable law or agreed to in writing, software 19 * distributed under the License is distributed on an "AS IS" BASIS, 20 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 21 * See the License for the specific language governing permissions and 22 * limitations under the License. 23 * 24 ******************************************************************************/ 25 26 #ifndef _EMAC_REVA_REGS_H_ 27 #define _EMAC_REVA_REGS_H_ 28 29 /* **** Includes **** */ 30 #include <stdint.h> 31 32 #ifdef __cplusplus 33 extern "C" { 34 #endif 35 36 #if defined (__ICCARM__) 37 #pragma system_include 38 #endif 39 40 #if defined (__CC_ARM) 41 #pragma anon_unions 42 #endif 43 /// @cond 44 /* 45 If types are not defined elsewhere (CMSIS) define them here 46 */ 47 #ifndef __IO 48 #define __IO volatile 49 #endif 50 #ifndef __I 51 #define __I volatile const 52 #endif 53 #ifndef __O 54 #define __O volatile 55 #endif 56 #ifndef __R 57 #define __R volatile const 58 #endif 59 /// @endcond 60 61 /* **** Definitions **** */ 62 63 /** 64 * @ingroup emac_reva 65 * @defgroup emac_reva_registers EMAC_REVA_Registers 66 * @brief Registers, Bit Masks and Bit Positions for the EMAC_REVA Peripheral Module. 67 * @details 10/100 Ethernet MAC. 68 */ 69 70 /** 71 * @ingroup emac_reva_registers 72 * Structure type to access the EMAC_REVA Registers. 73 */ 74 typedef struct { 75 __IO uint32_t cn; /**< <tt>\b 0x00:</tt> EMAC_REVA CN Register */ 76 __IO uint32_t cfg; /**< <tt>\b 0x04:</tt> EMAC_REVA CFG Register */ 77 __I uint32_t status; /**< <tt>\b 0x08:</tt> EMAC_REVA STATUS Register */ 78 __R uint32_t rsv_0xc_0x13[2]; 79 __IO uint32_t tx_st; /**< <tt>\b 0x14:</tt> EMAC_REVA TX_ST Register */ 80 __IO uint32_t rxbuf_ptr; /**< <tt>\b 0x18:</tt> EMAC_REVA RXBUF_PTR Register */ 81 __IO uint32_t txbuf_ptr; /**< <tt>\b 0x1C:</tt> EMAC_REVA TXBUF_PTR Register */ 82 __IO uint32_t rx_st; /**< <tt>\b 0x20:</tt> EMAC_REVA RX_ST Register */ 83 __IO uint32_t int_st; /**< <tt>\b 0x24:</tt> EMAC_REVA INT_ST Register */ 84 __O uint32_t int_en; /**< <tt>\b 0x28:</tt> EMAC_REVA INT_EN Register */ 85 __O uint32_t int_dis; /**< <tt>\b 0x2C:</tt> EMAC_REVA INT_DIS Register */ 86 __I uint32_t int_mask; /**< <tt>\b 0x30:</tt> EMAC_REVA INT_MASK Register */ 87 __IO uint32_t phy_mt; /**< <tt>\b 0x34:</tt> EMAC_REVA PHY_MT Register */ 88 __I uint32_t pt; /**< <tt>\b 0x38:</tt> EMAC_REVA PT Register */ 89 __IO uint32_t pfr; /**< <tt>\b 0x3C:</tt> EMAC_REVA PFR Register */ 90 __IO uint32_t ftok; /**< <tt>\b 0x40:</tt> EMAC_REVA FTOK Register */ 91 __IO uint32_t scf; /**< <tt>\b 0x44:</tt> EMAC_REVA SCF Register */ 92 __IO uint32_t mcf; /**< <tt>\b 0x48:</tt> EMAC_REVA MCF Register */ 93 __IO uint32_t frok; /**< <tt>\b 0x4C:</tt> EMAC_REVA FROK Register */ 94 __IO uint32_t fcs_err; /**< <tt>\b 0x50:</tt> EMAC_REVA FCS_ERR Register */ 95 __IO uint32_t algn_err; /**< <tt>\b 0x54:</tt> EMAC_REVA ALGN_ERR Register */ 96 __IO uint32_t dftxf; /**< <tt>\b 0x58:</tt> EMAC_REVA DFTXF Register */ 97 __IO uint32_t lc; /**< <tt>\b 0x5C:</tt> EMAC_REVA LC Register */ 98 __IO uint32_t ec; /**< <tt>\b 0x60:</tt> EMAC_REVA EC Register */ 99 __IO uint32_t tur_err; /**< <tt>\b 0x64:</tt> EMAC_REVA TUR_ERR Register */ 100 __IO uint32_t cs_err; /**< <tt>\b 0x68:</tt> EMAC_REVA CS_ERR Register */ 101 __IO uint32_t rr_err; /**< <tt>\b 0x6C:</tt> EMAC_REVA RR_ERR Register */ 102 __IO uint32_t ror_err; /**< <tt>\b 0x70:</tt> EMAC_REVA ROR_ERR Register */ 103 __IO uint32_t rs_err; /**< <tt>\b 0x74:</tt> EMAC_REVA RS_ERR Register */ 104 __IO uint32_t el_err; /**< <tt>\b 0x78:</tt> EMAC_REVA EL_ERR Register */ 105 __IO uint32_t rj; /**< <tt>\b 0x7C:</tt> EMAC_REVA RJ Register */ 106 __IO uint32_t usf; /**< <tt>\b 0x80:</tt> EMAC_REVA USF Register */ 107 __IO uint32_t sqe_err; /**< <tt>\b 0x84:</tt> EMAC_REVA SQE_ERR Register */ 108 __IO uint32_t rlfm; /**< <tt>\b 0x88:</tt> EMAC_REVA RLFM Register */ 109 __IO uint32_t tpf; /**< <tt>\b 0x8C:</tt> EMAC_REVA TPF Register */ 110 __IO uint32_t hashl; /**< <tt>\b 0x90:</tt> EMAC_REVA HASHL Register */ 111 __IO uint32_t hashh; /**< <tt>\b 0x94:</tt> EMAC_REVA HASHH Register */ 112 __IO uint32_t sa1l; /**< <tt>\b 0x98:</tt> EMAC_REVA SA1L Register */ 113 __IO uint32_t sa1h; /**< <tt>\b 0x9C:</tt> EMAC_REVA SA1H Register */ 114 __IO uint32_t sa2l; /**< <tt>\b 0xA0:</tt> EMAC_REVA SA2L Register */ 115 __IO uint32_t sa2h; /**< <tt>\b 0xA4:</tt> EMAC_REVA SA2H Register */ 116 __IO uint32_t sa3l; /**< <tt>\b 0xA8:</tt> EMAC_REVA SA3L Register */ 117 __IO uint32_t sa3h; /**< <tt>\b 0xAC:</tt> EMAC_REVA SA3H Register */ 118 __IO uint32_t sa4l; /**< <tt>\b 0xB0:</tt> EMAC_REVA SA4L Register */ 119 __IO uint32_t sa4h; /**< <tt>\b 0xB4:</tt> EMAC_REVA SA4H Register */ 120 __IO uint32_t tid_ck; /**< <tt>\b 0xB8:</tt> EMAC_REVA TID_CK Register */ 121 __IO uint32_t tpq; /**< <tt>\b 0xBC:</tt> EMAC_REVA TPQ Register */ 122 __IO uint32_t usrio; /**< <tt>\b 0xC0:</tt> EMAC_REVA USRIO Register */ 123 __IO uint32_t wol; /**< <tt>\b 0xC4:</tt> EMAC_REVA WOL Register */ 124 __R uint32_t rsv_0xc8_0xfb[13]; 125 __I uint32_t rev; /**< <tt>\b 0xFC:</tt> EMAC_REVA REV Register */ 126 } mxc_emac_reva_regs_t; 127 128 /* Register offsets for module EMAC_REVA */ 129 /** 130 * @ingroup emac_reva_registers 131 * @defgroup EMAC_REVA_Register_Offsets Register Offsets 132 * @brief EMAC_REVA Peripheral Register Offsets from the EMAC_REVA Base Peripheral Address. 133 * @{ 134 */ 135 #define MXC_R_EMAC_REVA_CN ((uint32_t)0x00000000UL) /**< Offset from EMAC_REVA Base Address: <tt> 0x0000</tt> */ 136 #define MXC_R_EMAC_REVA_CFG ((uint32_t)0x00000004UL) /**< Offset from EMAC_REVA Base Address: <tt> 0x0004</tt> */ 137 #define MXC_R_EMAC_REVA_STATUS ((uint32_t)0x00000008UL) /**< Offset from EMAC_REVA Base Address: <tt> 0x0008</tt> */ 138 #define MXC_R_EMAC_REVA_TX_ST ((uint32_t)0x00000014UL) /**< Offset from EMAC_REVA Base Address: <tt> 0x0014</tt> */ 139 #define MXC_R_EMAC_REVA_RXBUF_PTR ((uint32_t)0x00000018UL) /**< Offset from EMAC_REVA Base Address: <tt> 0x0018</tt> */ 140 #define MXC_R_EMAC_REVA_TXBUF_PTR ((uint32_t)0x0000001CUL) /**< Offset from EMAC_REVA Base Address: <tt> 0x001C</tt> */ 141 #define MXC_R_EMAC_REVA_RX_ST ((uint32_t)0x00000020UL) /**< Offset from EMAC_REVA Base Address: <tt> 0x0020</tt> */ 142 #define MXC_R_EMAC_REVA_INT_ST ((uint32_t)0x00000024UL) /**< Offset from EMAC_REVA Base Address: <tt> 0x0024</tt> */ 143 #define MXC_R_EMAC_REVA_INT_EN ((uint32_t)0x00000028UL) /**< Offset from EMAC_REVA Base Address: <tt> 0x0028</tt> */ 144 #define MXC_R_EMAC_REVA_INT_DIS ((uint32_t)0x0000002CUL) /**< Offset from EMAC_REVA Base Address: <tt> 0x002C</tt> */ 145 #define MXC_R_EMAC_REVA_INT_MASK ((uint32_t)0x00000030UL) /**< Offset from EMAC_REVA Base Address: <tt> 0x0030</tt> */ 146 #define MXC_R_EMAC_REVA_PHY_MT ((uint32_t)0x00000034UL) /**< Offset from EMAC_REVA Base Address: <tt> 0x0034</tt> */ 147 #define MXC_R_EMAC_REVA_PT ((uint32_t)0x00000038UL) /**< Offset from EMAC_REVA Base Address: <tt> 0x0038</tt> */ 148 #define MXC_R_EMAC_REVA_PFR ((uint32_t)0x0000003CUL) /**< Offset from EMAC_REVA Base Address: <tt> 0x003C</tt> */ 149 #define MXC_R_EMAC_REVA_FTOK ((uint32_t)0x00000040UL) /**< Offset from EMAC_REVA Base Address: <tt> 0x0040</tt> */ 150 #define MXC_R_EMAC_REVA_SCF ((uint32_t)0x00000044UL) /**< Offset from EMAC_REVA Base Address: <tt> 0x0044</tt> */ 151 #define MXC_R_EMAC_REVA_MCF ((uint32_t)0x00000048UL) /**< Offset from EMAC_REVA Base Address: <tt> 0x0048</tt> */ 152 #define MXC_R_EMAC_REVA_FROK ((uint32_t)0x0000004CUL) /**< Offset from EMAC_REVA Base Address: <tt> 0x004C</tt> */ 153 #define MXC_R_EMAC_REVA_FCS_ERR ((uint32_t)0x00000050UL) /**< Offset from EMAC_REVA Base Address: <tt> 0x0050</tt> */ 154 #define MXC_R_EMAC_REVA_ALGN_ERR ((uint32_t)0x00000054UL) /**< Offset from EMAC_REVA Base Address: <tt> 0x0054</tt> */ 155 #define MXC_R_EMAC_REVA_DFTXF ((uint32_t)0x00000058UL) /**< Offset from EMAC_REVA Base Address: <tt> 0x0058</tt> */ 156 #define MXC_R_EMAC_REVA_LC ((uint32_t)0x0000005CUL) /**< Offset from EMAC_REVA Base Address: <tt> 0x005C</tt> */ 157 #define MXC_R_EMAC_REVA_EC ((uint32_t)0x00000060UL) /**< Offset from EMAC_REVA Base Address: <tt> 0x0060</tt> */ 158 #define MXC_R_EMAC_REVA_TUR_ERR ((uint32_t)0x00000064UL) /**< Offset from EMAC_REVA Base Address: <tt> 0x0064</tt> */ 159 #define MXC_R_EMAC_REVA_CS_ERR ((uint32_t)0x00000068UL) /**< Offset from EMAC_REVA Base Address: <tt> 0x0068</tt> */ 160 #define MXC_R_EMAC_REVA_RR_ERR ((uint32_t)0x0000006CUL) /**< Offset from EMAC_REVA Base Address: <tt> 0x006C</tt> */ 161 #define MXC_R_EMAC_REVA_ROR_ERR ((uint32_t)0x00000070UL) /**< Offset from EMAC_REVA Base Address: <tt> 0x0070</tt> */ 162 #define MXC_R_EMAC_REVA_RS_ERR ((uint32_t)0x00000074UL) /**< Offset from EMAC_REVA Base Address: <tt> 0x0074</tt> */ 163 #define MXC_R_EMAC_REVA_EL_ERR ((uint32_t)0x00000078UL) /**< Offset from EMAC_REVA Base Address: <tt> 0x0078</tt> */ 164 #define MXC_R_EMAC_REVA_RJ ((uint32_t)0x0000007CUL) /**< Offset from EMAC_REVA Base Address: <tt> 0x007C</tt> */ 165 #define MXC_R_EMAC_REVA_USF ((uint32_t)0x00000080UL) /**< Offset from EMAC_REVA Base Address: <tt> 0x0080</tt> */ 166 #define MXC_R_EMAC_REVA_SQE_ERR ((uint32_t)0x00000084UL) /**< Offset from EMAC_REVA Base Address: <tt> 0x0084</tt> */ 167 #define MXC_R_EMAC_REVA_RLFM ((uint32_t)0x00000088UL) /**< Offset from EMAC_REVA Base Address: <tt> 0x0088</tt> */ 168 #define MXC_R_EMAC_REVA_TPF ((uint32_t)0x0000008CUL) /**< Offset from EMAC_REVA Base Address: <tt> 0x008C</tt> */ 169 #define MXC_R_EMAC_REVA_HASHL ((uint32_t)0x00000090UL) /**< Offset from EMAC_REVA Base Address: <tt> 0x0090</tt> */ 170 #define MXC_R_EMAC_REVA_HASHH ((uint32_t)0x00000094UL) /**< Offset from EMAC_REVA Base Address: <tt> 0x0094</tt> */ 171 #define MXC_R_EMAC_REVA_SA1L ((uint32_t)0x00000098UL) /**< Offset from EMAC_REVA Base Address: <tt> 0x0098</tt> */ 172 #define MXC_R_EMAC_REVA_SA1H ((uint32_t)0x0000009CUL) /**< Offset from EMAC_REVA Base Address: <tt> 0x009C</tt> */ 173 #define MXC_R_EMAC_REVA_SA2L ((uint32_t)0x000000A0UL) /**< Offset from EMAC_REVA Base Address: <tt> 0x00A0</tt> */ 174 #define MXC_R_EMAC_REVA_SA2H ((uint32_t)0x000000A4UL) /**< Offset from EMAC_REVA Base Address: <tt> 0x00A4</tt> */ 175 #define MXC_R_EMAC_REVA_SA3L ((uint32_t)0x000000A8UL) /**< Offset from EMAC_REVA Base Address: <tt> 0x00A8</tt> */ 176 #define MXC_R_EMAC_REVA_SA3H ((uint32_t)0x000000ACUL) /**< Offset from EMAC_REVA Base Address: <tt> 0x00AC</tt> */ 177 #define MXC_R_EMAC_REVA_SA4L ((uint32_t)0x000000B0UL) /**< Offset from EMAC_REVA Base Address: <tt> 0x00B0</tt> */ 178 #define MXC_R_EMAC_REVA_SA4H ((uint32_t)0x000000B4UL) /**< Offset from EMAC_REVA Base Address: <tt> 0x00B4</tt> */ 179 #define MXC_R_EMAC_REVA_TID_CK ((uint32_t)0x000000B8UL) /**< Offset from EMAC_REVA Base Address: <tt> 0x00B8</tt> */ 180 #define MXC_R_EMAC_REVA_TPQ ((uint32_t)0x000000BCUL) /**< Offset from EMAC_REVA Base Address: <tt> 0x00BC</tt> */ 181 #define MXC_R_EMAC_REVA_USRIO ((uint32_t)0x000000C0UL) /**< Offset from EMAC_REVA Base Address: <tt> 0x00C0</tt> */ 182 #define MXC_R_EMAC_REVA_WOL ((uint32_t)0x000000C4UL) /**< Offset from EMAC_REVA Base Address: <tt> 0x00C4</tt> */ 183 #define MXC_R_EMAC_REVA_REV ((uint32_t)0x000000FCUL) /**< Offset from EMAC_REVA Base Address: <tt> 0x00FC</tt> */ 184 /**@} end of group emac_reva_registers */ 185 186 /** 187 * @ingroup emac_reva_registers 188 * @defgroup EMAC_REVA_CN EMAC_REVA_CN 189 * @brief Network Control Register. 190 * @{ 191 */ 192 #define MXC_F_EMAC_REVA_CN_LB_POS 0 /**< CN_LB Position */ 193 #define MXC_F_EMAC_REVA_CN_LB ((uint32_t)(0x1UL << MXC_F_EMAC_REVA_CN_LB_POS)) /**< CN_LB Mask */ 194 195 #define MXC_F_EMAC_REVA_CN_LBL_POS 1 /**< CN_LBL Position */ 196 #define MXC_F_EMAC_REVA_CN_LBL ((uint32_t)(0x1UL << MXC_F_EMAC_REVA_CN_LBL_POS)) /**< CN_LBL Mask */ 197 198 #define MXC_F_EMAC_REVA_CN_RXEN_POS 2 /**< CN_RXEN Position */ 199 #define MXC_F_EMAC_REVA_CN_RXEN ((uint32_t)(0x1UL << MXC_F_EMAC_REVA_CN_RXEN_POS)) /**< CN_RXEN Mask */ 200 201 #define MXC_F_EMAC_REVA_CN_TXEN_POS 3 /**< CN_TXEN Position */ 202 #define MXC_F_EMAC_REVA_CN_TXEN ((uint32_t)(0x1UL << MXC_F_EMAC_REVA_CN_TXEN_POS)) /**< CN_TXEN Mask */ 203 204 #define MXC_F_EMAC_REVA_CN_MPEN_POS 4 /**< CN_MPEN Position */ 205 #define MXC_F_EMAC_REVA_CN_MPEN ((uint32_t)(0x1UL << MXC_F_EMAC_REVA_CN_MPEN_POS)) /**< CN_MPEN Mask */ 206 207 #define MXC_F_EMAC_REVA_CN_CLST_POS 5 /**< CN_CLST Position */ 208 #define MXC_F_EMAC_REVA_CN_CLST ((uint32_t)(0x1UL << MXC_F_EMAC_REVA_CN_CLST_POS)) /**< CN_CLST Mask */ 209 210 #define MXC_F_EMAC_REVA_CN_INCST_POS 6 /**< CN_INCST Position */ 211 #define MXC_F_EMAC_REVA_CN_INCST ((uint32_t)(0x1UL << MXC_F_EMAC_REVA_CN_INCST_POS)) /**< CN_INCST Mask */ 212 213 #define MXC_F_EMAC_REVA_CN_WREN_POS 7 /**< CN_WREN Position */ 214 #define MXC_F_EMAC_REVA_CN_WREN ((uint32_t)(0x1UL << MXC_F_EMAC_REVA_CN_WREN_POS)) /**< CN_WREN Mask */ 215 216 #define MXC_F_EMAC_REVA_CN_BP_POS 8 /**< CN_BP Position */ 217 #define MXC_F_EMAC_REVA_CN_BP ((uint32_t)(0x1UL << MXC_F_EMAC_REVA_CN_BP_POS)) /**< CN_BP Mask */ 218 219 #define MXC_F_EMAC_REVA_CN_TXSTART_POS 9 /**< CN_TXSTART Position */ 220 #define MXC_F_EMAC_REVA_CN_TXSTART ((uint32_t)(0x1UL << MXC_F_EMAC_REVA_CN_TXSTART_POS)) /**< CN_TXSTART Mask */ 221 222 #define MXC_F_EMAC_REVA_CN_TXHALT_POS 10 /**< CN_TXHALT Position */ 223 #define MXC_F_EMAC_REVA_CN_TXHALT ((uint32_t)(0x1UL << MXC_F_EMAC_REVA_CN_TXHALT_POS)) /**< CN_TXHALT Mask */ 224 225 #define MXC_F_EMAC_REVA_CN_TXPF_POS 11 /**< CN_TXPF Position */ 226 #define MXC_F_EMAC_REVA_CN_TXPF ((uint32_t)(0x1UL << MXC_F_EMAC_REVA_CN_TXPF_POS)) /**< CN_TXPF Mask */ 227 228 #define MXC_F_EMAC_REVA_CN_TXZQPF_POS 12 /**< CN_TXZQPF Position */ 229 #define MXC_F_EMAC_REVA_CN_TXZQPF ((uint32_t)(0x1UL << MXC_F_EMAC_REVA_CN_TXZQPF_POS)) /**< CN_TXZQPF Mask */ 230 231 /**@} end of group EMAC_REVA_CN_Register */ 232 233 /** 234 * @ingroup emac_reva_registers 235 * @defgroup EMAC_REVA_CFG EMAC_REVA_CFG 236 * @brief Network Configuration Register. 237 * @{ 238 */ 239 #define MXC_F_EMAC_REVA_CFG_SPD_POS 0 /**< CFG_SPD Position */ 240 #define MXC_F_EMAC_REVA_CFG_SPD ((uint32_t)(0x1UL << MXC_F_EMAC_REVA_CFG_SPD_POS)) /**< CFG_SPD Mask */ 241 242 #define MXC_F_EMAC_REVA_CFG_FULLDPLX_POS 1 /**< CFG_FULLDPLX Position */ 243 #define MXC_F_EMAC_REVA_CFG_FULLDPLX ((uint32_t)(0x1UL << MXC_F_EMAC_REVA_CFG_FULLDPLX_POS)) /**< CFG_FULLDPLX Mask */ 244 245 #define MXC_F_EMAC_REVA_CFG_BITRATE_POS 2 /**< CFG_BITRATE Position */ 246 #define MXC_F_EMAC_REVA_CFG_BITRATE ((uint32_t)(0x1UL << MXC_F_EMAC_REVA_CFG_BITRATE_POS)) /**< CFG_BITRATE Mask */ 247 248 #define MXC_F_EMAC_REVA_CFG_JUMBOFR_POS 3 /**< CFG_JUMBOFR Position */ 249 #define MXC_F_EMAC_REVA_CFG_JUMBOFR ((uint32_t)(0x1UL << MXC_F_EMAC_REVA_CFG_JUMBOFR_POS)) /**< CFG_JUMBOFR Mask */ 250 251 #define MXC_F_EMAC_REVA_CFG_COPYAF_POS 4 /**< CFG_COPYAF Position */ 252 #define MXC_F_EMAC_REVA_CFG_COPYAF ((uint32_t)(0x1UL << MXC_F_EMAC_REVA_CFG_COPYAF_POS)) /**< CFG_COPYAF Mask */ 253 254 #define MXC_F_EMAC_REVA_CFG_NOBC_POS 5 /**< CFG_NOBC Position */ 255 #define MXC_F_EMAC_REVA_CFG_NOBC ((uint32_t)(0x1UL << MXC_F_EMAC_REVA_CFG_NOBC_POS)) /**< CFG_NOBC Mask */ 256 257 #define MXC_F_EMAC_REVA_CFG_MHEN_POS 6 /**< CFG_MHEN Position */ 258 #define MXC_F_EMAC_REVA_CFG_MHEN ((uint32_t)(0x1UL << MXC_F_EMAC_REVA_CFG_MHEN_POS)) /**< CFG_MHEN Mask */ 259 260 #define MXC_F_EMAC_REVA_CFG_UHEN_POS 7 /**< CFG_UHEN Position */ 261 #define MXC_F_EMAC_REVA_CFG_UHEN ((uint32_t)(0x1UL << MXC_F_EMAC_REVA_CFG_UHEN_POS)) /**< CFG_UHEN Mask */ 262 263 #define MXC_F_EMAC_REVA_CFG_RXFR_POS 8 /**< CFG_RXFR Position */ 264 #define MXC_F_EMAC_REVA_CFG_RXFR ((uint32_t)(0x1UL << MXC_F_EMAC_REVA_CFG_RXFR_POS)) /**< CFG_RXFR Mask */ 265 266 #define MXC_F_EMAC_REVA_CFG_EAE_POS 9 /**< CFG_EAE Position */ 267 #define MXC_F_EMAC_REVA_CFG_EAE ((uint32_t)(0x1UL << MXC_F_EMAC_REVA_CFG_EAE_POS)) /**< CFG_EAE Mask */ 268 269 #define MXC_F_EMAC_REVA_CFG_MDCCLK_POS 10 /**< CFG_MDCCLK Position */ 270 #define MXC_F_EMAC_REVA_CFG_MDCCLK ((uint32_t)(0x3UL << MXC_F_EMAC_REVA_CFG_MDCCLK_POS)) /**< CFG_MDCCLK Mask */ 271 #define MXC_V_EMAC_REVA_CFG_MDCCLK_DIV8 ((uint32_t)0x0UL) /**< CFG_MDCCLK_DIV8 Value */ 272 #define MXC_S_EMAC_REVA_CFG_MDCCLK_DIV8 (MXC_V_EMAC_REVA_CFG_MDCCLK_DIV8 << MXC_F_EMAC_REVA_CFG_MDCCLK_POS) /**< CFG_MDCCLK_DIV8 Setting */ 273 #define MXC_V_EMAC_REVA_CFG_MDCCLK_DIV16 ((uint32_t)0x1UL) /**< CFG_MDCCLK_DIV16 Value */ 274 #define MXC_S_EMAC_REVA_CFG_MDCCLK_DIV16 (MXC_V_EMAC_REVA_CFG_MDCCLK_DIV16 << MXC_F_EMAC_REVA_CFG_MDCCLK_POS) /**< CFG_MDCCLK_DIV16 Setting */ 275 #define MXC_V_EMAC_REVA_CFG_MDCCLK_DIV32 ((uint32_t)0x2UL) /**< CFG_MDCCLK_DIV32 Value */ 276 #define MXC_S_EMAC_REVA_CFG_MDCCLK_DIV32 (MXC_V_EMAC_REVA_CFG_MDCCLK_DIV32 << MXC_F_EMAC_REVA_CFG_MDCCLK_POS) /**< CFG_MDCCLK_DIV32 Setting */ 277 #define MXC_V_EMAC_REVA_CFG_MDCCLK_DIV64 ((uint32_t)0x3UL) /**< CFG_MDCCLK_DIV64 Value */ 278 #define MXC_S_EMAC_REVA_CFG_MDCCLK_DIV64 (MXC_V_EMAC_REVA_CFG_MDCCLK_DIV64 << MXC_F_EMAC_REVA_CFG_MDCCLK_POS) /**< CFG_MDCCLK_DIV64 Setting */ 279 280 #define MXC_F_EMAC_REVA_CFG_TXPF_POS 11 /**< CFG_TXPF Position */ 281 #define MXC_F_EMAC_REVA_CFG_TXPF ((uint32_t)(0x1UL << MXC_F_EMAC_REVA_CFG_TXPF_POS)) /**< CFG_TXPF Mask */ 282 283 #define MXC_F_EMAC_REVA_CFG_RTTST_POS 12 /**< CFG_RTTST Position */ 284 #define MXC_F_EMAC_REVA_CFG_RTTST ((uint32_t)(0x1UL << MXC_F_EMAC_REVA_CFG_RTTST_POS)) /**< CFG_RTTST Mask */ 285 286 #define MXC_F_EMAC_REVA_CFG_PAUSEEN_POS 13 /**< CFG_PAUSEEN Position */ 287 #define MXC_F_EMAC_REVA_CFG_PAUSEEN ((uint32_t)(0x1UL << MXC_F_EMAC_REVA_CFG_PAUSEEN_POS)) /**< CFG_PAUSEEN Mask */ 288 289 #define MXC_F_EMAC_REVA_CFG_RXBUFFOFS_POS 14 /**< CFG_RXBUFFOFS Position */ 290 #define MXC_F_EMAC_REVA_CFG_RXBUFFOFS ((uint32_t)(0x3UL << MXC_F_EMAC_REVA_CFG_RXBUFFOFS_POS)) /**< CFG_RXBUFFOFS Mask */ 291 292 #define MXC_F_EMAC_REVA_CFG_RXLFCEN_POS 16 /**< CFG_RXLFCEN Position */ 293 #define MXC_F_EMAC_REVA_CFG_RXLFCEN ((uint32_t)(0x1UL << MXC_F_EMAC_REVA_CFG_RXLFCEN_POS)) /**< CFG_RXLFCEN Mask */ 294 295 #define MXC_F_EMAC_REVA_CFG_DCRXFCS_POS 17 /**< CFG_DCRXFCS Position */ 296 #define MXC_F_EMAC_REVA_CFG_DCRXFCS ((uint32_t)(0x1UL << MXC_F_EMAC_REVA_CFG_DCRXFCS_POS)) /**< CFG_DCRXFCS Mask */ 297 298 #define MXC_F_EMAC_REVA_CFG_HDPLXRXEN_POS 18 /**< CFG_HDPLXRXEN Position */ 299 #define MXC_F_EMAC_REVA_CFG_HDPLXRXEN ((uint32_t)(0x1UL << MXC_F_EMAC_REVA_CFG_HDPLXRXEN_POS)) /**< CFG_HDPLXRXEN Mask */ 300 301 #define MXC_F_EMAC_REVA_CFG_IGNRXFCS_POS 19 /**< CFG_IGNRXFCS Position */ 302 #define MXC_F_EMAC_REVA_CFG_IGNRXFCS ((uint32_t)(0x1UL << MXC_F_EMAC_REVA_CFG_IGNRXFCS_POS)) /**< CFG_IGNRXFCS Mask */ 303 304 /**@} end of group EMAC_REVA_CFG_Register */ 305 306 /** 307 * @ingroup emac_reva_registers 308 * @defgroup EMAC_REVA_STATUS EMAC_REVA_STATUS 309 * @brief Network Status Register. 310 * @{ 311 */ 312 #define MXC_F_EMAC_REVA_STATUS_LINK_POS 0 /**< STATUS_LINK Position */ 313 #define MXC_F_EMAC_REVA_STATUS_LINK ((uint32_t)(0x1UL << MXC_F_EMAC_REVA_STATUS_LINK_POS)) /**< STATUS_LINK Mask */ 314 315 #define MXC_F_EMAC_REVA_STATUS_MDIO_POS 1 /**< STATUS_MDIO Position */ 316 #define MXC_F_EMAC_REVA_STATUS_MDIO ((uint32_t)(0x1UL << MXC_F_EMAC_REVA_STATUS_MDIO_POS)) /**< STATUS_MDIO Mask */ 317 318 #define MXC_F_EMAC_REVA_STATUS_IDLE_POS 2 /**< STATUS_IDLE Position */ 319 #define MXC_F_EMAC_REVA_STATUS_IDLE ((uint32_t)(0x1UL << MXC_F_EMAC_REVA_STATUS_IDLE_POS)) /**< STATUS_IDLE Mask */ 320 321 /**@} end of group EMAC_REVA_STATUS_Register */ 322 323 /** 324 * @ingroup emac_reva_registers 325 * @defgroup EMAC_REVA_TX_ST EMAC_REVA_TX_ST 326 * @brief Transmit Status Register. 327 * @{ 328 */ 329 #define MXC_F_EMAC_REVA_TX_ST_UBR_POS 0 /**< TX_ST_UBR Position */ 330 #define MXC_F_EMAC_REVA_TX_ST_UBR ((uint32_t)(0x1UL << MXC_F_EMAC_REVA_TX_ST_UBR_POS)) /**< TX_ST_UBR Mask */ 331 332 #define MXC_F_EMAC_REVA_TX_ST_COLS_POS 1 /**< TX_ST_COLS Position */ 333 #define MXC_F_EMAC_REVA_TX_ST_COLS ((uint32_t)(0x1UL << MXC_F_EMAC_REVA_TX_ST_COLS_POS)) /**< TX_ST_COLS Mask */ 334 335 #define MXC_F_EMAC_REVA_TX_ST_RTYLIM_POS 2 /**< TX_ST_RTYLIM Position */ 336 #define MXC_F_EMAC_REVA_TX_ST_RTYLIM ((uint32_t)(0x1UL << MXC_F_EMAC_REVA_TX_ST_RTYLIM_POS)) /**< TX_ST_RTYLIM Mask */ 337 338 #define MXC_F_EMAC_REVA_TX_ST_TXGO_POS 3 /**< TX_ST_TXGO Position */ 339 #define MXC_F_EMAC_REVA_TX_ST_TXGO ((uint32_t)(0x1UL << MXC_F_EMAC_REVA_TX_ST_TXGO_POS)) /**< TX_ST_TXGO Mask */ 340 341 #define MXC_F_EMAC_REVA_TX_ST_BEMF_POS 4 /**< TX_ST_BEMF Position */ 342 #define MXC_F_EMAC_REVA_TX_ST_BEMF ((uint32_t)(0x1UL << MXC_F_EMAC_REVA_TX_ST_BEMF_POS)) /**< TX_ST_BEMF Mask */ 343 344 #define MXC_F_EMAC_REVA_TX_ST_TXCMPL_POS 5 /**< TX_ST_TXCMPL Position */ 345 #define MXC_F_EMAC_REVA_TX_ST_TXCMPL ((uint32_t)(0x1UL << MXC_F_EMAC_REVA_TX_ST_TXCMPL_POS)) /**< TX_ST_TXCMPL Mask */ 346 347 #define MXC_F_EMAC_REVA_TX_ST_TXUR_POS 6 /**< TX_ST_TXUR Position */ 348 #define MXC_F_EMAC_REVA_TX_ST_TXUR ((uint32_t)(0x1UL << MXC_F_EMAC_REVA_TX_ST_TXUR_POS)) /**< TX_ST_TXUR Mask */ 349 350 /**@} end of group EMAC_REVA_TX_ST_Register */ 351 352 /** 353 * @ingroup emac_reva_registers 354 * @defgroup EMAC_REVA_RXBUF_PTR EMAC_REVA_RXBUF_PTR 355 * @brief Receive Buffer Queue Pointer Register. 356 * @{ 357 */ 358 #define MXC_F_EMAC_REVA_RXBUF_PTR_RXBUF_POS 2 /**< RXBUF_PTR_RXBUF Position */ 359 #define MXC_F_EMAC_REVA_RXBUF_PTR_RXBUF ((uint32_t)(0x3FFFFFFFUL << MXC_F_EMAC_REVA_RXBUF_PTR_RXBUF_POS)) /**< RXBUF_PTR_RXBUF Mask */ 360 361 /**@} end of group EMAC_REVA_RXBUF_PTR_Register */ 362 363 /** 364 * @ingroup emac_reva_registers 365 * @defgroup EMAC_REVA_TXBUF_PTR EMAC_REVA_TXBUF_PTR 366 * @brief Transmit Buffer Queue Pointer Register. 367 * @{ 368 */ 369 #define MXC_F_EMAC_REVA_TXBUF_PTR_TXBUF_POS 2 /**< TXBUF_PTR_TXBUF Position */ 370 #define MXC_F_EMAC_REVA_TXBUF_PTR_TXBUF ((uint32_t)(0x3FFFFFFFUL << MXC_F_EMAC_REVA_TXBUF_PTR_TXBUF_POS)) /**< TXBUF_PTR_TXBUF Mask */ 371 372 /**@} end of group EMAC_REVA_TXBUF_PTR_Register */ 373 374 /** 375 * @ingroup emac_reva_registers 376 * @defgroup EMAC_REVA_RX_ST EMAC_REVA_RX_ST 377 * @brief Receive Status Register. 378 * @{ 379 */ 380 #define MXC_F_EMAC_REVA_RX_ST_BNA_POS 0 /**< RX_ST_BNA Position */ 381 #define MXC_F_EMAC_REVA_RX_ST_BNA ((uint32_t)(0x1UL << MXC_F_EMAC_REVA_RX_ST_BNA_POS)) /**< RX_ST_BNA Mask */ 382 383 #define MXC_F_EMAC_REVA_RX_ST_FR_POS 1 /**< RX_ST_FR Position */ 384 #define MXC_F_EMAC_REVA_RX_ST_FR ((uint32_t)(0x1UL << MXC_F_EMAC_REVA_RX_ST_FR_POS)) /**< RX_ST_FR Mask */ 385 386 #define MXC_F_EMAC_REVA_RX_ST_RXOR_POS 2 /**< RX_ST_RXOR Position */ 387 #define MXC_F_EMAC_REVA_RX_ST_RXOR ((uint32_t)(0x1UL << MXC_F_EMAC_REVA_RX_ST_RXOR_POS)) /**< RX_ST_RXOR Mask */ 388 389 /**@} end of group EMAC_REVA_RX_ST_Register */ 390 391 /** 392 * @ingroup emac_reva_registers 393 * @defgroup EMAC_REVA_INT_ST EMAC_REVA_INT_ST 394 * @brief Interrupt Status Register. 395 * @{ 396 */ 397 #define MXC_F_EMAC_REVA_INT_ST_MPS_POS 0 /**< INT_ST_MPS Position */ 398 #define MXC_F_EMAC_REVA_INT_ST_MPS ((uint32_t)(0x1UL << MXC_F_EMAC_REVA_INT_ST_MPS_POS)) /**< INT_ST_MPS Mask */ 399 400 #define MXC_F_EMAC_REVA_INT_ST_RXCMPL_POS 1 /**< INT_ST_RXCMPL Position */ 401 #define MXC_F_EMAC_REVA_INT_ST_RXCMPL ((uint32_t)(0x1UL << MXC_F_EMAC_REVA_INT_ST_RXCMPL_POS)) /**< INT_ST_RXCMPL Mask */ 402 403 #define MXC_F_EMAC_REVA_INT_ST_RXUBR_POS 2 /**< INT_ST_RXUBR Position */ 404 #define MXC_F_EMAC_REVA_INT_ST_RXUBR ((uint32_t)(0x1UL << MXC_F_EMAC_REVA_INT_ST_RXUBR_POS)) /**< INT_ST_RXUBR Mask */ 405 406 #define MXC_F_EMAC_REVA_INT_ST_TXUBR_POS 3 /**< INT_ST_TXUBR Position */ 407 #define MXC_F_EMAC_REVA_INT_ST_TXUBR ((uint32_t)(0x1UL << MXC_F_EMAC_REVA_INT_ST_TXUBR_POS)) /**< INT_ST_TXUBR Mask */ 408 409 #define MXC_F_EMAC_REVA_INT_ST_TXUR_POS 4 /**< INT_ST_TXUR Position */ 410 #define MXC_F_EMAC_REVA_INT_ST_TXUR ((uint32_t)(0x1UL << MXC_F_EMAC_REVA_INT_ST_TXUR_POS)) /**< INT_ST_TXUR Mask */ 411 412 #define MXC_F_EMAC_REVA_INT_ST_RLE_POS 5 /**< INT_ST_RLE Position */ 413 #define MXC_F_EMAC_REVA_INT_ST_RLE ((uint32_t)(0x1UL << MXC_F_EMAC_REVA_INT_ST_RLE_POS)) /**< INT_ST_RLE Mask */ 414 415 #define MXC_F_EMAC_REVA_INT_ST_TXERR_POS 6 /**< INT_ST_TXERR Position */ 416 #define MXC_F_EMAC_REVA_INT_ST_TXERR ((uint32_t)(0x1UL << MXC_F_EMAC_REVA_INT_ST_TXERR_POS)) /**< INT_ST_TXERR Mask */ 417 418 #define MXC_F_EMAC_REVA_INT_ST_TXCMPL_POS 7 /**< INT_ST_TXCMPL Position */ 419 #define MXC_F_EMAC_REVA_INT_ST_TXCMPL ((uint32_t)(0x1UL << MXC_F_EMAC_REVA_INT_ST_TXCMPL_POS)) /**< INT_ST_TXCMPL Mask */ 420 421 #define MXC_F_EMAC_REVA_INT_ST_LC_POS 9 /**< INT_ST_LC Position */ 422 #define MXC_F_EMAC_REVA_INT_ST_LC ((uint32_t)(0x1UL << MXC_F_EMAC_REVA_INT_ST_LC_POS)) /**< INT_ST_LC Mask */ 423 424 #define MXC_F_EMAC_REVA_INT_ST_RXOR_POS 10 /**< INT_ST_RXOR Position */ 425 #define MXC_F_EMAC_REVA_INT_ST_RXOR ((uint32_t)(0x1UL << MXC_F_EMAC_REVA_INT_ST_RXOR_POS)) /**< INT_ST_RXOR Mask */ 426 427 #define MXC_F_EMAC_REVA_INT_ST_HRESPNO_POS 11 /**< INT_ST_HRESPNO Position */ 428 #define MXC_F_EMAC_REVA_INT_ST_HRESPNO ((uint32_t)(0x1UL << MXC_F_EMAC_REVA_INT_ST_HRESPNO_POS)) /**< INT_ST_HRESPNO Mask */ 429 430 #define MXC_F_EMAC_REVA_INT_ST_PPR_POS 12 /**< INT_ST_PPR Position */ 431 #define MXC_F_EMAC_REVA_INT_ST_PPR ((uint32_t)(0x1UL << MXC_F_EMAC_REVA_INT_ST_PPR_POS)) /**< INT_ST_PPR Mask */ 432 433 #define MXC_F_EMAC_REVA_INT_ST_PTZ_POS 13 /**< INT_ST_PTZ Position */ 434 #define MXC_F_EMAC_REVA_INT_ST_PTZ ((uint32_t)(0x1UL << MXC_F_EMAC_REVA_INT_ST_PTZ_POS)) /**< INT_ST_PTZ Mask */ 435 436 /**@} end of group EMAC_REVA_INT_ST_Register */ 437 438 /** 439 * @ingroup emac_reva_registers 440 * @defgroup EMAC_REVA_INT_EN EMAC_REVA_INT_EN 441 * @brief Interrupt Enable Register. 442 * @{ 443 */ 444 #define MXC_F_EMAC_REVA_INT_EN_MPS_POS 0 /**< INT_EN_MPS Position */ 445 #define MXC_F_EMAC_REVA_INT_EN_MPS ((uint32_t)(0x1UL << MXC_F_EMAC_REVA_INT_EN_MPS_POS)) /**< INT_EN_MPS Mask */ 446 447 #define MXC_F_EMAC_REVA_INT_EN_RXCMPL_POS 1 /**< INT_EN_RXCMPL Position */ 448 #define MXC_F_EMAC_REVA_INT_EN_RXCMPL ((uint32_t)(0x1UL << MXC_F_EMAC_REVA_INT_EN_RXCMPL_POS)) /**< INT_EN_RXCMPL Mask */ 449 450 #define MXC_F_EMAC_REVA_INT_EN_RXUBR_POS 2 /**< INT_EN_RXUBR Position */ 451 #define MXC_F_EMAC_REVA_INT_EN_RXUBR ((uint32_t)(0x1UL << MXC_F_EMAC_REVA_INT_EN_RXUBR_POS)) /**< INT_EN_RXUBR Mask */ 452 453 #define MXC_F_EMAC_REVA_INT_EN_TXUBR_POS 3 /**< INT_EN_TXUBR Position */ 454 #define MXC_F_EMAC_REVA_INT_EN_TXUBR ((uint32_t)(0x1UL << MXC_F_EMAC_REVA_INT_EN_TXUBR_POS)) /**< INT_EN_TXUBR Mask */ 455 456 #define MXC_F_EMAC_REVA_INT_EN_TXUR_POS 4 /**< INT_EN_TXUR Position */ 457 #define MXC_F_EMAC_REVA_INT_EN_TXUR ((uint32_t)(0x1UL << MXC_F_EMAC_REVA_INT_EN_TXUR_POS)) /**< INT_EN_TXUR Mask */ 458 459 #define MXC_F_EMAC_REVA_INT_EN_RLE_POS 5 /**< INT_EN_RLE Position */ 460 #define MXC_F_EMAC_REVA_INT_EN_RLE ((uint32_t)(0x1UL << MXC_F_EMAC_REVA_INT_EN_RLE_POS)) /**< INT_EN_RLE Mask */ 461 462 #define MXC_F_EMAC_REVA_INT_EN_TXERR_POS 6 /**< INT_EN_TXERR Position */ 463 #define MXC_F_EMAC_REVA_INT_EN_TXERR ((uint32_t)(0x1UL << MXC_F_EMAC_REVA_INT_EN_TXERR_POS)) /**< INT_EN_TXERR Mask */ 464 465 #define MXC_F_EMAC_REVA_INT_EN_TXCMPL_POS 7 /**< INT_EN_TXCMPL Position */ 466 #define MXC_F_EMAC_REVA_INT_EN_TXCMPL ((uint32_t)(0x1UL << MXC_F_EMAC_REVA_INT_EN_TXCMPL_POS)) /**< INT_EN_TXCMPL Mask */ 467 468 #define MXC_F_EMAC_REVA_INT_EN_LC_POS 9 /**< INT_EN_LC Position */ 469 #define MXC_F_EMAC_REVA_INT_EN_LC ((uint32_t)(0x1UL << MXC_F_EMAC_REVA_INT_EN_LC_POS)) /**< INT_EN_LC Mask */ 470 471 #define MXC_F_EMAC_REVA_INT_EN_RXOR_POS 10 /**< INT_EN_RXOR Position */ 472 #define MXC_F_EMAC_REVA_INT_EN_RXOR ((uint32_t)(0x1UL << MXC_F_EMAC_REVA_INT_EN_RXOR_POS)) /**< INT_EN_RXOR Mask */ 473 474 #define MXC_F_EMAC_REVA_INT_EN_HRESPNO_POS 11 /**< INT_EN_HRESPNO Position */ 475 #define MXC_F_EMAC_REVA_INT_EN_HRESPNO ((uint32_t)(0x1UL << MXC_F_EMAC_REVA_INT_EN_HRESPNO_POS)) /**< INT_EN_HRESPNO Mask */ 476 477 #define MXC_F_EMAC_REVA_INT_EN_PPR_POS 12 /**< INT_EN_PPR Position */ 478 #define MXC_F_EMAC_REVA_INT_EN_PPR ((uint32_t)(0x1UL << MXC_F_EMAC_REVA_INT_EN_PPR_POS)) /**< INT_EN_PPR Mask */ 479 480 #define MXC_F_EMAC_REVA_INT_EN_PTZ_POS 13 /**< INT_EN_PTZ Position */ 481 #define MXC_F_EMAC_REVA_INT_EN_PTZ ((uint32_t)(0x1UL << MXC_F_EMAC_REVA_INT_EN_PTZ_POS)) /**< INT_EN_PTZ Mask */ 482 483 /**@} end of group EMAC_REVA_INT_EN_Register */ 484 485 /** 486 * @ingroup emac_reva_registers 487 * @defgroup EMAC_REVA_INT_DIS EMAC_REVA_INT_DIS 488 * @brief Interrupt Disable Register. 489 * @{ 490 */ 491 #define MXC_F_EMAC_REVA_INT_DIS_MPS_POS 0 /**< INT_DIS_MPS Position */ 492 #define MXC_F_EMAC_REVA_INT_DIS_MPS ((uint32_t)(0x1UL << MXC_F_EMAC_REVA_INT_DIS_MPS_POS)) /**< INT_DIS_MPS Mask */ 493 494 #define MXC_F_EMAC_REVA_INT_DIS_RXCMPL_POS 1 /**< INT_DIS_RXCMPL Position */ 495 #define MXC_F_EMAC_REVA_INT_DIS_RXCMPL ((uint32_t)(0x1UL << MXC_F_EMAC_REVA_INT_DIS_RXCMPL_POS)) /**< INT_DIS_RXCMPL Mask */ 496 497 #define MXC_F_EMAC_REVA_INT_DIS_RXUBR_POS 2 /**< INT_DIS_RXUBR Position */ 498 #define MXC_F_EMAC_REVA_INT_DIS_RXUBR ((uint32_t)(0x1UL << MXC_F_EMAC_REVA_INT_DIS_RXUBR_POS)) /**< INT_DIS_RXUBR Mask */ 499 500 #define MXC_F_EMAC_REVA_INT_DIS_TXUBR_POS 3 /**< INT_DIS_TXUBR Position */ 501 #define MXC_F_EMAC_REVA_INT_DIS_TXUBR ((uint32_t)(0x1UL << MXC_F_EMAC_REVA_INT_DIS_TXUBR_POS)) /**< INT_DIS_TXUBR Mask */ 502 503 #define MXC_F_EMAC_REVA_INT_DIS_TXUR_POS 4 /**< INT_DIS_TXUR Position */ 504 #define MXC_F_EMAC_REVA_INT_DIS_TXUR ((uint32_t)(0x1UL << MXC_F_EMAC_REVA_INT_DIS_TXUR_POS)) /**< INT_DIS_TXUR Mask */ 505 506 #define MXC_F_EMAC_REVA_INT_DIS_RLE_POS 5 /**< INT_DIS_RLE Position */ 507 #define MXC_F_EMAC_REVA_INT_DIS_RLE ((uint32_t)(0x1UL << MXC_F_EMAC_REVA_INT_DIS_RLE_POS)) /**< INT_DIS_RLE Mask */ 508 509 #define MXC_F_EMAC_REVA_INT_DIS_TXERR_POS 6 /**< INT_DIS_TXERR Position */ 510 #define MXC_F_EMAC_REVA_INT_DIS_TXERR ((uint32_t)(0x1UL << MXC_F_EMAC_REVA_INT_DIS_TXERR_POS)) /**< INT_DIS_TXERR Mask */ 511 512 #define MXC_F_EMAC_REVA_INT_DIS_TXCMPL_POS 7 /**< INT_DIS_TXCMPL Position */ 513 #define MXC_F_EMAC_REVA_INT_DIS_TXCMPL ((uint32_t)(0x1UL << MXC_F_EMAC_REVA_INT_DIS_TXCMPL_POS)) /**< INT_DIS_TXCMPL Mask */ 514 515 #define MXC_F_EMAC_REVA_INT_DIS_LC_POS 9 /**< INT_DIS_LC Position */ 516 #define MXC_F_EMAC_REVA_INT_DIS_LC ((uint32_t)(0x1UL << MXC_F_EMAC_REVA_INT_DIS_LC_POS)) /**< INT_DIS_LC Mask */ 517 518 #define MXC_F_EMAC_REVA_INT_DIS_RXOR_POS 10 /**< INT_DIS_RXOR Position */ 519 #define MXC_F_EMAC_REVA_INT_DIS_RXOR ((uint32_t)(0x1UL << MXC_F_EMAC_REVA_INT_DIS_RXOR_POS)) /**< INT_DIS_RXOR Mask */ 520 521 #define MXC_F_EMAC_REVA_INT_DIS_HRESPNO_POS 11 /**< INT_DIS_HRESPNO Position */ 522 #define MXC_F_EMAC_REVA_INT_DIS_HRESPNO ((uint32_t)(0x1UL << MXC_F_EMAC_REVA_INT_DIS_HRESPNO_POS)) /**< INT_DIS_HRESPNO Mask */ 523 524 #define MXC_F_EMAC_REVA_INT_DIS_PPR_POS 12 /**< INT_DIS_PPR Position */ 525 #define MXC_F_EMAC_REVA_INT_DIS_PPR ((uint32_t)(0x1UL << MXC_F_EMAC_REVA_INT_DIS_PPR_POS)) /**< INT_DIS_PPR Mask */ 526 527 #define MXC_F_EMAC_REVA_INT_DIS_PTZ_POS 13 /**< INT_DIS_PTZ Position */ 528 #define MXC_F_EMAC_REVA_INT_DIS_PTZ ((uint32_t)(0x1UL << MXC_F_EMAC_REVA_INT_DIS_PTZ_POS)) /**< INT_DIS_PTZ Mask */ 529 530 /**@} end of group EMAC_REVA_INT_DIS_Register */ 531 532 /** 533 * @ingroup emac_reva_registers 534 * @defgroup EMAC_REVA_INT_MASK EMAC_REVA_INT_MASK 535 * @brief Interrupt Mask Register. 536 * @{ 537 */ 538 #define MXC_F_EMAC_REVA_INT_MASK_MPS_POS 0 /**< INT_MASK_MPS Position */ 539 #define MXC_F_EMAC_REVA_INT_MASK_MPS ((uint32_t)(0x1UL << MXC_F_EMAC_REVA_INT_MASK_MPS_POS)) /**< INT_MASK_MPS Mask */ 540 541 #define MXC_F_EMAC_REVA_INT_MASK_RXCMPL_POS 1 /**< INT_MASK_RXCMPL Position */ 542 #define MXC_F_EMAC_REVA_INT_MASK_RXCMPL ((uint32_t)(0x1UL << MXC_F_EMAC_REVA_INT_MASK_RXCMPL_POS)) /**< INT_MASK_RXCMPL Mask */ 543 544 #define MXC_F_EMAC_REVA_INT_MASK_RXUBR_POS 2 /**< INT_MASK_RXUBR Position */ 545 #define MXC_F_EMAC_REVA_INT_MASK_RXUBR ((uint32_t)(0x1UL << MXC_F_EMAC_REVA_INT_MASK_RXUBR_POS)) /**< INT_MASK_RXUBR Mask */ 546 547 #define MXC_F_EMAC_REVA_INT_MASK_TXUBR_POS 3 /**< INT_MASK_TXUBR Position */ 548 #define MXC_F_EMAC_REVA_INT_MASK_TXUBR ((uint32_t)(0x1UL << MXC_F_EMAC_REVA_INT_MASK_TXUBR_POS)) /**< INT_MASK_TXUBR Mask */ 549 550 #define MXC_F_EMAC_REVA_INT_MASK_TXUR_POS 4 /**< INT_MASK_TXUR Position */ 551 #define MXC_F_EMAC_REVA_INT_MASK_TXUR ((uint32_t)(0x1UL << MXC_F_EMAC_REVA_INT_MASK_TXUR_POS)) /**< INT_MASK_TXUR Mask */ 552 553 #define MXC_F_EMAC_REVA_INT_MASK_RLE_POS 5 /**< INT_MASK_RLE Position */ 554 #define MXC_F_EMAC_REVA_INT_MASK_RLE ((uint32_t)(0x1UL << MXC_F_EMAC_REVA_INT_MASK_RLE_POS)) /**< INT_MASK_RLE Mask */ 555 556 #define MXC_F_EMAC_REVA_INT_MASK_TXERR_POS 6 /**< INT_MASK_TXERR Position */ 557 #define MXC_F_EMAC_REVA_INT_MASK_TXERR ((uint32_t)(0x1UL << MXC_F_EMAC_REVA_INT_MASK_TXERR_POS)) /**< INT_MASK_TXERR Mask */ 558 559 #define MXC_F_EMAC_REVA_INT_MASK_TXCMPL_POS 7 /**< INT_MASK_TXCMPL Position */ 560 #define MXC_F_EMAC_REVA_INT_MASK_TXCMPL ((uint32_t)(0x1UL << MXC_F_EMAC_REVA_INT_MASK_TXCMPL_POS)) /**< INT_MASK_TXCMPL Mask */ 561 562 #define MXC_F_EMAC_REVA_INT_MASK_LC_POS 9 /**< INT_MASK_LC Position */ 563 #define MXC_F_EMAC_REVA_INT_MASK_LC ((uint32_t)(0x1UL << MXC_F_EMAC_REVA_INT_MASK_LC_POS)) /**< INT_MASK_LC Mask */ 564 565 #define MXC_F_EMAC_REVA_INT_MASK_RXOR_POS 10 /**< INT_MASK_RXOR Position */ 566 #define MXC_F_EMAC_REVA_INT_MASK_RXOR ((uint32_t)(0x1UL << MXC_F_EMAC_REVA_INT_MASK_RXOR_POS)) /**< INT_MASK_RXOR Mask */ 567 568 #define MXC_F_EMAC_REVA_INT_MASK_HRESPNO_POS 11 /**< INT_MASK_HRESPNO Position */ 569 #define MXC_F_EMAC_REVA_INT_MASK_HRESPNO ((uint32_t)(0x1UL << MXC_F_EMAC_REVA_INT_MASK_HRESPNO_POS)) /**< INT_MASK_HRESPNO Mask */ 570 571 #define MXC_F_EMAC_REVA_INT_MASK_PPR_POS 12 /**< INT_MASK_PPR Position */ 572 #define MXC_F_EMAC_REVA_INT_MASK_PPR ((uint32_t)(0x1UL << MXC_F_EMAC_REVA_INT_MASK_PPR_POS)) /**< INT_MASK_PPR Mask */ 573 574 #define MXC_F_EMAC_REVA_INT_MASK_PTZ_POS 13 /**< INT_MASK_PTZ Position */ 575 #define MXC_F_EMAC_REVA_INT_MASK_PTZ ((uint32_t)(0x1UL << MXC_F_EMAC_REVA_INT_MASK_PTZ_POS)) /**< INT_MASK_PTZ Mask */ 576 577 /**@} end of group EMAC_REVA_INT_MASK_Register */ 578 579 /** 580 * @ingroup emac_reva_registers 581 * @defgroup EMAC_REVA_PHY_MT EMAC_REVA_PHY_MT 582 * @brief PHY Maintenance Register. 583 * @{ 584 */ 585 #define MXC_F_EMAC_REVA_PHY_MT_DATA_POS 0 /**< PHY_MT_DATA Position */ 586 #define MXC_F_EMAC_REVA_PHY_MT_DATA ((uint32_t)(0xFFFFUL << MXC_F_EMAC_REVA_PHY_MT_DATA_POS)) /**< PHY_MT_DATA Mask */ 587 588 #define MXC_F_EMAC_REVA_PHY_MT_CODE_POS 16 /**< PHY_MT_CODE Position */ 589 #define MXC_F_EMAC_REVA_PHY_MT_CODE ((uint32_t)(0x3UL << MXC_F_EMAC_REVA_PHY_MT_CODE_POS)) /**< PHY_MT_CODE Mask */ 590 591 #define MXC_F_EMAC_REVA_PHY_MT_REGADDR_POS 18 /**< PHY_MT_REGADDR Position */ 592 #define MXC_F_EMAC_REVA_PHY_MT_REGADDR ((uint32_t)(0x1FUL << MXC_F_EMAC_REVA_PHY_MT_REGADDR_POS)) /**< PHY_MT_REGADDR Mask */ 593 594 #define MXC_F_EMAC_REVA_PHY_MT_PHYADDR_POS 23 /**< PHY_MT_PHYADDR Position */ 595 #define MXC_F_EMAC_REVA_PHY_MT_PHYADDR ((uint32_t)(0x1FUL << MXC_F_EMAC_REVA_PHY_MT_PHYADDR_POS)) /**< PHY_MT_PHYADDR Mask */ 596 597 #define MXC_F_EMAC_REVA_PHY_MT_OP_POS 28 /**< PHY_MT_OP Position */ 598 #define MXC_F_EMAC_REVA_PHY_MT_OP ((uint32_t)(0x3UL << MXC_F_EMAC_REVA_PHY_MT_OP_POS)) /**< PHY_MT_OP Mask */ 599 #define MXC_V_EMAC_REVA_PHY_MT_OP_WRITE ((uint32_t)0x1UL) /**< PHY_MT_OP_WRITE Value */ 600 #define MXC_S_EMAC_REVA_PHY_MT_OP_WRITE (MXC_V_EMAC_REVA_PHY_MT_OP_WRITE << MXC_F_EMAC_REVA_PHY_MT_OP_POS) /**< PHY_MT_OP_WRITE Setting */ 601 #define MXC_V_EMAC_REVA_PHY_MT_OP_READ ((uint32_t)0x2UL) /**< PHY_MT_OP_READ Value */ 602 #define MXC_S_EMAC_REVA_PHY_MT_OP_READ (MXC_V_EMAC_REVA_PHY_MT_OP_READ << MXC_F_EMAC_REVA_PHY_MT_OP_POS) /**< PHY_MT_OP_READ Setting */ 603 604 #define MXC_F_EMAC_REVA_PHY_MT_SOP_POS 30 /**< PHY_MT_SOP Position */ 605 #define MXC_F_EMAC_REVA_PHY_MT_SOP ((uint32_t)(0x3UL << MXC_F_EMAC_REVA_PHY_MT_SOP_POS)) /**< PHY_MT_SOP Mask */ 606 607 /**@} end of group EMAC_REVA_PHY_MT_Register */ 608 609 /** 610 * @ingroup emac_reva_registers 611 * @defgroup EMAC_REVA_PT EMAC_REVA_PT 612 * @brief Pause Time Register. 613 * @{ 614 */ 615 #define MXC_F_EMAC_REVA_PT_TIME_POS 0 /**< PT_TIME Position */ 616 #define MXC_F_EMAC_REVA_PT_TIME ((uint32_t)(0xFFFFUL << MXC_F_EMAC_REVA_PT_TIME_POS)) /**< PT_TIME Mask */ 617 618 /**@} end of group EMAC_REVA_PT_Register */ 619 620 /** 621 * @ingroup emac_reva_registers 622 * @defgroup EMAC_REVA_PFR EMAC_REVA_PFR 623 * @brief Pause Frame Received OK. 624 * @{ 625 */ 626 #define MXC_F_EMAC_REVA_PFR_PFR_POS 0 /**< PFR_PFR Position */ 627 #define MXC_F_EMAC_REVA_PFR_PFR ((uint32_t)(0xFFFFUL << MXC_F_EMAC_REVA_PFR_PFR_POS)) /**< PFR_PFR Mask */ 628 629 /**@} end of group EMAC_REVA_PFR_Register */ 630 631 /** 632 * @ingroup emac_reva_registers 633 * @defgroup EMAC_REVA_FTOK EMAC_REVA_FTOK 634 * @brief Frames Transmitted OK. 635 * @{ 636 */ 637 #define MXC_F_EMAC_REVA_FTOK_FTOK_POS 0 /**< FTOK_FTOK Position */ 638 #define MXC_F_EMAC_REVA_FTOK_FTOK ((uint32_t)(0xFFFFFFFFUL << MXC_F_EMAC_REVA_FTOK_FTOK_POS)) /**< FTOK_FTOK Mask */ 639 640 /**@} end of group EMAC_REVA_FTOK_Register */ 641 642 /** 643 * @ingroup emac_reva_registers 644 * @defgroup EMAC_REVA_SCF EMAC_REVA_SCF 645 * @brief Single Collision Frames. 646 * @{ 647 */ 648 #define MXC_F_EMAC_REVA_SCF_SCF_POS 0 /**< SCF_SCF Position */ 649 #define MXC_F_EMAC_REVA_SCF_SCF ((uint32_t)(0xFFFFUL << MXC_F_EMAC_REVA_SCF_SCF_POS)) /**< SCF_SCF Mask */ 650 651 /**@} end of group EMAC_REVA_SCF_Register */ 652 653 /** 654 * @ingroup emac_reva_registers 655 * @defgroup EMAC_REVA_MCF EMAC_REVA_MCF 656 * @brief Multiple Collision Frames. 657 * @{ 658 */ 659 #define MXC_F_EMAC_REVA_MCF_MCF_POS 0 /**< MCF_MCF Position */ 660 #define MXC_F_EMAC_REVA_MCF_MCF ((uint32_t)(0xFFFFUL << MXC_F_EMAC_REVA_MCF_MCF_POS)) /**< MCF_MCF Mask */ 661 662 /**@} end of group EMAC_REVA_MCF_Register */ 663 664 /** 665 * @ingroup emac_reva_registers 666 * @defgroup EMAC_REVA_FROK EMAC_REVA_FROK 667 * @brief Fames Received OK. 668 * @{ 669 */ 670 #define MXC_F_EMAC_REVA_FROK_FROK_POS 0 /**< FROK_FROK Position */ 671 #define MXC_F_EMAC_REVA_FROK_FROK ((uint32_t)(0xFFFFFFUL << MXC_F_EMAC_REVA_FROK_FROK_POS)) /**< FROK_FROK Mask */ 672 673 /**@} end of group EMAC_REVA_FROK_Register */ 674 675 /** 676 * @ingroup emac_reva_registers 677 * @defgroup EMAC_REVA_FCS_ERR EMAC_REVA_FCS_ERR 678 * @brief Frame Check Sequence Errors. 679 * @{ 680 */ 681 #define MXC_F_EMAC_REVA_FCS_ERR_FCSERR_POS 0 /**< FCS_ERR_FCSERR Position */ 682 #define MXC_F_EMAC_REVA_FCS_ERR_FCSERR ((uint32_t)(0xFFUL << MXC_F_EMAC_REVA_FCS_ERR_FCSERR_POS)) /**< FCS_ERR_FCSERR Mask */ 683 684 /**@} end of group EMAC_REVA_FCS_ERR_Register */ 685 686 /** 687 * @ingroup emac_reva_registers 688 * @defgroup EMAC_REVA_ALGN_ERR EMAC_REVA_ALGN_ERR 689 * @brief Alignment Errors. 690 * @{ 691 */ 692 #define MXC_F_EMAC_REVA_ALGN_ERR_ALGNERR_POS 0 /**< ALGN_ERR_ALGNERR Position */ 693 #define MXC_F_EMAC_REVA_ALGN_ERR_ALGNERR ((uint32_t)(0xFFUL << MXC_F_EMAC_REVA_ALGN_ERR_ALGNERR_POS)) /**< ALGN_ERR_ALGNERR Mask */ 694 695 /**@} end of group EMAC_REVA_ALGN_ERR_Register */ 696 697 /** 698 * @ingroup emac_reva_registers 699 * @defgroup EMAC_REVA_DFTXF EMAC_REVA_DFTXF 700 * @brief Deferred Transmission Frames. 701 * @{ 702 */ 703 #define MXC_F_EMAC_REVA_DFTXF_DFTXF_POS 0 /**< DFTXF_DFTXF Position */ 704 #define MXC_F_EMAC_REVA_DFTXF_DFTXF ((uint32_t)(0xFFFFUL << MXC_F_EMAC_REVA_DFTXF_DFTXF_POS)) /**< DFTXF_DFTXF Mask */ 705 706 /**@} end of group EMAC_REVA_DFTXF_Register */ 707 708 /** 709 * @ingroup emac_reva_registers 710 * @defgroup EMAC_REVA_LC EMAC_REVA_LC 711 * @brief Late Collisions. 712 * @{ 713 */ 714 #define MXC_F_EMAC_REVA_LC_LC_POS 0 /**< LC_LC Position */ 715 #define MXC_F_EMAC_REVA_LC_LC ((uint32_t)(0xFFUL << MXC_F_EMAC_REVA_LC_LC_POS)) /**< LC_LC Mask */ 716 717 /**@} end of group EMAC_REVA_LC_Register */ 718 719 /** 720 * @ingroup emac_reva_registers 721 * @defgroup EMAC_REVA_EC EMAC_REVA_EC 722 * @brief Excessive Collisions. 723 * @{ 724 */ 725 #define MXC_F_EMAC_REVA_EC_EC_POS 0 /**< EC_EC Position */ 726 #define MXC_F_EMAC_REVA_EC_EC ((uint32_t)(0xFFUL << MXC_F_EMAC_REVA_EC_EC_POS)) /**< EC_EC Mask */ 727 728 /**@} end of group EMAC_REVA_EC_Register */ 729 730 /** 731 * @ingroup emac_reva_registers 732 * @defgroup EMAC_REVA_TUR_ERR EMAC_REVA_TUR_ERR 733 * @brief Transmit Underrun Errors. 734 * @{ 735 */ 736 #define MXC_F_EMAC_REVA_TUR_ERR_TURERR_POS 0 /**< TUR_ERR_TURERR Position */ 737 #define MXC_F_EMAC_REVA_TUR_ERR_TURERR ((uint32_t)(0xFFUL << MXC_F_EMAC_REVA_TUR_ERR_TURERR_POS)) /**< TUR_ERR_TURERR Mask */ 738 739 /**@} end of group EMAC_REVA_TUR_ERR_Register */ 740 741 /** 742 * @ingroup emac_reva_registers 743 * @defgroup EMAC_REVA_CS_ERR EMAC_REVA_CS_ERR 744 * @brief Carrier Sense Errors. 745 * @{ 746 */ 747 #define MXC_F_EMAC_REVA_CS_ERR_CSERR_POS 0 /**< CS_ERR_CSERR Position */ 748 #define MXC_F_EMAC_REVA_CS_ERR_CSERR ((uint32_t)(0xFFUL << MXC_F_EMAC_REVA_CS_ERR_CSERR_POS)) /**< CS_ERR_CSERR Mask */ 749 750 /**@} end of group EMAC_REVA_CS_ERR_Register */ 751 752 /** 753 * @ingroup emac_reva_registers 754 * @defgroup EMAC_REVA_RR_ERR EMAC_REVA_RR_ERR 755 * @brief Receive Resource Errors. 756 * @{ 757 */ 758 #define MXC_F_EMAC_REVA_RR_ERR_RRERR_POS 0 /**< RR_ERR_RRERR Position */ 759 #define MXC_F_EMAC_REVA_RR_ERR_RRERR ((uint32_t)(0xFFFFUL << MXC_F_EMAC_REVA_RR_ERR_RRERR_POS)) /**< RR_ERR_RRERR Mask */ 760 761 /**@} end of group EMAC_REVA_RR_ERR_Register */ 762 763 /** 764 * @ingroup emac_reva_registers 765 * @defgroup EMAC_REVA_ROR_ERR EMAC_REVA_ROR_ERR 766 * @brief Receive Overrun Errors. 767 * @{ 768 */ 769 #define MXC_F_EMAC_REVA_ROR_ERR_RORERR_POS 0 /**< ROR_ERR_RORERR Position */ 770 #define MXC_F_EMAC_REVA_ROR_ERR_RORERR ((uint32_t)(0xFFUL << MXC_F_EMAC_REVA_ROR_ERR_RORERR_POS)) /**< ROR_ERR_RORERR Mask */ 771 772 /**@} end of group EMAC_REVA_ROR_ERR_Register */ 773 774 /** 775 * @ingroup emac_reva_registers 776 * @defgroup EMAC_REVA_RS_ERR EMAC_REVA_RS_ERR 777 * @brief Receive Symbol Errors. 778 * @{ 779 */ 780 #define MXC_F_EMAC_REVA_RS_ERR_RSERR_POS 0 /**< RS_ERR_RSERR Position */ 781 #define MXC_F_EMAC_REVA_RS_ERR_RSERR ((uint32_t)(0xFFUL << MXC_F_EMAC_REVA_RS_ERR_RSERR_POS)) /**< RS_ERR_RSERR Mask */ 782 783 /**@} end of group EMAC_REVA_RS_ERR_Register */ 784 785 /** 786 * @ingroup emac_reva_registers 787 * @defgroup EMAC_REVA_EL_ERR EMAC_REVA_EL_ERR 788 * @brief Excessive Length Errors. 789 * @{ 790 */ 791 #define MXC_F_EMAC_REVA_EL_ERR_ELERR_POS 0 /**< EL_ERR_ELERR Position */ 792 #define MXC_F_EMAC_REVA_EL_ERR_ELERR ((uint32_t)(0xFFUL << MXC_F_EMAC_REVA_EL_ERR_ELERR_POS)) /**< EL_ERR_ELERR Mask */ 793 794 /**@} end of group EMAC_REVA_EL_ERR_Register */ 795 796 /** 797 * @ingroup emac_reva_registers 798 * @defgroup EMAC_REVA_RJ EMAC_REVA_RJ 799 * @brief Receive Jabber. 800 * @{ 801 */ 802 #define MXC_F_EMAC_REVA_RJ_RJERR_POS 0 /**< RJ_RJERR Position */ 803 #define MXC_F_EMAC_REVA_RJ_RJERR ((uint32_t)(0xFFUL << MXC_F_EMAC_REVA_RJ_RJERR_POS)) /**< RJ_RJERR Mask */ 804 805 /**@} end of group EMAC_REVA_RJ_Register */ 806 807 /** 808 * @ingroup emac_reva_registers 809 * @defgroup EMAC_REVA_USF EMAC_REVA_USF 810 * @brief Undersize Frames. 811 * @{ 812 */ 813 #define MXC_F_EMAC_REVA_USF_USF_POS 0 /**< USF_USF Position */ 814 #define MXC_F_EMAC_REVA_USF_USF ((uint32_t)(0xFFUL << MXC_F_EMAC_REVA_USF_USF_POS)) /**< USF_USF Mask */ 815 816 /**@} end of group EMAC_REVA_USF_Register */ 817 818 /** 819 * @ingroup emac_reva_registers 820 * @defgroup EMAC_REVA_SQE_ERR EMAC_REVA_SQE_ERR 821 * @brief SQE Test Errors. 822 * @{ 823 */ 824 #define MXC_F_EMAC_REVA_SQE_ERR_SQEERR_POS 0 /**< SQE_ERR_SQEERR Position */ 825 #define MXC_F_EMAC_REVA_SQE_ERR_SQEERR ((uint32_t)(0xFFUL << MXC_F_EMAC_REVA_SQE_ERR_SQEERR_POS)) /**< SQE_ERR_SQEERR Mask */ 826 827 /**@} end of group EMAC_REVA_SQE_ERR_Register */ 828 829 /** 830 * @ingroup emac_reva_registers 831 * @defgroup EMAC_REVA_RLFM EMAC_REVA_RLFM 832 * @brief Received Length Field Mismatch. 833 * @{ 834 */ 835 #define MXC_F_EMAC_REVA_RLFM_RLFM_POS 0 /**< RLFM_RLFM Position */ 836 #define MXC_F_EMAC_REVA_RLFM_RLFM ((uint32_t)(0xFFUL << MXC_F_EMAC_REVA_RLFM_RLFM_POS)) /**< RLFM_RLFM Mask */ 837 838 /**@} end of group EMAC_REVA_RLFM_Register */ 839 840 /** 841 * @ingroup emac_reva_registers 842 * @defgroup EMAC_REVA_TPF EMAC_REVA_TPF 843 * @brief Transmitted Pause Frames. 844 * @{ 845 */ 846 #define MXC_F_EMAC_REVA_TPF_TPF_POS 0 /**< TPF_TPF Position */ 847 #define MXC_F_EMAC_REVA_TPF_TPF ((uint32_t)(0xFFFFUL << MXC_F_EMAC_REVA_TPF_TPF_POS)) /**< TPF_TPF Mask */ 848 849 /**@} end of group EMAC_REVA_TPF_Register */ 850 851 /** 852 * @ingroup emac_reva_registers 853 * @defgroup EMAC_REVA_HASHL EMAC_REVA_HASHL 854 * @brief Hash Register Bottom [31:0]. 855 * @{ 856 */ 857 #define MXC_F_EMAC_REVA_HASHL_HASH_POS 0 /**< HASHL_HASH Position */ 858 #define MXC_F_EMAC_REVA_HASHL_HASH ((uint32_t)(0xFFFFFFFFUL << MXC_F_EMAC_REVA_HASHL_HASH_POS)) /**< HASHL_HASH Mask */ 859 860 /**@} end of group EMAC_REVA_HASHL_Register */ 861 862 /** 863 * @ingroup emac_reva_registers 864 * @defgroup EMAC_REVA_HASHH EMAC_REVA_HASHH 865 * @brief Hash Register top [63:32]. 866 * @{ 867 */ 868 #define MXC_F_EMAC_REVA_HASHH_HASH_POS 0 /**< HASHH_HASH Position */ 869 #define MXC_F_EMAC_REVA_HASHH_HASH ((uint32_t)(0xFFFFFFFFUL << MXC_F_EMAC_REVA_HASHH_HASH_POS)) /**< HASHH_HASH Mask */ 870 871 /**@} end of group EMAC_REVA_HASHH_Register */ 872 873 /** 874 * @ingroup emac_reva_registers 875 * @defgroup EMAC_REVA_SA1L EMAC_REVA_SA1L 876 * @brief Specific Address 1 Bottom. 877 * @{ 878 */ 879 #define MXC_F_EMAC_REVA_SA1L_ADDR_POS 0 /**< SA1L_ADDR Position */ 880 #define MXC_F_EMAC_REVA_SA1L_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_EMAC_REVA_SA1L_ADDR_POS)) /**< SA1L_ADDR Mask */ 881 882 /**@} end of group EMAC_REVA_SA1L_Register */ 883 884 /** 885 * @ingroup emac_reva_registers 886 * @defgroup EMAC_REVA_SA1H EMAC_REVA_SA1H 887 * @brief Specific Address 1 Top. 888 * @{ 889 */ 890 #define MXC_F_EMAC_REVA_SA1H_ADDR_POS 0 /**< SA1H_ADDR Position */ 891 #define MXC_F_EMAC_REVA_SA1H_ADDR ((uint32_t)(0xFFFFUL << MXC_F_EMAC_REVA_SA1H_ADDR_POS)) /**< SA1H_ADDR Mask */ 892 893 /**@} end of group EMAC_REVA_SA1H_Register */ 894 895 /** 896 * @ingroup emac_reva_registers 897 * @defgroup EMAC_REVA_SA2L EMAC_REVA_SA2L 898 * @brief Specific Address 2 Bottom. 899 * @{ 900 */ 901 #define MXC_F_EMAC_REVA_SA2L_ADDR_POS 0 /**< SA2L_ADDR Position */ 902 #define MXC_F_EMAC_REVA_SA2L_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_EMAC_REVA_SA2L_ADDR_POS)) /**< SA2L_ADDR Mask */ 903 904 /**@} end of group EMAC_REVA_SA2L_Register */ 905 906 /** 907 * @ingroup emac_reva_registers 908 * @defgroup EMAC_REVA_SA2H EMAC_REVA_SA2H 909 * @brief Specific Address 2 Top. 910 * @{ 911 */ 912 #define MXC_F_EMAC_REVA_SA2H_ADDR_POS 0 /**< SA2H_ADDR Position */ 913 #define MXC_F_EMAC_REVA_SA2H_ADDR ((uint32_t)(0xFFFFUL << MXC_F_EMAC_REVA_SA2H_ADDR_POS)) /**< SA2H_ADDR Mask */ 914 915 /**@} end of group EMAC_REVA_SA2H_Register */ 916 917 /** 918 * @ingroup emac_reva_registers 919 * @defgroup EMAC_REVA_SA3L EMAC_REVA_SA3L 920 * @brief Specific Address 3 Bottom. 921 * @{ 922 */ 923 #define MXC_F_EMAC_REVA_SA3L_ADDR_POS 0 /**< SA3L_ADDR Position */ 924 #define MXC_F_EMAC_REVA_SA3L_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_EMAC_REVA_SA3L_ADDR_POS)) /**< SA3L_ADDR Mask */ 925 926 /**@} end of group EMAC_REVA_SA3L_Register */ 927 928 /** 929 * @ingroup emac_reva_registers 930 * @defgroup EMAC_REVA_SA3H EMAC_REVA_SA3H 931 * @brief Specific Address 3 Top. 932 * @{ 933 */ 934 #define MXC_F_EMAC_REVA_SA3H_ADDR_POS 0 /**< SA3H_ADDR Position */ 935 #define MXC_F_EMAC_REVA_SA3H_ADDR ((uint32_t)(0xFFFFUL << MXC_F_EMAC_REVA_SA3H_ADDR_POS)) /**< SA3H_ADDR Mask */ 936 937 /**@} end of group EMAC_REVA_SA3H_Register */ 938 939 /** 940 * @ingroup emac_reva_registers 941 * @defgroup EMAC_REVA_SA4L EMAC_REVA_SA4L 942 * @brief Specific Address 4 Bottom. 943 * @{ 944 */ 945 #define MXC_F_EMAC_REVA_SA4L_ADDR_POS 0 /**< SA4L_ADDR Position */ 946 #define MXC_F_EMAC_REVA_SA4L_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_EMAC_REVA_SA4L_ADDR_POS)) /**< SA4L_ADDR Mask */ 947 948 /**@} end of group EMAC_REVA_SA4L_Register */ 949 950 /** 951 * @ingroup emac_reva_registers 952 * @defgroup EMAC_REVA_SA4H EMAC_REVA_SA4H 953 * @brief Specific Address 4 Top. 954 * @{ 955 */ 956 #define MXC_F_EMAC_REVA_SA4H_ADDR_POS 0 /**< SA4H_ADDR Position */ 957 #define MXC_F_EMAC_REVA_SA4H_ADDR ((uint32_t)(0xFFFFUL << MXC_F_EMAC_REVA_SA4H_ADDR_POS)) /**< SA4H_ADDR Mask */ 958 959 /**@} end of group EMAC_REVA_SA4H_Register */ 960 961 /** 962 * @ingroup emac_reva_registers 963 * @defgroup EMAC_REVA_TID_CK EMAC_REVA_TID_CK 964 * @brief Type ID Checking. 965 * @{ 966 */ 967 #define MXC_F_EMAC_REVA_TID_CK_TID_POS 0 /**< TID_CK_TID Position */ 968 #define MXC_F_EMAC_REVA_TID_CK_TID ((uint32_t)(0xFFFFUL << MXC_F_EMAC_REVA_TID_CK_TID_POS)) /**< TID_CK_TID Mask */ 969 970 /**@} end of group EMAC_REVA_TID_CK_Register */ 971 972 /** 973 * @ingroup emac_reva_registers 974 * @defgroup EMAC_REVA_TPQ EMAC_REVA_TPQ 975 * @brief Transmit Pause Quantum. 976 * @{ 977 */ 978 #define MXC_F_EMAC_REVA_TPQ_TPQ_POS 0 /**< TPQ_TPQ Position */ 979 #define MXC_F_EMAC_REVA_TPQ_TPQ ((uint32_t)(0xFFFFUL << MXC_F_EMAC_REVA_TPQ_TPQ_POS)) /**< TPQ_TPQ Mask */ 980 981 /**@} end of group EMAC_REVA_TPQ_Register */ 982 983 /** 984 * @ingroup emac_reva_registers 985 * @defgroup EMAC_REVA_USRIO EMAC_REVA_USRIO 986 * @brief User Input Output Register 987 * @{ 988 */ 989 #define MXC_F_EMAC_REVA_USRIO_MII_POS 0 /**< USRIO_MII Position */ 990 #define MXC_F_EMAC_REVA_USRIO_MII ((uint32_t)(0x1UL << MXC_F_EMAC_REVA_USRIO_MII_POS)) /**< USRIO_MII Mask */ 991 992 /**@} end of group EMAC_REVA_USRIO_Register */ 993 994 /** 995 * @ingroup emac_reva_registers 996 * @defgroup EMAC_REVA_WOL EMAC_REVA_WOL 997 * @brief Wake On LAN Register 998 * @{ 999 */ 1000 #define MXC_F_EMAC_REVA_WOL_IP_POS 0 /**< WOL_IP Position */ 1001 #define MXC_F_EMAC_REVA_WOL_IP ((uint32_t)(0xFFFFUL << MXC_F_EMAC_REVA_WOL_IP_POS)) /**< WOL_IP Mask */ 1002 1003 #define MXC_F_EMAC_REVA_WOL_MAG_POS 16 /**< WOL_MAG Position */ 1004 #define MXC_F_EMAC_REVA_WOL_MAG ((uint32_t)(0x1UL << MXC_F_EMAC_REVA_WOL_MAG_POS)) /**< WOL_MAG Mask */ 1005 1006 #define MXC_F_EMAC_REVA_WOL_ARP_POS 17 /**< WOL_ARP Position */ 1007 #define MXC_F_EMAC_REVA_WOL_ARP ((uint32_t)(0x1UL << MXC_F_EMAC_REVA_WOL_ARP_POS)) /**< WOL_ARP Mask */ 1008 1009 #define MXC_F_EMAC_REVA_WOL_SA1_POS 18 /**< WOL_SA1 Position */ 1010 #define MXC_F_EMAC_REVA_WOL_SA1 ((uint32_t)(0x1UL << MXC_F_EMAC_REVA_WOL_SA1_POS)) /**< WOL_SA1 Mask */ 1011 1012 #define MXC_F_EMAC_REVA_WOL_MTI_POS 19 /**< WOL_MTI Position */ 1013 #define MXC_F_EMAC_REVA_WOL_MTI ((uint32_t)(0x1UL << MXC_F_EMAC_REVA_WOL_MTI_POS)) /**< WOL_MTI Mask */ 1014 1015 /**@} end of group EMAC_REVA_WOL_Register */ 1016 1017 /** 1018 * @ingroup emac_reva_registers 1019 * @defgroup EMAC_REVA_REV EMAC_REVA_REV 1020 * @brief Revision register. 1021 * @{ 1022 */ 1023 #define MXC_F_EMAC_REVA_REV_REV_POS 0 /**< REV_REV Position */ 1024 #define MXC_F_EMAC_REVA_REV_REV ((uint32_t)(0xFFFFUL << MXC_F_EMAC_REVA_REV_REV_POS)) /**< REV_REV Mask */ 1025 1026 #define MXC_F_EMAC_REVA_REV_PART_POS 16 /**< REV_PART Position */ 1027 #define MXC_F_EMAC_REVA_REV_PART ((uint32_t)(0xFFFFUL << MXC_F_EMAC_REVA_REV_PART_POS)) /**< REV_PART Mask */ 1028 1029 /**@} end of group EMAC_REVA_REV_Register */ 1030 1031 #ifdef __cplusplus 1032 } 1033 #endif 1034 1035 #endif /* _EMAC_REVA_REGS_H_ */ 1036
