1/*
2 * Copyright (c) 2024 Renesas Electronics Corporation
3 * SPDX-License-Identifier: Apache-2.0
4 */
5
6&pinctrl {
7	sci9_default: sci9_default {
8		group1 {
9			/* tx */
10			psels = <RA_PSEL(RA_PSEL_SCI_9, 10, 14)>;
11			drive-strength = "medium";
12		};
13		group2 {
14			/* rx */
15			psels = <RA_PSEL(RA_PSEL_SCI_9, 10, 15)>;
16		};
17	};
18
19	spi0_default: spi0_default {
20		group1 {
21			/* MISO MOSI RSPCK SSL */
22			psels = <RA_PSEL(RA_PSEL_SPI, 4, 10)>,
23			<RA_PSEL(RA_PSEL_SPI, 4, 11)>,
24			<RA_PSEL(RA_PSEL_SPI, 4, 12)>,
25			<RA_PSEL(RA_PSEL_SPI, 4, 13)>;
26		};
27	};
28
29	pwm7_default: pwm7_default {
30		group1 {
31			/* GTIOC7A */
32			psels = <RA_PSEL(RA_PSEL_GPT1, 10, 7)>;
33		};
34		group2 {
35			/* GTIOC7B */
36			psels = <RA_PSEL(RA_PSEL_GPT1, 10, 6)>;
37		};
38	};
39
40	canfd0_default: canfd0_default {
41		group1 {
42			/* CRX0 CTX0 */
43			psels = <RA_PSEL(RA_PSEL_CANFD, 4, 2)>,
44			<RA_PSEL(RA_PSEL_CANFD, 4, 1)>;
45			drive-strength = "high";
46		};
47	};
48
49	iic1_default: iic1_default {
50		group1 {
51			/* SCL1 SDA1*/
52			psels = <RA_PSEL(RA_PSEL_I2C, 5, 12)>,<RA_PSEL(RA_PSEL_I2C, 5, 11)>;
53			drive-strength = "medium";
54		};
55	};
56
57	ether_default: ether_default {
58		group1 {
59			psels = <RA_PSEL(RA_PSEL_ETH_RMII, 4, 1)>, /* ET0_MDC */
60					<RA_PSEL(RA_PSEL_ETH_RMII, 4, 2)>, /* ET0_MDIO */
61					<RA_PSEL(RA_PSEL_ETH_RMII, 4, 3)>, /* ET0_LINKSTA */
62					<RA_PSEL(RA_PSEL_ETH_RMII, 4, 5)>, /* RMII0_TXD_EN_B */
63					<RA_PSEL(RA_PSEL_ETH_RMII, 4, 6)>, /* RMII0_TXD1_BR */
64					<RA_PSEL(RA_PSEL_ETH_RMII, 7, 0)>, /* RMII0_TXD0_B */
65					<RA_PSEL(RA_PSEL_ETH_RMII, 7, 1)>, /* REF50CK0_B */
66					<RA_PSEL(RA_PSEL_ETH_RMII, 7, 2)>, /* RMII0_RXD0_B */
67					<RA_PSEL(RA_PSEL_ETH_RMII, 7, 3)>, /* RMII0_RXD1_B */
68					<RA_PSEL(RA_PSEL_ETH_RMII, 7, 4)>, /* RMII0_RX_ER_B */
69					<RA_PSEL(RA_PSEL_ETH_RMII, 7, 5)>; /* RMII0_CRS_DV_B */
70			drive-strength = "high";
71		};
72	};
73
74	usbhs_default: usbhs_default {
75		group1 {
76			psels = <RA_PSEL(RA_PSEL_USBHS, 11, 1)>; /* USBHS-VBUS */
77			drive-strength = "high";
78		};
79	};
80
81	adc0_default: adc0_default {
82		group1 {
83			/* input */
84			psels = <RA_PSEL(RA_PSEL_ADC, 0, 4)>;
85			renesas,analog-enable;
86		};
87	};
88
89	sdram_default: sdram_default{
90		group1 {
91			/* SDRAM_DQM1 */
92			psels = <RA_PSEL(RA_PSEL_BUS, 1, 12)>,
93			/* SDRAM_CKE */
94			<RA_PSEL(RA_PSEL_BUS, 1, 13)>,
95			/* SDRAM_WE */
96			<RA_PSEL(RA_PSEL_BUS, 1, 14)>,
97			/* SDRAM_CS */
98			<RA_PSEL(RA_PSEL_BUS, 1, 15)>,
99			/* SDRAM_A0 */
100			<RA_PSEL(RA_PSEL_BUS, 3, 0)>,
101			/* SDRAM_A1 */
102			<RA_PSEL(RA_PSEL_BUS, 3, 1)>,
103			/* SDRAM_A2 */
104			<RA_PSEL(RA_PSEL_BUS, 3, 2)>,
105			/* SDRAM_A3 */
106			<RA_PSEL(RA_PSEL_BUS, 3, 3)>,
107			/* SDRAM_A4 */
108			<RA_PSEL(RA_PSEL_BUS, 3, 4)>,
109			/* SDRAM_A5 */
110			<RA_PSEL(RA_PSEL_BUS, 3, 5)>,
111			/* SDRAM_A6 */
112			<RA_PSEL(RA_PSEL_BUS, 3, 6)>,
113			/* SDRAM_A7 */
114			<RA_PSEL(RA_PSEL_BUS, 3, 7)>,
115			/* SDRAM_A8 */
116			<RA_PSEL(RA_PSEL_BUS, 3, 8)>,
117			/* SDRAM_A9 */
118			<RA_PSEL(RA_PSEL_BUS, 3, 9)>,
119			/* SDRAM_A10 */
120			<RA_PSEL(RA_PSEL_BUS, 3, 10)>,
121			/* SDRAM_A11 */
122			<RA_PSEL(RA_PSEL_BUS, 3, 11)>,
123			/* SDRAM_A12 */
124			<RA_PSEL(RA_PSEL_BUS, 3, 12)>,
125			/* SDRAM_D0 */
126			<RA_PSEL(RA_PSEL_BUS, 6, 1)>,
127			/* SDRAM_D1 */
128			<RA_PSEL(RA_PSEL_BUS, 6, 2)>,
129			/* SDRAM_D2 */
130			<RA_PSEL(RA_PSEL_BUS, 6, 3)>,
131			/* SDRAM_D3 */
132			<RA_PSEL(RA_PSEL_BUS, 6, 4)>,
133			/* SDRAM_D4 */
134			<RA_PSEL(RA_PSEL_BUS, 6, 5)>,
135			/* SDRAM_D5 */
136			<RA_PSEL(RA_PSEL_BUS, 6, 6)>,
137			/* SDRAM_D6 */
138			<RA_PSEL(RA_PSEL_BUS, 6, 7)>,
139			/* SDRAM_D8 */
140			<RA_PSEL(RA_PSEL_BUS, 6, 9)>,
141			/* SDRAM_D9 */
142			<RA_PSEL(RA_PSEL_BUS, 6, 10)>,
143			/* SDRAM_D10 */
144			<RA_PSEL(RA_PSEL_BUS, 6, 11)>,
145			/* SDRAM_D11 */
146			<RA_PSEL(RA_PSEL_BUS, 6, 12)>,
147			/* SDRAM_D12 */
148			<RA_PSEL(RA_PSEL_BUS, 6, 13)>,
149			/* SDRAM_D13 */
150			<RA_PSEL(RA_PSEL_BUS, 6, 14)>,
151			/* SDRAM_D14 */
152			<RA_PSEL(RA_PSEL_BUS, 6, 15)>,
153			/* SDRAM_BA0 */
154			<RA_PSEL(RA_PSEL_BUS, 9, 5)>,
155			/* SDRAM_BA1 */
156			<RA_PSEL(RA_PSEL_BUS, 9, 6)>,
157			/* SDRAM_RAS */
158			<RA_PSEL(RA_PSEL_BUS, 9, 8)>,
159			/* SDRAM_CAS */
160			<RA_PSEL(RA_PSEL_BUS, 9, 9)>,
161			/* SDRAM_SDCLK */
162			<RA_PSEL(RA_PSEL_BUS, 10, 9)>;
163			drive-strength = "high";
164		};
165
166		group2 {
167			/* SDRAM_SDCLK */
168			psels = <RA_PSEL(RA_PSEL_BUS, 10, 9)>;
169			drive-strength = "highspeed-high";
170		};
171
172		group3 {
173			/* SDRAM_D7 */
174			psels = <RA_PSEL(RA_PSEL_BUS, 10, 0)>,
175			/* SDRAM_D15 */
176			<RA_PSEL(RA_PSEL_BUS, 10, 8)>,
177			/* SDRAM_DQM0 */
178			<RA_PSEL(RA_PSEL_BUS, 10, 10)>;
179		};
180	};
181
182	glcdc_default: glcdc_default {
183		group1 {
184			/* LCDC_TCON0 */
185			psels = <RA_PSEL(RA_PSEL_GLCDC, 8, 5)>,
186			/* LCDC_TCON1 */
187			<RA_PSEL(RA_PSEL_GLCDC, 8, 7)>,
188			/* LCDC_TCON2 */
189			<RA_PSEL(RA_PSEL_GLCDC, 5, 13)>,
190			/* LCDC_TCON3 */
191			<RA_PSEL(RA_PSEL_GLCDC, 5, 15)>,
192			/* LCDC_DATA00 */
193			<RA_PSEL(RA_PSEL_GLCDC, 9, 14)>,
194			/* LCDC_DATA01 */
195			<RA_PSEL(RA_PSEL_GLCDC, 9, 15)>,
196			/* LCDC_DATA02 */
197			<RA_PSEL(RA_PSEL_GLCDC, 9, 10)>,
198			/* LCDC_DATA03 */
199			<RA_PSEL(RA_PSEL_GLCDC, 9, 11)>,
200			/* LCDC_DATA04 */
201			<RA_PSEL(RA_PSEL_GLCDC, 9, 12)>,
202			/* LCDC_DATA05 */
203			<RA_PSEL(RA_PSEL_GLCDC, 9, 13)>,
204			/* LCDC_DATA06 */
205			<RA_PSEL(RA_PSEL_GLCDC, 9, 4)>,
206			/* LCDC_DATA07 */
207			<RA_PSEL(RA_PSEL_GLCDC, 9, 3)>,
208			/* LCDC_DATA08 */
209			<RA_PSEL(RA_PSEL_GLCDC, 9, 2)>,
210			/* LCDC_DATA09 */
211			<RA_PSEL(RA_PSEL_GLCDC, 2, 7)>,
212			/* LCDC_DATA10 */
213			<RA_PSEL(RA_PSEL_GLCDC, 7, 11)>,
214			/* LCDC_DATA11 */
215			<RA_PSEL(RA_PSEL_GLCDC, 7, 12)>,
216			/* LCDC_DATA12 */
217			<RA_PSEL(RA_PSEL_GLCDC, 7, 13)>,
218			/* LCDC_DATA13 */
219			<RA_PSEL(RA_PSEL_GLCDC, 7, 14)>,
220			/* LCDC_DATA14 */
221			<RA_PSEL(RA_PSEL_GLCDC, 7, 15)>,
222			/* LCDC_DATA15 */
223			<RA_PSEL(RA_PSEL_GLCDC, 11, 7)>,
224			/* LCDC_DATA16 */
225			<RA_PSEL(RA_PSEL_GLCDC, 11, 6)>,
226			/* LCDC_DATA17 */
227			<RA_PSEL(RA_PSEL_GLCDC, 11, 5)>,
228			/* LCDC_DATA18 */
229			<RA_PSEL(RA_PSEL_GLCDC, 11, 1)>,
230			/* LCDC_DATA19 */
231			<RA_PSEL(RA_PSEL_GLCDC, 11, 4)>,
232			/* LCDC_DATA20 */
233			<RA_PSEL(RA_PSEL_GLCDC, 11, 3)>,
234			/* LCDC_DATA21 */
235			<RA_PSEL(RA_PSEL_GLCDC, 11, 2)>,
236			/* LCDC_DATA22 */
237			<RA_PSEL(RA_PSEL_GLCDC, 11, 0)>,
238			/* LCDC_DATA23 */
239			<RA_PSEL(RA_PSEL_GLCDC, 7, 7)>,
240			/* LCDC_CLK */
241			<RA_PSEL(RA_PSEL_GLCDC, 8, 6)>,
242			/* LCDC_EXTCLK */
243			<RA_PSEL(RA_PSEL_GLCDC, 5, 14)>;
244		};
245	};
246
247	/* NOTE: pins conflict with ether_default */
248	sdhc1_default: sdhc1_default {
249		group1 {
250			psels = <RA_PSEL(RA_PSEL_SDHI, 4, 6)>, /* SDCD */
251			<RA_PSEL(RA_PSEL_SDHI, 4, 1)>, /* SDCMD */
252			<RA_PSEL(RA_PSEL_SDHI, 4, 2)>, /* SDDATA0 */
253			<RA_PSEL(RA_PSEL_SDHI, 4, 3)>, /* SDDATA1 */
254			<RA_PSEL(RA_PSEL_SDHI, 4, 4)>, /* SDDATA2 */
255			<RA_PSEL(RA_PSEL_SDHI, 4, 5)>, /* SDDATA3 */
256			<RA_PSEL(RA_PSEL_SDHI, 7, 0)>; /* SDWP */
257			drive-strength = "high";
258		};
259		group2 {
260			psels = <RA_PSEL(RA_PSEL_SDHI, 4, 0)>; /* SDCLK */
261			drive-strength = "highspeed-high";
262		};
263	};
264};
265