1 /**************************************************************************//** 2 * @file 3 * @brief EFR32ZG23 PFMXPPRF register and bit field definitions 4 ****************************************************************************** 5 * # License 6 * <b>Copyright 2024 Silicon Laboratories, Inc. www.silabs.com</b> 7 ****************************************************************************** 8 * 9 * SPDX-License-Identifier: Zlib 10 * 11 * The licensor of this software is Silicon Laboratories Inc. 12 * 13 * This software is provided 'as-is', without any express or implied 14 * warranty. In no event will the authors be held liable for any damages 15 * arising from the use of this software. 16 * 17 * Permission is granted to anyone to use this software for any purpose, 18 * including commercial applications, and to alter it and redistribute it 19 * freely, subject to the following restrictions: 20 * 21 * 1. The origin of this software must not be misrepresented; you must not 22 * claim that you wrote the original software. If you use this software 23 * in a product, an acknowledgment in the product documentation would be 24 * appreciated but is not required. 25 * 2. Altered source versions must be plainly marked as such, and must not be 26 * misrepresented as being the original software. 27 * 3. This notice may not be removed or altered from any source distribution. 28 * 29 *****************************************************************************/ 30 #ifndef EFR32ZG23_PFMXPPRF_H 31 #define EFR32ZG23_PFMXPPRF_H 32 #define PFMXPPRF_HAS_SET_CLEAR 33 34 /**************************************************************************//** 35 * @addtogroup Parts 36 * @{ 37 ******************************************************************************/ 38 /**************************************************************************//** 39 * @defgroup EFR32ZG23_PFMXPPRF PFMXPPRF 40 * @{ 41 * @brief EFR32ZG23 PFMXPPRF Register Declaration. 42 *****************************************************************************/ 43 44 /** PFMXPPRF Register Declaration. */ 45 typedef struct pfmxpprf_typedef{ 46 __IOM uint32_t RFIMDCDCCTRL0; /**< New Register */ 47 __IOM uint32_t RFIMDCDCCTRL1; /**< New Register */ 48 __IOM uint32_t RFIMDCDCCTRL2; /**< New Register */ 49 __IM uint32_t RFIMDCDCSTATUS; /**< New Register */ 50 __IOM uint32_t RPURATD0; /**< Root Access Type Descriptor Register */ 51 uint32_t RESERVED0[1019U]; /**< Reserved for future use */ 52 __IOM uint32_t RFIMDCDCCTRL0_SET; /**< New Register */ 53 __IOM uint32_t RFIMDCDCCTRL1_SET; /**< New Register */ 54 __IOM uint32_t RFIMDCDCCTRL2_SET; /**< New Register */ 55 __IM uint32_t RFIMDCDCSTATUS_SET; /**< New Register */ 56 __IOM uint32_t RPURATD0_SET; /**< Root Access Type Descriptor Register */ 57 uint32_t RESERVED1[1019U]; /**< Reserved for future use */ 58 __IOM uint32_t RFIMDCDCCTRL0_CLR; /**< New Register */ 59 __IOM uint32_t RFIMDCDCCTRL1_CLR; /**< New Register */ 60 __IOM uint32_t RFIMDCDCCTRL2_CLR; /**< New Register */ 61 __IM uint32_t RFIMDCDCSTATUS_CLR; /**< New Register */ 62 __IOM uint32_t RPURATD0_CLR; /**< Root Access Type Descriptor Register */ 63 uint32_t RESERVED2[1019U]; /**< Reserved for future use */ 64 __IOM uint32_t RFIMDCDCCTRL0_TGL; /**< New Register */ 65 __IOM uint32_t RFIMDCDCCTRL1_TGL; /**< New Register */ 66 __IOM uint32_t RFIMDCDCCTRL2_TGL; /**< New Register */ 67 __IM uint32_t RFIMDCDCSTATUS_TGL; /**< New Register */ 68 __IOM uint32_t RPURATD0_TGL; /**< Root Access Type Descriptor Register */ 69 } PFMXPPRF_TypeDef; 70 /** @} End of group EFR32ZG23_PFMXPPRF */ 71 72 /**************************************************************************//** 73 * @addtogroup EFR32ZG23_PFMXPPRF 74 * @{ 75 * @defgroup EFR32ZG23_PFMXPPRF_BitFields PFMXPPRF Bit Fields 76 * @{ 77 *****************************************************************************/ 78 79 /* Bit fields for PFMXPPRF RFIMDCDCCTRL0 */ 80 #define _PFMXPPRF_RFIMDCDCCTRL0_RESETVALUE 0x00000000UL /**< Default value for PFMXPPRF_RFIMDCDCCTRL0 */ 81 #define _PFMXPPRF_RFIMDCDCCTRL0_MASK 0x80000003UL /**< Mask for PFMXPPRF_RFIMDCDCCTRL0 */ 82 #define PFMXPPRF_RFIMDCDCCTRL0_TXMAXREQ (0x1UL << 0) /**< TX Max Req */ 83 #define _PFMXPPRF_RFIMDCDCCTRL0_TXMAXREQ_SHIFT 0 /**< Shift value for PFMXPPRF_TXMAXREQ */ 84 #define _PFMXPPRF_RFIMDCDCCTRL0_TXMAXREQ_MASK 0x1UL /**< Bit mask for PFMXPPRF_TXMAXREQ */ 85 #define _PFMXPPRF_RFIMDCDCCTRL0_TXMAXREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for PFMXPPRF_RFIMDCDCCTRL0 */ 86 #define PFMXPPRF_RFIMDCDCCTRL0_TXMAXREQ_DEFAULT (_PFMXPPRF_RFIMDCDCCTRL0_TXMAXREQ_DEFAULT << 0) /**< Shifted mode DEFAULT for PFMXPPRF_RFIMDCDCCTRL0*/ 87 #define PFMXPPRF_RFIMDCDCCTRL0_RXPPREQ (0x1UL << 1) /**< RX PP Req */ 88 #define _PFMXPPRF_RFIMDCDCCTRL0_RXPPREQ_SHIFT 1 /**< Shift value for PFMXPPRF_RXPPREQ */ 89 #define _PFMXPPRF_RFIMDCDCCTRL0_RXPPREQ_MASK 0x2UL /**< Bit mask for PFMXPPRF_RXPPREQ */ 90 #define _PFMXPPRF_RFIMDCDCCTRL0_RXPPREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for PFMXPPRF_RFIMDCDCCTRL0 */ 91 #define PFMXPPRF_RFIMDCDCCTRL0_RXPPREQ_DEFAULT (_PFMXPPRF_RFIMDCDCCTRL0_RXPPREQ_DEFAULT << 1) /**< Shifted mode DEFAULT for PFMXPPRF_RFIMDCDCCTRL0*/ 92 93 /* Bit fields for PFMXPPRF RFIMDCDCCTRL1 */ 94 #define _PFMXPPRF_RFIMDCDCCTRL1_RESETVALUE 0x00000014UL /**< Default value for PFMXPPRF_RFIMDCDCCTRL1 */ 95 #define _PFMXPPRF_RFIMDCDCCTRL1_MASK 0x0000003FUL /**< Mask for PFMXPPRF_RFIMDCDCCTRL1 */ 96 #define PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVEN (0x1UL << 0) /**< DCDC DIV Enable */ 97 #define _PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVEN_SHIFT 0 /**< Shift value for PFMXPPRF_DCDCDIVEN */ 98 #define _PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVEN_MASK 0x1UL /**< Bit mask for PFMXPPRF_DCDCDIVEN */ 99 #define _PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PFMXPPRF_RFIMDCDCCTRL1 */ 100 #define PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVEN_DEFAULT (_PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVEN_DEFAULT << 0) /**< Shifted mode DEFAULT for PFMXPPRF_RFIMDCDCCTRL1*/ 101 #define PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVINVEN (0x1UL << 1) /**< DCDC DIV Inverter Enable */ 102 #define _PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVINVEN_SHIFT 1 /**< Shift value for PFMXPPRF_DCDCDIVINVEN */ 103 #define _PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVINVEN_MASK 0x2UL /**< Bit mask for PFMXPPRF_DCDCDIVINVEN */ 104 #define _PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVINVEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PFMXPPRF_RFIMDCDCCTRL1 */ 105 #define PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVINVEN_DEFAULT (_PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVINVEN_DEFAULT << 1) /**< Shifted mode DEFAULT for PFMXPPRF_RFIMDCDCCTRL1*/ 106 #define _PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_SHIFT 2 /**< Shift value for PFMXPPRF_DCDCDIVRATIO */ 107 #define _PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_MASK 0x3CUL /**< Bit mask for PFMXPPRF_DCDCDIVRATIO */ 108 #define _PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DEFAULT 0x00000005UL /**< Mode DEFAULT for PFMXPPRF_RFIMDCDCCTRL1 */ 109 #define _PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO8 0x00000000UL /**< Mode DIVRATIO8 for PFMXPPRF_RFIMDCDCCTRL1 */ 110 #define _PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO9 0x00000001UL /**< Mode DIVRATIO9 for PFMXPPRF_RFIMDCDCCTRL1 */ 111 #define _PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO10 0x00000002UL /**< Mode DIVRATIO10 for PFMXPPRF_RFIMDCDCCTRL1 */ 112 #define _PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO11 0x00000003UL /**< Mode DIVRATIO11 for PFMXPPRF_RFIMDCDCCTRL1 */ 113 #define _PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO12 0x00000004UL /**< Mode DIVRATIO12 for PFMXPPRF_RFIMDCDCCTRL1 */ 114 #define _PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO13 0x00000005UL /**< Mode DIVRATIO13 for PFMXPPRF_RFIMDCDCCTRL1 */ 115 #define _PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO14 0x00000006UL /**< Mode DIVRATIO14 for PFMXPPRF_RFIMDCDCCTRL1 */ 116 #define _PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO15 0x00000007UL /**< Mode DIVRATIO15 for PFMXPPRF_RFIMDCDCCTRL1 */ 117 #define _PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO16 0x00000008UL /**< Mode DIVRATIO16 for PFMXPPRF_RFIMDCDCCTRL1 */ 118 #define _PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO17 0x00000009UL /**< Mode DIVRATIO17 for PFMXPPRF_RFIMDCDCCTRL1 */ 119 #define _PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO18 0x0000000AUL /**< Mode DIVRATIO18 for PFMXPPRF_RFIMDCDCCTRL1 */ 120 #define _PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO19 0x0000000BUL /**< Mode DIVRATIO19 for PFMXPPRF_RFIMDCDCCTRL1 */ 121 #define _PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO20 0x0000000CUL /**< Mode DIVRATIO20 for PFMXPPRF_RFIMDCDCCTRL1 */ 122 #define _PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO21 0x0000000DUL /**< Mode DIVRATIO21 for PFMXPPRF_RFIMDCDCCTRL1 */ 123 #define _PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO22 0x0000000EUL /**< Mode DIVRATIO22 for PFMXPPRF_RFIMDCDCCTRL1 */ 124 #define _PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO23 0x0000000FUL /**< Mode DIVRATIO23 for PFMXPPRF_RFIMDCDCCTRL1 */ 125 #define PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DEFAULT (_PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DEFAULT << 2) /**< Shifted mode DEFAULT for PFMXPPRF_RFIMDCDCCTRL1*/ 126 #define PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO8 (_PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO8 << 2) /**< Shifted mode DIVRATIO8 for PFMXPPRF_RFIMDCDCCTRL1*/ 127 #define PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO9 (_PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO9 << 2) /**< Shifted mode DIVRATIO9 for PFMXPPRF_RFIMDCDCCTRL1*/ 128 #define PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO10 (_PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO10 << 2) /**< Shifted mode DIVRATIO10 for PFMXPPRF_RFIMDCDCCTRL1*/ 129 #define PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO11 (_PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO11 << 2) /**< Shifted mode DIVRATIO11 for PFMXPPRF_RFIMDCDCCTRL1*/ 130 #define PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO12 (_PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO12 << 2) /**< Shifted mode DIVRATIO12 for PFMXPPRF_RFIMDCDCCTRL1*/ 131 #define PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO13 (_PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO13 << 2) /**< Shifted mode DIVRATIO13 for PFMXPPRF_RFIMDCDCCTRL1*/ 132 #define PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO14 (_PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO14 << 2) /**< Shifted mode DIVRATIO14 for PFMXPPRF_RFIMDCDCCTRL1*/ 133 #define PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO15 (_PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO15 << 2) /**< Shifted mode DIVRATIO15 for PFMXPPRF_RFIMDCDCCTRL1*/ 134 #define PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO16 (_PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO16 << 2) /**< Shifted mode DIVRATIO16 for PFMXPPRF_RFIMDCDCCTRL1*/ 135 #define PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO17 (_PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO17 << 2) /**< Shifted mode DIVRATIO17 for PFMXPPRF_RFIMDCDCCTRL1*/ 136 #define PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO18 (_PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO18 << 2) /**< Shifted mode DIVRATIO18 for PFMXPPRF_RFIMDCDCCTRL1*/ 137 #define PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO19 (_PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO19 << 2) /**< Shifted mode DIVRATIO19 for PFMXPPRF_RFIMDCDCCTRL1*/ 138 #define PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO20 (_PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO20 << 2) /**< Shifted mode DIVRATIO20 for PFMXPPRF_RFIMDCDCCTRL1*/ 139 #define PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO21 (_PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO21 << 2) /**< Shifted mode DIVRATIO21 for PFMXPPRF_RFIMDCDCCTRL1*/ 140 #define PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO22 (_PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO22 << 2) /**< Shifted mode DIVRATIO22 for PFMXPPRF_RFIMDCDCCTRL1*/ 141 #define PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO23 (_PFMXPPRF_RFIMDCDCCTRL1_DCDCDIVRATIO_DIVRATIO23 << 2) /**< Shifted mode DIVRATIO23 for PFMXPPRF_RFIMDCDCCTRL1*/ 142 143 /* Bit fields for PFMXPPRF RFIMDCDCCTRL2 */ 144 #define _PFMXPPRF_RFIMDCDCCTRL2_RESETVALUE 0x0AD0B4A0UL /**< Default value for PFMXPPRF_RFIMDCDCCTRL2 */ 145 #define _PFMXPPRF_RFIMDCDCCTRL2_MASK 0x9FFFFFFFUL /**< Mask for PFMXPPRF_RFIMDCDCCTRL2 */ 146 #define _PFMXPPRF_RFIMDCDCCTRL2_PPTMAX_SHIFT 0 /**< Shift value for PFMXPPRF_PPTMAX */ 147 #define _PFMXPPRF_RFIMDCDCCTRL2_PPTMAX_MASK 0x1FFUL /**< Bit mask for PFMXPPRF_PPTMAX */ 148 #define _PFMXPPRF_RFIMDCDCCTRL2_PPTMAX_DEFAULT 0x000000A0UL /**< Mode DEFAULT for PFMXPPRF_RFIMDCDCCTRL2 */ 149 #define PFMXPPRF_RFIMDCDCCTRL2_PPTMAX_DEFAULT (_PFMXPPRF_RFIMDCDCCTRL2_PPTMAX_DEFAULT << 0) /**< Shifted mode DEFAULT for PFMXPPRF_RFIMDCDCCTRL2*/ 150 #define _PFMXPPRF_RFIMDCDCCTRL2_PPTMIN_SHIFT 9 /**< Shift value for PFMXPPRF_PPTMIN */ 151 #define _PFMXPPRF_RFIMDCDCCTRL2_PPTMIN_MASK 0x3FE00UL /**< Bit mask for PFMXPPRF_PPTMIN */ 152 #define _PFMXPPRF_RFIMDCDCCTRL2_PPTMIN_DEFAULT 0x0000005AUL /**< Mode DEFAULT for PFMXPPRF_RFIMDCDCCTRL2 */ 153 #define PFMXPPRF_RFIMDCDCCTRL2_PPTMIN_DEFAULT (_PFMXPPRF_RFIMDCDCCTRL2_PPTMIN_DEFAULT << 9) /**< Shifted mode DEFAULT for PFMXPPRF_RFIMDCDCCTRL2*/ 154 #define _PFMXPPRF_RFIMDCDCCTRL2_PPND_SHIFT 18 /**< Shift value for PFMXPPRF_PPND */ 155 #define _PFMXPPRF_RFIMDCDCCTRL2_PPND_MASK 0x7FC0000UL /**< Bit mask for PFMXPPRF_PPND */ 156 #define _PFMXPPRF_RFIMDCDCCTRL2_PPND_DEFAULT 0x000000B4UL /**< Mode DEFAULT for PFMXPPRF_RFIMDCDCCTRL2 */ 157 #define PFMXPPRF_RFIMDCDCCTRL2_PPND_DEFAULT (_PFMXPPRF_RFIMDCDCCTRL2_PPND_DEFAULT << 18) /**< Shifted mode DEFAULT for PFMXPPRF_RFIMDCDCCTRL2*/ 158 #define PFMXPPRF_RFIMDCDCCTRL2_PPCALEN (0x1UL << 27) /**< Pulse Pairing Calibration Loop Enable */ 159 #define _PFMXPPRF_RFIMDCDCCTRL2_PPCALEN_SHIFT 27 /**< Shift value for PFMXPPRF_PPCALEN */ 160 #define _PFMXPPRF_RFIMDCDCCTRL2_PPCALEN_MASK 0x8000000UL /**< Bit mask for PFMXPPRF_PPCALEN */ 161 #define _PFMXPPRF_RFIMDCDCCTRL2_PPCALEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for PFMXPPRF_RFIMDCDCCTRL2 */ 162 #define PFMXPPRF_RFIMDCDCCTRL2_PPCALEN_DEFAULT (_PFMXPPRF_RFIMDCDCCTRL2_PPCALEN_DEFAULT << 27) /**< Shifted mode DEFAULT for PFMXPPRF_RFIMDCDCCTRL2*/ 163 #define PFMXPPRF_RFIMDCDCCTRL2_PPSYNCONLY (0x1UL << 28) /**< Pulse Pairing Sync Only */ 164 #define _PFMXPPRF_RFIMDCDCCTRL2_PPSYNCONLY_SHIFT 28 /**< Shift value for PFMXPPRF_PPSYNCONLY */ 165 #define _PFMXPPRF_RFIMDCDCCTRL2_PPSYNCONLY_MASK 0x10000000UL /**< Bit mask for PFMXPPRF_PPSYNCONLY */ 166 #define _PFMXPPRF_RFIMDCDCCTRL2_PPSYNCONLY_DEFAULT 0x00000000UL /**< Mode DEFAULT for PFMXPPRF_RFIMDCDCCTRL2 */ 167 #define PFMXPPRF_RFIMDCDCCTRL2_PPSYNCONLY_DEFAULT (_PFMXPPRF_RFIMDCDCCTRL2_PPSYNCONLY_DEFAULT << 28) /**< Shifted mode DEFAULT for PFMXPPRF_RFIMDCDCCTRL2*/ 168 169 /* Bit fields for PFMXPPRF RFIMDCDCSTATUS */ 170 #define _PFMXPPRF_RFIMDCDCSTATUS_RESETVALUE 0x00000000UL /**< Default value for PFMXPPRF_RFIMDCDCSTATUS */ 171 #define _PFMXPPRF_RFIMDCDCSTATUS_MASK 0x0001FF07UL /**< Mask for PFMXPPRF_RFIMDCDCSTATUS */ 172 #define PFMXPPRF_RFIMDCDCSTATUS_DCDCEN (0x1UL << 0) /**< DCDC Enable Status */ 173 #define _PFMXPPRF_RFIMDCDCSTATUS_DCDCEN_SHIFT 0 /**< Shift value for PFMXPPRF_DCDCEN */ 174 #define _PFMXPPRF_RFIMDCDCSTATUS_DCDCEN_MASK 0x1UL /**< Bit mask for PFMXPPRF_DCDCEN */ 175 #define _PFMXPPRF_RFIMDCDCSTATUS_DCDCEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PFMXPPRF_RFIMDCDCSTATUS */ 176 #define PFMXPPRF_RFIMDCDCSTATUS_DCDCEN_DEFAULT (_PFMXPPRF_RFIMDCDCSTATUS_DCDCEN_DEFAULT << 0) /**< Shifted mode DEFAULT for PFMXPPRF_RFIMDCDCSTATUS*/ 177 #define PFMXPPRF_RFIMDCDCSTATUS_TXMAXSTATUS (0x1UL << 1) /**< TX MAX Status */ 178 #define _PFMXPPRF_RFIMDCDCSTATUS_TXMAXSTATUS_SHIFT 1 /**< Shift value for PFMXPPRF_TXMAXSTATUS */ 179 #define _PFMXPPRF_RFIMDCDCSTATUS_TXMAXSTATUS_MASK 0x2UL /**< Bit mask for PFMXPPRF_TXMAXSTATUS */ 180 #define _PFMXPPRF_RFIMDCDCSTATUS_TXMAXSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for PFMXPPRF_RFIMDCDCSTATUS */ 181 #define PFMXPPRF_RFIMDCDCSTATUS_TXMAXSTATUS_DEFAULT (_PFMXPPRF_RFIMDCDCSTATUS_TXMAXSTATUS_DEFAULT << 1) /**< Shifted mode DEFAULT for PFMXPPRF_RFIMDCDCSTATUS*/ 182 #define PFMXPPRF_RFIMDCDCSTATUS_RXPPSTATUS (0x1UL << 2) /**< RX PP Status */ 183 #define _PFMXPPRF_RFIMDCDCSTATUS_RXPPSTATUS_SHIFT 2 /**< Shift value for PFMXPPRF_RXPPSTATUS */ 184 #define _PFMXPPRF_RFIMDCDCSTATUS_RXPPSTATUS_MASK 0x4UL /**< Bit mask for PFMXPPRF_RXPPSTATUS */ 185 #define _PFMXPPRF_RFIMDCDCSTATUS_RXPPSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for PFMXPPRF_RFIMDCDCSTATUS */ 186 #define PFMXPPRF_RFIMDCDCSTATUS_RXPPSTATUS_DEFAULT (_PFMXPPRF_RFIMDCDCSTATUS_RXPPSTATUS_DEFAULT << 2) /**< Shifted mode DEFAULT for PFMXPPRF_RFIMDCDCSTATUS*/ 187 #define _PFMXPPRF_RFIMDCDCSTATUS_WNO1_SHIFT 8 /**< Shift value for PFMXPPRF_WNO1 */ 188 #define _PFMXPPRF_RFIMDCDCSTATUS_WNO1_MASK 0x1FF00UL /**< Bit mask for PFMXPPRF_WNO1 */ 189 #define _PFMXPPRF_RFIMDCDCSTATUS_WNO1_DEFAULT 0x00000000UL /**< Mode DEFAULT for PFMXPPRF_RFIMDCDCSTATUS */ 190 #define PFMXPPRF_RFIMDCDCSTATUS_WNO1_DEFAULT (_PFMXPPRF_RFIMDCDCSTATUS_WNO1_DEFAULT << 8) /**< Shifted mode DEFAULT for PFMXPPRF_RFIMDCDCSTATUS*/ 191 192 /* Bit fields for PFMXPPRF RPURATD0 */ 193 #define _PFMXPPRF_RPURATD0_RESETVALUE 0x00000000UL /**< Default value for PFMXPPRF_RPURATD0 */ 194 #define _PFMXPPRF_RPURATD0_MASK 0x00000007UL /**< Mask for PFMXPPRF_RPURATD0 */ 195 #define PFMXPPRF_RPURATD0_RATDRFIMDCDCCTRL0 (0x1UL << 0) /**< RFIMDCDCCTRL0 Protection Bit */ 196 #define _PFMXPPRF_RPURATD0_RATDRFIMDCDCCTRL0_SHIFT 0 /**< Shift value for PFMXPPRF_RATDRFIMDCDCCTRL0 */ 197 #define _PFMXPPRF_RPURATD0_RATDRFIMDCDCCTRL0_MASK 0x1UL /**< Bit mask for PFMXPPRF_RATDRFIMDCDCCTRL0 */ 198 #define _PFMXPPRF_RPURATD0_RATDRFIMDCDCCTRL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for PFMXPPRF_RPURATD0 */ 199 #define PFMXPPRF_RPURATD0_RATDRFIMDCDCCTRL0_DEFAULT (_PFMXPPRF_RPURATD0_RATDRFIMDCDCCTRL0_DEFAULT << 0) /**< Shifted mode DEFAULT for PFMXPPRF_RPURATD0 */ 200 #define PFMXPPRF_RPURATD0_RATDRFIMDCDCCTRL1 (0x1UL << 1) /**< RFIMDCDCCTRL1 Protection Bit */ 201 #define _PFMXPPRF_RPURATD0_RATDRFIMDCDCCTRL1_SHIFT 1 /**< Shift value for PFMXPPRF_RATDRFIMDCDCCTRL1 */ 202 #define _PFMXPPRF_RPURATD0_RATDRFIMDCDCCTRL1_MASK 0x2UL /**< Bit mask for PFMXPPRF_RATDRFIMDCDCCTRL1 */ 203 #define _PFMXPPRF_RPURATD0_RATDRFIMDCDCCTRL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for PFMXPPRF_RPURATD0 */ 204 #define PFMXPPRF_RPURATD0_RATDRFIMDCDCCTRL1_DEFAULT (_PFMXPPRF_RPURATD0_RATDRFIMDCDCCTRL1_DEFAULT << 1) /**< Shifted mode DEFAULT for PFMXPPRF_RPURATD0 */ 205 #define PFMXPPRF_RPURATD0_RATDRFIMDCDCCTRL2 (0x1UL << 2) /**< RFIMDCDCCTRL2 Protection Bit */ 206 #define _PFMXPPRF_RPURATD0_RATDRFIMDCDCCTRL2_SHIFT 2 /**< Shift value for PFMXPPRF_RATDRFIMDCDCCTRL2 */ 207 #define _PFMXPPRF_RPURATD0_RATDRFIMDCDCCTRL2_MASK 0x4UL /**< Bit mask for PFMXPPRF_RATDRFIMDCDCCTRL2 */ 208 #define _PFMXPPRF_RPURATD0_RATDRFIMDCDCCTRL2_DEFAULT 0x00000000UL /**< Mode DEFAULT for PFMXPPRF_RPURATD0 */ 209 #define PFMXPPRF_RPURATD0_RATDRFIMDCDCCTRL2_DEFAULT (_PFMXPPRF_RPURATD0_RATDRFIMDCDCCTRL2_DEFAULT << 2) /**< Shifted mode DEFAULT for PFMXPPRF_RPURATD0 */ 210 211 /** @} End of group EFR32ZG23_PFMXPPRF_BitFields */ 212 /** @} End of group EFR32ZG23_PFMXPPRF */ 213 /** @} End of group Parts */ 214 215 #endif // EFR32ZG23_PFMXPPRF_H 216
