1 /**************************************************************************//** 2 * @file 3 * @brief EFR32MG24 PCNT register and bit field definitions 4 ****************************************************************************** 5 * # License 6 * <b>Copyright 2023 Silicon Laboratories, Inc. www.silabs.com</b> 7 ****************************************************************************** 8 * 9 * SPDX-License-Identifier: Zlib 10 * 11 * The licensor of this software is Silicon Laboratories Inc. 12 * 13 * This software is provided 'as-is', without any express or implied 14 * warranty. In no event will the authors be held liable for any damages 15 * arising from the use of this software. 16 * 17 * Permission is granted to anyone to use this software for any purpose, 18 * including commercial applications, and to alter it and redistribute it 19 * freely, subject to the following restrictions: 20 * 21 * 1. The origin of this software must not be misrepresented; you must not 22 * claim that you wrote the original software. If you use this software 23 * in a product, an acknowledgment in the product documentation would be 24 * appreciated but is not required. 25 * 2. Altered source versions must be plainly marked as such, and must not be 26 * misrepresented as being the original software. 27 * 3. This notice may not be removed or altered from any source distribution. 28 * 29 *****************************************************************************/ 30 #ifndef EFR32MG24_PCNT_H 31 #define EFR32MG24_PCNT_H 32 #define PCNT_HAS_SET_CLEAR 33 34 /**************************************************************************//** 35 * @addtogroup Parts 36 * @{ 37 ******************************************************************************/ 38 /**************************************************************************//** 39 * @defgroup EFR32MG24_PCNT PCNT 40 * @{ 41 * @brief EFR32MG24 PCNT Register Declaration. 42 *****************************************************************************/ 43 44 /** PCNT Register Declaration. */ 45 typedef struct { 46 __IM uint32_t IPVERSION; /**< IP version ID */ 47 __IOM uint32_t EN; /**< Module Enable Register */ 48 __IOM uint32_t SWRST; /**< Software Reset Register */ 49 __IOM uint32_t CFG; /**< Configuration Register */ 50 __IOM uint32_t CTRL; /**< Control Register */ 51 __IOM uint32_t CMD; /**< Command Register */ 52 __IM uint32_t STATUS; /**< Status Register */ 53 __IOM uint32_t IF; /**< Interrupt Flag Register */ 54 __IOM uint32_t IEN; /**< Interrupt Enable Register */ 55 __IM uint32_t CNT; /**< Counter Value Register */ 56 __IM uint32_t AUXCNT; /**< Auxiliary Counter Value Register */ 57 __IOM uint32_t TOP; /**< Top Value Register */ 58 __IOM uint32_t TOPB; /**< Counter Top Value Buffer Register */ 59 __IOM uint32_t OVSCTRL; /**< Oversampling Control Register */ 60 __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */ 61 __IOM uint32_t LOCK; /**< Configuration Lock Register */ 62 uint32_t RESERVED0[1008U]; /**< Reserved for future use */ 63 __IM uint32_t IPVERSION_SET; /**< IP version ID */ 64 __IOM uint32_t EN_SET; /**< Module Enable Register */ 65 __IOM uint32_t SWRST_SET; /**< Software Reset Register */ 66 __IOM uint32_t CFG_SET; /**< Configuration Register */ 67 __IOM uint32_t CTRL_SET; /**< Control Register */ 68 __IOM uint32_t CMD_SET; /**< Command Register */ 69 __IM uint32_t STATUS_SET; /**< Status Register */ 70 __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ 71 __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ 72 __IM uint32_t CNT_SET; /**< Counter Value Register */ 73 __IM uint32_t AUXCNT_SET; /**< Auxiliary Counter Value Register */ 74 __IOM uint32_t TOP_SET; /**< Top Value Register */ 75 __IOM uint32_t TOPB_SET; /**< Counter Top Value Buffer Register */ 76 __IOM uint32_t OVSCTRL_SET; /**< Oversampling Control Register */ 77 __IM uint32_t SYNCBUSY_SET; /**< Synchronization Busy Register */ 78 __IOM uint32_t LOCK_SET; /**< Configuration Lock Register */ 79 uint32_t RESERVED1[1008U]; /**< Reserved for future use */ 80 __IM uint32_t IPVERSION_CLR; /**< IP version ID */ 81 __IOM uint32_t EN_CLR; /**< Module Enable Register */ 82 __IOM uint32_t SWRST_CLR; /**< Software Reset Register */ 83 __IOM uint32_t CFG_CLR; /**< Configuration Register */ 84 __IOM uint32_t CTRL_CLR; /**< Control Register */ 85 __IOM uint32_t CMD_CLR; /**< Command Register */ 86 __IM uint32_t STATUS_CLR; /**< Status Register */ 87 __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ 88 __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ 89 __IM uint32_t CNT_CLR; /**< Counter Value Register */ 90 __IM uint32_t AUXCNT_CLR; /**< Auxiliary Counter Value Register */ 91 __IOM uint32_t TOP_CLR; /**< Top Value Register */ 92 __IOM uint32_t TOPB_CLR; /**< Counter Top Value Buffer Register */ 93 __IOM uint32_t OVSCTRL_CLR; /**< Oversampling Control Register */ 94 __IM uint32_t SYNCBUSY_CLR; /**< Synchronization Busy Register */ 95 __IOM uint32_t LOCK_CLR; /**< Configuration Lock Register */ 96 uint32_t RESERVED2[1008U]; /**< Reserved for future use */ 97 __IM uint32_t IPVERSION_TGL; /**< IP version ID */ 98 __IOM uint32_t EN_TGL; /**< Module Enable Register */ 99 __IOM uint32_t SWRST_TGL; /**< Software Reset Register */ 100 __IOM uint32_t CFG_TGL; /**< Configuration Register */ 101 __IOM uint32_t CTRL_TGL; /**< Control Register */ 102 __IOM uint32_t CMD_TGL; /**< Command Register */ 103 __IM uint32_t STATUS_TGL; /**< Status Register */ 104 __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ 105 __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ 106 __IM uint32_t CNT_TGL; /**< Counter Value Register */ 107 __IM uint32_t AUXCNT_TGL; /**< Auxiliary Counter Value Register */ 108 __IOM uint32_t TOP_TGL; /**< Top Value Register */ 109 __IOM uint32_t TOPB_TGL; /**< Counter Top Value Buffer Register */ 110 __IOM uint32_t OVSCTRL_TGL; /**< Oversampling Control Register */ 111 __IM uint32_t SYNCBUSY_TGL; /**< Synchronization Busy Register */ 112 __IOM uint32_t LOCK_TGL; /**< Configuration Lock Register */ 113 } PCNT_TypeDef; 114 /** @} End of group EFR32MG24_PCNT */ 115 116 /**************************************************************************//** 117 * @addtogroup EFR32MG24_PCNT 118 * @{ 119 * @defgroup EFR32MG24_PCNT_BitFields PCNT Bit Fields 120 * @{ 121 *****************************************************************************/ 122 123 /* Bit fields for PCNT IPVERSION */ 124 #define _PCNT_IPVERSION_RESETVALUE 0x00000001UL /**< Default value for PCNT_IPVERSION */ 125 #define _PCNT_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for PCNT_IPVERSION */ 126 #define _PCNT_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for PCNT_IPVERSION */ 127 #define _PCNT_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for PCNT_IPVERSION */ 128 #define _PCNT_IPVERSION_IPVERSION_DEFAULT 0x00000001UL /**< Mode DEFAULT for PCNT_IPVERSION */ 129 #define PCNT_IPVERSION_IPVERSION_DEFAULT (_PCNT_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_IPVERSION */ 130 131 /* Bit fields for PCNT EN */ 132 #define _PCNT_EN_RESETVALUE 0x00000000UL /**< Default value for PCNT_EN */ 133 #define _PCNT_EN_MASK 0x00000003UL /**< Mask for PCNT_EN */ 134 #define PCNT_EN_EN (0x1UL << 0) /**< PCNT Module Enable */ 135 #define _PCNT_EN_EN_SHIFT 0 /**< Shift value for PCNT_EN */ 136 #define _PCNT_EN_EN_MASK 0x1UL /**< Bit mask for PCNT_EN */ 137 #define _PCNT_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_EN */ 138 #define PCNT_EN_EN_DEFAULT (_PCNT_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_EN */ 139 #define PCNT_EN_DISABLING (0x1UL << 1) /**< Disablement busy status */ 140 #define _PCNT_EN_DISABLING_SHIFT 1 /**< Shift value for PCNT_DISABLING */ 141 #define _PCNT_EN_DISABLING_MASK 0x2UL /**< Bit mask for PCNT_DISABLING */ 142 #define _PCNT_EN_DISABLING_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_EN */ 143 #define PCNT_EN_DISABLING_DEFAULT (_PCNT_EN_DISABLING_DEFAULT << 1) /**< Shifted mode DEFAULT for PCNT_EN */ 144 145 /* Bit fields for PCNT SWRST */ 146 #define _PCNT_SWRST_RESETVALUE 0x00000000UL /**< Default value for PCNT_SWRST */ 147 #define _PCNT_SWRST_MASK 0x00000003UL /**< Mask for PCNT_SWRST */ 148 #define PCNT_SWRST_SWRST (0x1UL << 0) /**< Software reset command */ 149 #define _PCNT_SWRST_SWRST_SHIFT 0 /**< Shift value for PCNT_SWRST */ 150 #define _PCNT_SWRST_SWRST_MASK 0x1UL /**< Bit mask for PCNT_SWRST */ 151 #define _PCNT_SWRST_SWRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_SWRST */ 152 #define PCNT_SWRST_SWRST_DEFAULT (_PCNT_SWRST_SWRST_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_SWRST */ 153 #define PCNT_SWRST_RESETTING (0x1UL << 1) /**< Software reset busy status */ 154 #define _PCNT_SWRST_RESETTING_SHIFT 1 /**< Shift value for PCNT_RESETTING */ 155 #define _PCNT_SWRST_RESETTING_MASK 0x2UL /**< Bit mask for PCNT_RESETTING */ 156 #define _PCNT_SWRST_RESETTING_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_SWRST */ 157 #define PCNT_SWRST_RESETTING_DEFAULT (_PCNT_SWRST_RESETTING_DEFAULT << 1) /**< Shifted mode DEFAULT for PCNT_SWRST */ 158 159 /* Bit fields for PCNT CFG */ 160 #define _PCNT_CFG_RESETVALUE 0x00000000UL /**< Default value for PCNT_CFG */ 161 #define _PCNT_CFG_MASK 0x00000377UL /**< Mask for PCNT_CFG */ 162 #define _PCNT_CFG_MODE_SHIFT 0 /**< Shift value for PCNT_MODE */ 163 #define _PCNT_CFG_MODE_MASK 0x7UL /**< Bit mask for PCNT_MODE */ 164 #define _PCNT_CFG_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CFG */ 165 #define _PCNT_CFG_MODE_OVSSINGLE 0x00000000UL /**< Mode OVSSINGLE for PCNT_CFG */ 166 #define _PCNT_CFG_MODE_EXTCLKSINGLE 0x00000001UL /**< Mode EXTCLKSINGLE for PCNT_CFG */ 167 #define _PCNT_CFG_MODE_EXTCLKQUAD 0x00000002UL /**< Mode EXTCLKQUAD for PCNT_CFG */ 168 #define _PCNT_CFG_MODE_OVSQUAD1X 0x00000003UL /**< Mode OVSQUAD1X for PCNT_CFG */ 169 #define _PCNT_CFG_MODE_OVSQUAD2X 0x00000004UL /**< Mode OVSQUAD2X for PCNT_CFG */ 170 #define _PCNT_CFG_MODE_OVSQUAD4X 0x00000005UL /**< Mode OVSQUAD4X for PCNT_CFG */ 171 #define PCNT_CFG_MODE_DEFAULT (_PCNT_CFG_MODE_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_CFG */ 172 #define PCNT_CFG_MODE_OVSSINGLE (_PCNT_CFG_MODE_OVSSINGLE << 0) /**< Shifted mode OVSSINGLE for PCNT_CFG */ 173 #define PCNT_CFG_MODE_EXTCLKSINGLE (_PCNT_CFG_MODE_EXTCLKSINGLE << 0) /**< Shifted mode EXTCLKSINGLE for PCNT_CFG */ 174 #define PCNT_CFG_MODE_EXTCLKQUAD (_PCNT_CFG_MODE_EXTCLKQUAD << 0) /**< Shifted mode EXTCLKQUAD for PCNT_CFG */ 175 #define PCNT_CFG_MODE_OVSQUAD1X (_PCNT_CFG_MODE_OVSQUAD1X << 0) /**< Shifted mode OVSQUAD1X for PCNT_CFG */ 176 #define PCNT_CFG_MODE_OVSQUAD2X (_PCNT_CFG_MODE_OVSQUAD2X << 0) /**< Shifted mode OVSQUAD2X for PCNT_CFG */ 177 #define PCNT_CFG_MODE_OVSQUAD4X (_PCNT_CFG_MODE_OVSQUAD4X << 0) /**< Shifted mode OVSQUAD4X for PCNT_CFG */ 178 #define PCNT_CFG_DEBUGHALT (0x1UL << 4) /**< Debug Mode Halt Enable */ 179 #define _PCNT_CFG_DEBUGHALT_SHIFT 4 /**< Shift value for PCNT_DEBUGHALT */ 180 #define _PCNT_CFG_DEBUGHALT_MASK 0x10UL /**< Bit mask for PCNT_DEBUGHALT */ 181 #define _PCNT_CFG_DEBUGHALT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CFG */ 182 #define _PCNT_CFG_DEBUGHALT_DISABLE 0x00000000UL /**< Mode DISABLE for PCNT_CFG */ 183 #define _PCNT_CFG_DEBUGHALT_ENABLE 0x00000001UL /**< Mode ENABLE for PCNT_CFG */ 184 #define PCNT_CFG_DEBUGHALT_DEFAULT (_PCNT_CFG_DEBUGHALT_DEFAULT << 4) /**< Shifted mode DEFAULT for PCNT_CFG */ 185 #define PCNT_CFG_DEBUGHALT_DISABLE (_PCNT_CFG_DEBUGHALT_DISABLE << 4) /**< Shifted mode DISABLE for PCNT_CFG */ 186 #define PCNT_CFG_DEBUGHALT_ENABLE (_PCNT_CFG_DEBUGHALT_ENABLE << 4) /**< Shifted mode ENABLE for PCNT_CFG */ 187 #define PCNT_CFG_FILTEN (0x1UL << 5) /**< Enable Digital Pulse Width Filter */ 188 #define _PCNT_CFG_FILTEN_SHIFT 5 /**< Shift value for PCNT_FILTEN */ 189 #define _PCNT_CFG_FILTEN_MASK 0x20UL /**< Bit mask for PCNT_FILTEN */ 190 #define _PCNT_CFG_FILTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CFG */ 191 #define PCNT_CFG_FILTEN_DEFAULT (_PCNT_CFG_FILTEN_DEFAULT << 5) /**< Shifted mode DEFAULT for PCNT_CFG */ 192 #define PCNT_CFG_HYST (0x1UL << 6) /**< Enable Hysteresis */ 193 #define _PCNT_CFG_HYST_SHIFT 6 /**< Shift value for PCNT_HYST */ 194 #define _PCNT_CFG_HYST_MASK 0x40UL /**< Bit mask for PCNT_HYST */ 195 #define _PCNT_CFG_HYST_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CFG */ 196 #define PCNT_CFG_HYST_DEFAULT (_PCNT_CFG_HYST_DEFAULT << 6) /**< Shifted mode DEFAULT for PCNT_CFG */ 197 #define PCNT_CFG_S0PRSEN (0x1UL << 8) /**< S0IN PRS Enable */ 198 #define _PCNT_CFG_S0PRSEN_SHIFT 8 /**< Shift value for PCNT_S0PRSEN */ 199 #define _PCNT_CFG_S0PRSEN_MASK 0x100UL /**< Bit mask for PCNT_S0PRSEN */ 200 #define _PCNT_CFG_S0PRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CFG */ 201 #define PCNT_CFG_S0PRSEN_DEFAULT (_PCNT_CFG_S0PRSEN_DEFAULT << 8) /**< Shifted mode DEFAULT for PCNT_CFG */ 202 #define PCNT_CFG_S1PRSEN (0x1UL << 9) /**< S1IN PRS Enable */ 203 #define _PCNT_CFG_S1PRSEN_SHIFT 9 /**< Shift value for PCNT_S1PRSEN */ 204 #define _PCNT_CFG_S1PRSEN_MASK 0x200UL /**< Bit mask for PCNT_S1PRSEN */ 205 #define _PCNT_CFG_S1PRSEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CFG */ 206 #define PCNT_CFG_S1PRSEN_DEFAULT (_PCNT_CFG_S1PRSEN_DEFAULT << 9) /**< Shifted mode DEFAULT for PCNT_CFG */ 207 208 /* Bit fields for PCNT CTRL */ 209 #define _PCNT_CTRL_RESETVALUE 0x00000000UL /**< Default value for PCNT_CTRL */ 210 #define _PCNT_CTRL_MASK 0x000000F7UL /**< Mask for PCNT_CTRL */ 211 #define PCNT_CTRL_S1CDIR (0x1UL << 0) /**< Count Direction Determined By S1 */ 212 #define _PCNT_CTRL_S1CDIR_SHIFT 0 /**< Shift value for PCNT_S1CDIR */ 213 #define _PCNT_CTRL_S1CDIR_MASK 0x1UL /**< Bit mask for PCNT_S1CDIR */ 214 #define _PCNT_CTRL_S1CDIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */ 215 #define PCNT_CTRL_S1CDIR_DEFAULT (_PCNT_CTRL_S1CDIR_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_CTRL */ 216 #define PCNT_CTRL_CNTDIR (0x1UL << 1) /**< Non-Quadrature Mode Counter Direction Co */ 217 #define _PCNT_CTRL_CNTDIR_SHIFT 1 /**< Shift value for PCNT_CNTDIR */ 218 #define _PCNT_CTRL_CNTDIR_MASK 0x2UL /**< Bit mask for PCNT_CNTDIR */ 219 #define _PCNT_CTRL_CNTDIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */ 220 #define _PCNT_CTRL_CNTDIR_UP 0x00000000UL /**< Mode UP for PCNT_CTRL */ 221 #define _PCNT_CTRL_CNTDIR_DOWN 0x00000001UL /**< Mode DOWN for PCNT_CTRL */ 222 #define PCNT_CTRL_CNTDIR_DEFAULT (_PCNT_CTRL_CNTDIR_DEFAULT << 1) /**< Shifted mode DEFAULT for PCNT_CTRL */ 223 #define PCNT_CTRL_CNTDIR_UP (_PCNT_CTRL_CNTDIR_UP << 1) /**< Shifted mode UP for PCNT_CTRL */ 224 #define PCNT_CTRL_CNTDIR_DOWN (_PCNT_CTRL_CNTDIR_DOWN << 1) /**< Shifted mode DOWN for PCNT_CTRL */ 225 #define PCNT_CTRL_EDGE (0x1UL << 2) /**< Edge Select */ 226 #define _PCNT_CTRL_EDGE_SHIFT 2 /**< Shift value for PCNT_EDGE */ 227 #define _PCNT_CTRL_EDGE_MASK 0x4UL /**< Bit mask for PCNT_EDGE */ 228 #define _PCNT_CTRL_EDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */ 229 #define _PCNT_CTRL_EDGE_POS 0x00000000UL /**< Mode POS for PCNT_CTRL */ 230 #define _PCNT_CTRL_EDGE_NEG 0x00000001UL /**< Mode NEG for PCNT_CTRL */ 231 #define PCNT_CTRL_EDGE_DEFAULT (_PCNT_CTRL_EDGE_DEFAULT << 2) /**< Shifted mode DEFAULT for PCNT_CTRL */ 232 #define PCNT_CTRL_EDGE_POS (_PCNT_CTRL_EDGE_POS << 2) /**< Shifted mode POS for PCNT_CTRL */ 233 #define PCNT_CTRL_EDGE_NEG (_PCNT_CTRL_EDGE_NEG << 2) /**< Shifted mode NEG for PCNT_CTRL */ 234 #define _PCNT_CTRL_CNTEV_SHIFT 4 /**< Shift value for PCNT_CNTEV */ 235 #define _PCNT_CTRL_CNTEV_MASK 0x30UL /**< Bit mask for PCNT_CNTEV */ 236 #define _PCNT_CTRL_CNTEV_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */ 237 #define _PCNT_CTRL_CNTEV_BOTH 0x00000000UL /**< Mode BOTH for PCNT_CTRL */ 238 #define _PCNT_CTRL_CNTEV_UP 0x00000001UL /**< Mode UP for PCNT_CTRL */ 239 #define _PCNT_CTRL_CNTEV_DOWN 0x00000002UL /**< Mode DOWN for PCNT_CTRL */ 240 #define PCNT_CTRL_CNTEV_DEFAULT (_PCNT_CTRL_CNTEV_DEFAULT << 4) /**< Shifted mode DEFAULT for PCNT_CTRL */ 241 #define PCNT_CTRL_CNTEV_BOTH (_PCNT_CTRL_CNTEV_BOTH << 4) /**< Shifted mode BOTH for PCNT_CTRL */ 242 #define PCNT_CTRL_CNTEV_UP (_PCNT_CTRL_CNTEV_UP << 4) /**< Shifted mode UP for PCNT_CTRL */ 243 #define PCNT_CTRL_CNTEV_DOWN (_PCNT_CTRL_CNTEV_DOWN << 4) /**< Shifted mode DOWN for PCNT_CTRL */ 244 #define _PCNT_CTRL_AUXCNTEV_SHIFT 6 /**< Shift value for PCNT_AUXCNTEV */ 245 #define _PCNT_CTRL_AUXCNTEV_MASK 0xC0UL /**< Bit mask for PCNT_AUXCNTEV */ 246 #define _PCNT_CTRL_AUXCNTEV_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CTRL */ 247 #define _PCNT_CTRL_AUXCNTEV_BOTH 0x00000000UL /**< Mode BOTH for PCNT_CTRL */ 248 #define _PCNT_CTRL_AUXCNTEV_UP 0x00000001UL /**< Mode UP for PCNT_CTRL */ 249 #define _PCNT_CTRL_AUXCNTEV_DOWN 0x00000002UL /**< Mode DOWN for PCNT_CTRL */ 250 #define PCNT_CTRL_AUXCNTEV_DEFAULT (_PCNT_CTRL_AUXCNTEV_DEFAULT << 6) /**< Shifted mode DEFAULT for PCNT_CTRL */ 251 #define PCNT_CTRL_AUXCNTEV_BOTH (_PCNT_CTRL_AUXCNTEV_BOTH << 6) /**< Shifted mode BOTH for PCNT_CTRL */ 252 #define PCNT_CTRL_AUXCNTEV_UP (_PCNT_CTRL_AUXCNTEV_UP << 6) /**< Shifted mode UP for PCNT_CTRL */ 253 #define PCNT_CTRL_AUXCNTEV_DOWN (_PCNT_CTRL_AUXCNTEV_DOWN << 6) /**< Shifted mode DOWN for PCNT_CTRL */ 254 255 /* Bit fields for PCNT CMD */ 256 #define _PCNT_CMD_RESETVALUE 0x00000000UL /**< Default value for PCNT_CMD */ 257 #define _PCNT_CMD_MASK 0x00000F17UL /**< Mask for PCNT_CMD */ 258 #define PCNT_CMD_CORERST (0x1UL << 0) /**< PCNT Clock Domain Reset */ 259 #define _PCNT_CMD_CORERST_SHIFT 0 /**< Shift value for PCNT_CORERST */ 260 #define _PCNT_CMD_CORERST_MASK 0x1UL /**< Bit mask for PCNT_CORERST */ 261 #define _PCNT_CMD_CORERST_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CMD */ 262 #define PCNT_CMD_CORERST_DEFAULT (_PCNT_CMD_CORERST_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_CMD */ 263 #define PCNT_CMD_CNTRST (0x1UL << 1) /**< CNT Reset */ 264 #define _PCNT_CMD_CNTRST_SHIFT 1 /**< Shift value for PCNT_CNTRST */ 265 #define _PCNT_CMD_CNTRST_MASK 0x2UL /**< Bit mask for PCNT_CNTRST */ 266 #define _PCNT_CMD_CNTRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CMD */ 267 #define PCNT_CMD_CNTRST_DEFAULT (_PCNT_CMD_CNTRST_DEFAULT << 1) /**< Shifted mode DEFAULT for PCNT_CMD */ 268 #define PCNT_CMD_AUXCNTRST (0x1UL << 2) /**< AUXCNT Reset */ 269 #define _PCNT_CMD_AUXCNTRST_SHIFT 2 /**< Shift value for PCNT_AUXCNTRST */ 270 #define _PCNT_CMD_AUXCNTRST_MASK 0x4UL /**< Bit mask for PCNT_AUXCNTRST */ 271 #define _PCNT_CMD_AUXCNTRST_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CMD */ 272 #define PCNT_CMD_AUXCNTRST_DEFAULT (_PCNT_CMD_AUXCNTRST_DEFAULT << 2) /**< Shifted mode DEFAULT for PCNT_CMD */ 273 #define PCNT_CMD_LCNTIM (0x1UL << 4) /**< Load CNT Immediately */ 274 #define _PCNT_CMD_LCNTIM_SHIFT 4 /**< Shift value for PCNT_LCNTIM */ 275 #define _PCNT_CMD_LCNTIM_MASK 0x10UL /**< Bit mask for PCNT_LCNTIM */ 276 #define _PCNT_CMD_LCNTIM_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CMD */ 277 #define PCNT_CMD_LCNTIM_DEFAULT (_PCNT_CMD_LCNTIM_DEFAULT << 4) /**< Shifted mode DEFAULT for PCNT_CMD */ 278 #define PCNT_CMD_STARTCNT (0x1UL << 8) /**< Start Main Counter */ 279 #define _PCNT_CMD_STARTCNT_SHIFT 8 /**< Shift value for PCNT_STARTCNT */ 280 #define _PCNT_CMD_STARTCNT_MASK 0x100UL /**< Bit mask for PCNT_STARTCNT */ 281 #define _PCNT_CMD_STARTCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CMD */ 282 #define PCNT_CMD_STARTCNT_DEFAULT (_PCNT_CMD_STARTCNT_DEFAULT << 8) /**< Shifted mode DEFAULT for PCNT_CMD */ 283 #define PCNT_CMD_STARTAUXCNT (0x1UL << 9) /**< Start Aux Counter */ 284 #define _PCNT_CMD_STARTAUXCNT_SHIFT 9 /**< Shift value for PCNT_STARTAUXCNT */ 285 #define _PCNT_CMD_STARTAUXCNT_MASK 0x200UL /**< Bit mask for PCNT_STARTAUXCNT */ 286 #define _PCNT_CMD_STARTAUXCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CMD */ 287 #define PCNT_CMD_STARTAUXCNT_DEFAULT (_PCNT_CMD_STARTAUXCNT_DEFAULT << 9) /**< Shifted mode DEFAULT for PCNT_CMD */ 288 #define PCNT_CMD_STOPCNT (0x1UL << 10) /**< Stop Main Counter */ 289 #define _PCNT_CMD_STOPCNT_SHIFT 10 /**< Shift value for PCNT_STOPCNT */ 290 #define _PCNT_CMD_STOPCNT_MASK 0x400UL /**< Bit mask for PCNT_STOPCNT */ 291 #define _PCNT_CMD_STOPCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CMD */ 292 #define PCNT_CMD_STOPCNT_DEFAULT (_PCNT_CMD_STOPCNT_DEFAULT << 10) /**< Shifted mode DEFAULT for PCNT_CMD */ 293 #define PCNT_CMD_STOPAUXCNT (0x1UL << 11) /**< Stop Aux Counter */ 294 #define _PCNT_CMD_STOPAUXCNT_SHIFT 11 /**< Shift value for PCNT_STOPAUXCNT */ 295 #define _PCNT_CMD_STOPAUXCNT_MASK 0x800UL /**< Bit mask for PCNT_STOPAUXCNT */ 296 #define _PCNT_CMD_STOPAUXCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CMD */ 297 #define PCNT_CMD_STOPAUXCNT_DEFAULT (_PCNT_CMD_STOPAUXCNT_DEFAULT << 11) /**< Shifted mode DEFAULT for PCNT_CMD */ 298 299 /* Bit fields for PCNT STATUS */ 300 #define _PCNT_STATUS_RESETVALUE 0x00000000UL /**< Default value for PCNT_STATUS */ 301 #define _PCNT_STATUS_MASK 0x0000001FUL /**< Mask for PCNT_STATUS */ 302 #define PCNT_STATUS_DIR (0x1UL << 0) /**< Current Counter Direction */ 303 #define _PCNT_STATUS_DIR_SHIFT 0 /**< Shift value for PCNT_DIR */ 304 #define _PCNT_STATUS_DIR_MASK 0x1UL /**< Bit mask for PCNT_DIR */ 305 #define _PCNT_STATUS_DIR_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_STATUS */ 306 #define _PCNT_STATUS_DIR_UP 0x00000000UL /**< Mode UP for PCNT_STATUS */ 307 #define _PCNT_STATUS_DIR_DOWN 0x00000001UL /**< Mode DOWN for PCNT_STATUS */ 308 #define PCNT_STATUS_DIR_DEFAULT (_PCNT_STATUS_DIR_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_STATUS */ 309 #define PCNT_STATUS_DIR_UP (_PCNT_STATUS_DIR_UP << 0) /**< Shifted mode UP for PCNT_STATUS */ 310 #define PCNT_STATUS_DIR_DOWN (_PCNT_STATUS_DIR_DOWN << 0) /**< Shifted mode DOWN for PCNT_STATUS */ 311 #define PCNT_STATUS_TOPBV (0x1UL << 1) /**< TOP Buffer Valid */ 312 #define _PCNT_STATUS_TOPBV_SHIFT 1 /**< Shift value for PCNT_TOPBV */ 313 #define _PCNT_STATUS_TOPBV_MASK 0x2UL /**< Bit mask for PCNT_TOPBV */ 314 #define _PCNT_STATUS_TOPBV_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_STATUS */ 315 #define PCNT_STATUS_TOPBV_DEFAULT (_PCNT_STATUS_TOPBV_DEFAULT << 1) /**< Shifted mode DEFAULT for PCNT_STATUS */ 316 #define PCNT_STATUS_PCNTLOCKSTATUS (0x1UL << 2) /**< Lock Status */ 317 #define _PCNT_STATUS_PCNTLOCKSTATUS_SHIFT 2 /**< Shift value for PCNT_PCNTLOCKSTATUS */ 318 #define _PCNT_STATUS_PCNTLOCKSTATUS_MASK 0x4UL /**< Bit mask for PCNT_PCNTLOCKSTATUS */ 319 #define _PCNT_STATUS_PCNTLOCKSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_STATUS */ 320 #define _PCNT_STATUS_PCNTLOCKSTATUS_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for PCNT_STATUS */ 321 #define _PCNT_STATUS_PCNTLOCKSTATUS_LOCKED 0x00000001UL /**< Mode LOCKED for PCNT_STATUS */ 322 #define PCNT_STATUS_PCNTLOCKSTATUS_DEFAULT (_PCNT_STATUS_PCNTLOCKSTATUS_DEFAULT << 2) /**< Shifted mode DEFAULT for PCNT_STATUS */ 323 #define PCNT_STATUS_PCNTLOCKSTATUS_UNLOCKED (_PCNT_STATUS_PCNTLOCKSTATUS_UNLOCKED << 2) /**< Shifted mode UNLOCKED for PCNT_STATUS */ 324 #define PCNT_STATUS_PCNTLOCKSTATUS_LOCKED (_PCNT_STATUS_PCNTLOCKSTATUS_LOCKED << 2) /**< Shifted mode LOCKED for PCNT_STATUS */ 325 #define PCNT_STATUS_CNTRUNNING (0x1UL << 3) /**< Main Counter running status */ 326 #define _PCNT_STATUS_CNTRUNNING_SHIFT 3 /**< Shift value for PCNT_CNTRUNNING */ 327 #define _PCNT_STATUS_CNTRUNNING_MASK 0x8UL /**< Bit mask for PCNT_CNTRUNNING */ 328 #define _PCNT_STATUS_CNTRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_STATUS */ 329 #define PCNT_STATUS_CNTRUNNING_DEFAULT (_PCNT_STATUS_CNTRUNNING_DEFAULT << 3) /**< Shifted mode DEFAULT for PCNT_STATUS */ 330 #define PCNT_STATUS_AUXCNTRUNNING (0x1UL << 4) /**< Aux Counter running status */ 331 #define _PCNT_STATUS_AUXCNTRUNNING_SHIFT 4 /**< Shift value for PCNT_AUXCNTRUNNING */ 332 #define _PCNT_STATUS_AUXCNTRUNNING_MASK 0x10UL /**< Bit mask for PCNT_AUXCNTRUNNING */ 333 #define _PCNT_STATUS_AUXCNTRUNNING_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_STATUS */ 334 #define PCNT_STATUS_AUXCNTRUNNING_DEFAULT (_PCNT_STATUS_AUXCNTRUNNING_DEFAULT << 4) /**< Shifted mode DEFAULT for PCNT_STATUS */ 335 336 /* Bit fields for PCNT IF */ 337 #define _PCNT_IF_RESETVALUE 0x00000000UL /**< Default value for PCNT_IF */ 338 #define _PCNT_IF_MASK 0x0000001FUL /**< Mask for PCNT_IF */ 339 #define PCNT_IF_UF (0x1UL << 0) /**< Underflow Interrupt Read Flag */ 340 #define _PCNT_IF_UF_SHIFT 0 /**< Shift value for PCNT_UF */ 341 #define _PCNT_IF_UF_MASK 0x1UL /**< Bit mask for PCNT_UF */ 342 #define _PCNT_IF_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IF */ 343 #define PCNT_IF_UF_DEFAULT (_PCNT_IF_UF_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_IF */ 344 #define PCNT_IF_OF (0x1UL << 1) /**< Overflow Interrupt Read Flag */ 345 #define _PCNT_IF_OF_SHIFT 1 /**< Shift value for PCNT_OF */ 346 #define _PCNT_IF_OF_MASK 0x2UL /**< Bit mask for PCNT_OF */ 347 #define _PCNT_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IF */ 348 #define PCNT_IF_OF_DEFAULT (_PCNT_IF_OF_DEFAULT << 1) /**< Shifted mode DEFAULT for PCNT_IF */ 349 #define PCNT_IF_DIRCNG (0x1UL << 2) /**< Direction Change Detect Interrupt Flag */ 350 #define _PCNT_IF_DIRCNG_SHIFT 2 /**< Shift value for PCNT_DIRCNG */ 351 #define _PCNT_IF_DIRCNG_MASK 0x4UL /**< Bit mask for PCNT_DIRCNG */ 352 #define _PCNT_IF_DIRCNG_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IF */ 353 #define PCNT_IF_DIRCNG_DEFAULT (_PCNT_IF_DIRCNG_DEFAULT << 2) /**< Shifted mode DEFAULT for PCNT_IF */ 354 #define PCNT_IF_AUXOF (0x1UL << 3) /**< Auxiliary Overflow Interrupt Read Flag */ 355 #define _PCNT_IF_AUXOF_SHIFT 3 /**< Shift value for PCNT_AUXOF */ 356 #define _PCNT_IF_AUXOF_MASK 0x8UL /**< Bit mask for PCNT_AUXOF */ 357 #define _PCNT_IF_AUXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IF */ 358 #define PCNT_IF_AUXOF_DEFAULT (_PCNT_IF_AUXOF_DEFAULT << 3) /**< Shifted mode DEFAULT for PCNT_IF */ 359 #define PCNT_IF_OQSTERR (0x1UL << 4) /**< Oversampling Quad State Err Int Flag */ 360 #define _PCNT_IF_OQSTERR_SHIFT 4 /**< Shift value for PCNT_OQSTERR */ 361 #define _PCNT_IF_OQSTERR_MASK 0x10UL /**< Bit mask for PCNT_OQSTERR */ 362 #define _PCNT_IF_OQSTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IF */ 363 #define PCNT_IF_OQSTERR_DEFAULT (_PCNT_IF_OQSTERR_DEFAULT << 4) /**< Shifted mode DEFAULT for PCNT_IF */ 364 365 /* Bit fields for PCNT IEN */ 366 #define _PCNT_IEN_RESETVALUE 0x00000000UL /**< Default value for PCNT_IEN */ 367 #define _PCNT_IEN_MASK 0x0000001FUL /**< Mask for PCNT_IEN */ 368 #define PCNT_IEN_UF (0x1UL << 0) /**< Underflow Interrupt Read Flag */ 369 #define _PCNT_IEN_UF_SHIFT 0 /**< Shift value for PCNT_UF */ 370 #define _PCNT_IEN_UF_MASK 0x1UL /**< Bit mask for PCNT_UF */ 371 #define _PCNT_IEN_UF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IEN */ 372 #define PCNT_IEN_UF_DEFAULT (_PCNT_IEN_UF_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_IEN */ 373 #define PCNT_IEN_OF (0x1UL << 1) /**< Overflow Interrupt Read Flag */ 374 #define _PCNT_IEN_OF_SHIFT 1 /**< Shift value for PCNT_OF */ 375 #define _PCNT_IEN_OF_MASK 0x2UL /**< Bit mask for PCNT_OF */ 376 #define _PCNT_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IEN */ 377 #define PCNT_IEN_OF_DEFAULT (_PCNT_IEN_OF_DEFAULT << 1) /**< Shifted mode DEFAULT for PCNT_IEN */ 378 #define PCNT_IEN_DIRCNG (0x1UL << 2) /**< Direction Change Detect Interrupt Flag */ 379 #define _PCNT_IEN_DIRCNG_SHIFT 2 /**< Shift value for PCNT_DIRCNG */ 380 #define _PCNT_IEN_DIRCNG_MASK 0x4UL /**< Bit mask for PCNT_DIRCNG */ 381 #define _PCNT_IEN_DIRCNG_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IEN */ 382 #define PCNT_IEN_DIRCNG_DEFAULT (_PCNT_IEN_DIRCNG_DEFAULT << 2) /**< Shifted mode DEFAULT for PCNT_IEN */ 383 #define PCNT_IEN_AUXOF (0x1UL << 3) /**< Auxiliary Overflow Interrupt Read Flag */ 384 #define _PCNT_IEN_AUXOF_SHIFT 3 /**< Shift value for PCNT_AUXOF */ 385 #define _PCNT_IEN_AUXOF_MASK 0x8UL /**< Bit mask for PCNT_AUXOF */ 386 #define _PCNT_IEN_AUXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IEN */ 387 #define PCNT_IEN_AUXOF_DEFAULT (_PCNT_IEN_AUXOF_DEFAULT << 3) /**< Shifted mode DEFAULT for PCNT_IEN */ 388 #define PCNT_IEN_OQSTERR (0x1UL << 4) /**< Oversampling Quad State Err Int Flag */ 389 #define _PCNT_IEN_OQSTERR_SHIFT 4 /**< Shift value for PCNT_OQSTERR */ 390 #define _PCNT_IEN_OQSTERR_MASK 0x10UL /**< Bit mask for PCNT_OQSTERR */ 391 #define _PCNT_IEN_OQSTERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_IEN */ 392 #define PCNT_IEN_OQSTERR_DEFAULT (_PCNT_IEN_OQSTERR_DEFAULT << 4) /**< Shifted mode DEFAULT for PCNT_IEN */ 393 394 /* Bit fields for PCNT CNT */ 395 #define _PCNT_CNT_RESETVALUE 0x00000000UL /**< Default value for PCNT_CNT */ 396 #define _PCNT_CNT_MASK 0x0000FFFFUL /**< Mask for PCNT_CNT */ 397 #define _PCNT_CNT_CNT_SHIFT 0 /**< Shift value for PCNT_CNT */ 398 #define _PCNT_CNT_CNT_MASK 0xFFFFUL /**< Bit mask for PCNT_CNT */ 399 #define _PCNT_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_CNT */ 400 #define PCNT_CNT_CNT_DEFAULT (_PCNT_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_CNT */ 401 402 /* Bit fields for PCNT AUXCNT */ 403 #define _PCNT_AUXCNT_RESETVALUE 0x00000000UL /**< Default value for PCNT_AUXCNT */ 404 #define _PCNT_AUXCNT_MASK 0x0000FFFFUL /**< Mask for PCNT_AUXCNT */ 405 #define _PCNT_AUXCNT_AUXCNT_SHIFT 0 /**< Shift value for PCNT_AUXCNT */ 406 #define _PCNT_AUXCNT_AUXCNT_MASK 0xFFFFUL /**< Bit mask for PCNT_AUXCNT */ 407 #define _PCNT_AUXCNT_AUXCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_AUXCNT */ 408 #define PCNT_AUXCNT_AUXCNT_DEFAULT (_PCNT_AUXCNT_AUXCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_AUXCNT */ 409 410 /* Bit fields for PCNT TOP */ 411 #define _PCNT_TOP_RESETVALUE 0x000000FFUL /**< Default value for PCNT_TOP */ 412 #define _PCNT_TOP_MASK 0x0000FFFFUL /**< Mask for PCNT_TOP */ 413 #define _PCNT_TOP_TOP_SHIFT 0 /**< Shift value for PCNT_TOP */ 414 #define _PCNT_TOP_TOP_MASK 0xFFFFUL /**< Bit mask for PCNT_TOP */ 415 #define _PCNT_TOP_TOP_DEFAULT 0x000000FFUL /**< Mode DEFAULT for PCNT_TOP */ 416 #define PCNT_TOP_TOP_DEFAULT (_PCNT_TOP_TOP_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_TOP */ 417 418 /* Bit fields for PCNT TOPB */ 419 #define _PCNT_TOPB_RESETVALUE 0x000000FFUL /**< Default value for PCNT_TOPB */ 420 #define _PCNT_TOPB_MASK 0x0000FFFFUL /**< Mask for PCNT_TOPB */ 421 #define _PCNT_TOPB_TOPB_SHIFT 0 /**< Shift value for PCNT_TOPB */ 422 #define _PCNT_TOPB_TOPB_MASK 0xFFFFUL /**< Bit mask for PCNT_TOPB */ 423 #define _PCNT_TOPB_TOPB_DEFAULT 0x000000FFUL /**< Mode DEFAULT for PCNT_TOPB */ 424 #define PCNT_TOPB_TOPB_DEFAULT (_PCNT_TOPB_TOPB_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_TOPB */ 425 426 /* Bit fields for PCNT OVSCTRL */ 427 #define _PCNT_OVSCTRL_RESETVALUE 0x00000000UL /**< Default value for PCNT_OVSCTRL */ 428 #define _PCNT_OVSCTRL_MASK 0x000010FFUL /**< Mask for PCNT_OVSCTRL */ 429 #define _PCNT_OVSCTRL_FILTLEN_SHIFT 0 /**< Shift value for PCNT_FILTLEN */ 430 #define _PCNT_OVSCTRL_FILTLEN_MASK 0xFFUL /**< Bit mask for PCNT_FILTLEN */ 431 #define _PCNT_OVSCTRL_FILTLEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_OVSCTRL */ 432 #define PCNT_OVSCTRL_FILTLEN_DEFAULT (_PCNT_OVSCTRL_FILTLEN_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_OVSCTRL */ 433 #define PCNT_OVSCTRL_FLUTTERRM (0x1UL << 12) /**< Flutter Remove */ 434 #define _PCNT_OVSCTRL_FLUTTERRM_SHIFT 12 /**< Shift value for PCNT_FLUTTERRM */ 435 #define _PCNT_OVSCTRL_FLUTTERRM_MASK 0x1000UL /**< Bit mask for PCNT_FLUTTERRM */ 436 #define _PCNT_OVSCTRL_FLUTTERRM_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_OVSCTRL */ 437 #define PCNT_OVSCTRL_FLUTTERRM_DEFAULT (_PCNT_OVSCTRL_FLUTTERRM_DEFAULT << 12) /**< Shifted mode DEFAULT for PCNT_OVSCTRL */ 438 439 /* Bit fields for PCNT SYNCBUSY */ 440 #define _PCNT_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for PCNT_SYNCBUSY */ 441 #define _PCNT_SYNCBUSY_MASK 0x0000001FUL /**< Mask for PCNT_SYNCBUSY */ 442 #define PCNT_SYNCBUSY_CTRL (0x1UL << 0) /**< CTRL Register Busy */ 443 #define _PCNT_SYNCBUSY_CTRL_SHIFT 0 /**< Shift value for PCNT_CTRL */ 444 #define _PCNT_SYNCBUSY_CTRL_MASK 0x1UL /**< Bit mask for PCNT_CTRL */ 445 #define _PCNT_SYNCBUSY_CTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_SYNCBUSY */ 446 #define PCNT_SYNCBUSY_CTRL_DEFAULT (_PCNT_SYNCBUSY_CTRL_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_SYNCBUSY */ 447 #define PCNT_SYNCBUSY_CMD (0x1UL << 1) /**< CMD Register Busy */ 448 #define _PCNT_SYNCBUSY_CMD_SHIFT 1 /**< Shift value for PCNT_CMD */ 449 #define _PCNT_SYNCBUSY_CMD_MASK 0x2UL /**< Bit mask for PCNT_CMD */ 450 #define _PCNT_SYNCBUSY_CMD_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_SYNCBUSY */ 451 #define PCNT_SYNCBUSY_CMD_DEFAULT (_PCNT_SYNCBUSY_CMD_DEFAULT << 1) /**< Shifted mode DEFAULT for PCNT_SYNCBUSY */ 452 #define PCNT_SYNCBUSY_TOP (0x1UL << 2) /**< TOP Register Busy */ 453 #define _PCNT_SYNCBUSY_TOP_SHIFT 2 /**< Shift value for PCNT_TOP */ 454 #define _PCNT_SYNCBUSY_TOP_MASK 0x4UL /**< Bit mask for PCNT_TOP */ 455 #define _PCNT_SYNCBUSY_TOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_SYNCBUSY */ 456 #define PCNT_SYNCBUSY_TOP_DEFAULT (_PCNT_SYNCBUSY_TOP_DEFAULT << 2) /**< Shifted mode DEFAULT for PCNT_SYNCBUSY */ 457 #define PCNT_SYNCBUSY_TOPB (0x1UL << 3) /**< TOPB Register Busy */ 458 #define _PCNT_SYNCBUSY_TOPB_SHIFT 3 /**< Shift value for PCNT_TOPB */ 459 #define _PCNT_SYNCBUSY_TOPB_MASK 0x8UL /**< Bit mask for PCNT_TOPB */ 460 #define _PCNT_SYNCBUSY_TOPB_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_SYNCBUSY */ 461 #define PCNT_SYNCBUSY_TOPB_DEFAULT (_PCNT_SYNCBUSY_TOPB_DEFAULT << 3) /**< Shifted mode DEFAULT for PCNT_SYNCBUSY */ 462 #define PCNT_SYNCBUSY_OVSCTRL (0x1UL << 4) /**< OVSCTRL Register Busy */ 463 #define _PCNT_SYNCBUSY_OVSCTRL_SHIFT 4 /**< Shift value for PCNT_OVSCTRL */ 464 #define _PCNT_SYNCBUSY_OVSCTRL_MASK 0x10UL /**< Bit mask for PCNT_OVSCTRL */ 465 #define _PCNT_SYNCBUSY_OVSCTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_SYNCBUSY */ 466 #define PCNT_SYNCBUSY_OVSCTRL_DEFAULT (_PCNT_SYNCBUSY_OVSCTRL_DEFAULT << 4) /**< Shifted mode DEFAULT for PCNT_SYNCBUSY */ 467 468 /* Bit fields for PCNT LOCK */ 469 #define _PCNT_LOCK_RESETVALUE 0x00000000UL /**< Default value for PCNT_LOCK */ 470 #define _PCNT_LOCK_MASK 0x0000FFFFUL /**< Mask for PCNT_LOCK */ 471 #define _PCNT_LOCK_PCNTLOCKKEY_SHIFT 0 /**< Shift value for PCNT_PCNTLOCKKEY */ 472 #define _PCNT_LOCK_PCNTLOCKKEY_MASK 0xFFFFUL /**< Bit mask for PCNT_PCNTLOCKKEY */ 473 #define _PCNT_LOCK_PCNTLOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for PCNT_LOCK */ 474 #define _PCNT_LOCK_PCNTLOCKKEY_UNLOCK 0x0000A7E0UL /**< Mode UNLOCK for PCNT_LOCK */ 475 #define PCNT_LOCK_PCNTLOCKKEY_DEFAULT (_PCNT_LOCK_PCNTLOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for PCNT_LOCK */ 476 #define PCNT_LOCK_PCNTLOCKKEY_UNLOCK (_PCNT_LOCK_PCNTLOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for PCNT_LOCK */ 477 478 /** @} End of group EFR32MG24_PCNT_BitFields */ 479 /** @} End of group EFR32MG24_PCNT */ 480 /** @} End of group Parts */ 481 482 #endif /* EFR32MG24_PCNT_H */ 483
