1 /**************************************************************************//** 2 * @file 3 * @brief EFR32MG24 MAILBOX register and bit field definitions 4 ****************************************************************************** 5 * # License 6 * <b>Copyright 2022 Silicon Laboratories, Inc. www.silabs.com</b> 7 ****************************************************************************** 8 * 9 * SPDX-License-Identifier: Zlib 10 * 11 * The licensor of this software is Silicon Laboratories Inc. 12 * 13 * This software is provided 'as-is', without any express or implied 14 * warranty. In no event will the authors be held liable for any damages 15 * arising from the use of this software. 16 * 17 * Permission is granted to anyone to use this software for any purpose, 18 * including commercial applications, and to alter it and redistribute it 19 * freely, subject to the following restrictions: 20 * 21 * 1. The origin of this software must not be misrepresented; you must not 22 * claim that you wrote the original software. If you use this software 23 * in a product, an acknowledgment in the product documentation would be 24 * appreciated but is not required. 25 * 2. Altered source versions must be plainly marked as such, and must not be 26 * misrepresented as being the original software. 27 * 3. This notice may not be removed or altered from any source distribution. 28 * 29 *****************************************************************************/ 30 #ifndef EFR32MG24_MAILBOX_H 31 #define EFR32MG24_MAILBOX_H 32 #define MAILBOX_HAS_SET_CLEAR 33 34 /**************************************************************************//** 35 * @addtogroup Parts 36 * @{ 37 ******************************************************************************/ 38 /**************************************************************************//** 39 * @defgroup EFR32MG24_MAILBOX MAILBOX 40 * @{ 41 * @brief EFR32MG24 MAILBOX Register Declaration. 42 *****************************************************************************/ 43 44 /** MAILBOX MSGPTRS Register Group Declaration. */ 45 typedef struct { 46 __IOM uint32_t MSGPTR; /**< Message Pointer */ 47 } MAILBOX_MSGPTRS_TypeDef; 48 49 /** MAILBOX Register Declaration. */ 50 typedef struct { 51 MAILBOX_MSGPTRS_TypeDef MSGPTRS[4U]; /**< Message Pointers */ 52 uint32_t RESERVED0[12U]; /**< Reserved for future use */ 53 __IOM uint32_t IF; /**< Interrupt Flag register */ 54 __IOM uint32_t IEN; /**< Interrupt Enable register */ 55 uint32_t RESERVED1[1006U]; /**< Reserved for future use */ 56 MAILBOX_MSGPTRS_TypeDef MSGPTRS_SET[4U]; /**< Message Pointers */ 57 uint32_t RESERVED2[12U]; /**< Reserved for future use */ 58 __IOM uint32_t IF_SET; /**< Interrupt Flag register */ 59 __IOM uint32_t IEN_SET; /**< Interrupt Enable register */ 60 uint32_t RESERVED3[1006U]; /**< Reserved for future use */ 61 MAILBOX_MSGPTRS_TypeDef MSGPTRS_CLR[4U]; /**< Message Pointers */ 62 uint32_t RESERVED4[12U]; /**< Reserved for future use */ 63 __IOM uint32_t IF_CLR; /**< Interrupt Flag register */ 64 __IOM uint32_t IEN_CLR; /**< Interrupt Enable register */ 65 uint32_t RESERVED5[1006U]; /**< Reserved for future use */ 66 MAILBOX_MSGPTRS_TypeDef MSGPTRS_TGL[4U]; /**< Message Pointers */ 67 uint32_t RESERVED6[12U]; /**< Reserved for future use */ 68 __IOM uint32_t IF_TGL; /**< Interrupt Flag register */ 69 __IOM uint32_t IEN_TGL; /**< Interrupt Enable register */ 70 } MAILBOX_TypeDef; 71 /** @} End of group EFR32MG24_MAILBOX */ 72 73 /**************************************************************************//** 74 * @addtogroup EFR32MG24_MAILBOX 75 * @{ 76 * @defgroup EFR32MG24_MAILBOX_BitFields MAILBOX Bit Fields 77 * @{ 78 *****************************************************************************/ 79 80 /* Bit fields for MAILBOX MSGPTR */ 81 #define _MAILBOX_MSGPTR_RESETVALUE 0x00000000UL /**< Default value for MAILBOX_MSGPTR */ 82 #define _MAILBOX_MSGPTR_MASK 0xFFFFFFFFUL /**< Mask for MAILBOX_MSGPTR */ 83 #define _MAILBOX_MSGPTR_PTR_SHIFT 0 /**< Shift value for MAILBOX_PTR */ 84 #define _MAILBOX_MSGPTR_PTR_MASK 0xFFFFFFFFUL /**< Bit mask for MAILBOX_PTR */ 85 #define _MAILBOX_MSGPTR_PTR_DEFAULT 0x00000000UL /**< Mode DEFAULT for MAILBOX_MSGPTR */ 86 #define MAILBOX_MSGPTR_PTR_DEFAULT (_MAILBOX_MSGPTR_PTR_DEFAULT << 0) /**< Shifted mode DEFAULT for MAILBOX_MSGPTR */ 87 88 /* Bit fields for MAILBOX IF */ 89 #define _MAILBOX_IF_RESETVALUE 0x00000000UL /**< Default value for MAILBOX_IF */ 90 #define _MAILBOX_IF_MASK 0x0000000FUL /**< Mask for MAILBOX_IF */ 91 #define MAILBOX_IF_MBOXIF0 (0x1UL << 0) /**< Mailbox Interupt Flag */ 92 #define _MAILBOX_IF_MBOXIF0_SHIFT 0 /**< Shift value for MAILBOX_MBOXIF0 */ 93 #define _MAILBOX_IF_MBOXIF0_MASK 0x1UL /**< Bit mask for MAILBOX_MBOXIF0 */ 94 #define _MAILBOX_IF_MBOXIF0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MAILBOX_IF */ 95 #define MAILBOX_IF_MBOXIF0_DEFAULT (_MAILBOX_IF_MBOXIF0_DEFAULT << 0) /**< Shifted mode DEFAULT for MAILBOX_IF */ 96 #define MAILBOX_IF_MBOXIF1 (0x1UL << 1) /**< Mailbox Interupt Flag */ 97 #define _MAILBOX_IF_MBOXIF1_SHIFT 1 /**< Shift value for MAILBOX_MBOXIF1 */ 98 #define _MAILBOX_IF_MBOXIF1_MASK 0x2UL /**< Bit mask for MAILBOX_MBOXIF1 */ 99 #define _MAILBOX_IF_MBOXIF1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MAILBOX_IF */ 100 #define MAILBOX_IF_MBOXIF1_DEFAULT (_MAILBOX_IF_MBOXIF1_DEFAULT << 1) /**< Shifted mode DEFAULT for MAILBOX_IF */ 101 #define MAILBOX_IF_MBOXIF2 (0x1UL << 2) /**< Mailbox Interupt Flag */ 102 #define _MAILBOX_IF_MBOXIF2_SHIFT 2 /**< Shift value for MAILBOX_MBOXIF2 */ 103 #define _MAILBOX_IF_MBOXIF2_MASK 0x4UL /**< Bit mask for MAILBOX_MBOXIF2 */ 104 #define _MAILBOX_IF_MBOXIF2_DEFAULT 0x00000000UL /**< Mode DEFAULT for MAILBOX_IF */ 105 #define MAILBOX_IF_MBOXIF2_DEFAULT (_MAILBOX_IF_MBOXIF2_DEFAULT << 2) /**< Shifted mode DEFAULT for MAILBOX_IF */ 106 #define MAILBOX_IF_MBOXIF3 (0x1UL << 3) /**< Mailbox Interupt Flag */ 107 #define _MAILBOX_IF_MBOXIF3_SHIFT 3 /**< Shift value for MAILBOX_MBOXIF3 */ 108 #define _MAILBOX_IF_MBOXIF3_MASK 0x8UL /**< Bit mask for MAILBOX_MBOXIF3 */ 109 #define _MAILBOX_IF_MBOXIF3_DEFAULT 0x00000000UL /**< Mode DEFAULT for MAILBOX_IF */ 110 #define MAILBOX_IF_MBOXIF3_DEFAULT (_MAILBOX_IF_MBOXIF3_DEFAULT << 3) /**< Shifted mode DEFAULT for MAILBOX_IF */ 111 112 /* Bit fields for MAILBOX IEN */ 113 #define _MAILBOX_IEN_RESETVALUE 0x00000000UL /**< Default value for MAILBOX_IEN */ 114 #define _MAILBOX_IEN_MASK 0x0000000FUL /**< Mask for MAILBOX_IEN */ 115 #define MAILBOX_IEN_MBOXIEN0 (0x1UL << 0) /**< Mailbox Interrupt Enable */ 116 #define _MAILBOX_IEN_MBOXIEN0_SHIFT 0 /**< Shift value for MAILBOX_MBOXIEN0 */ 117 #define _MAILBOX_IEN_MBOXIEN0_MASK 0x1UL /**< Bit mask for MAILBOX_MBOXIEN0 */ 118 #define _MAILBOX_IEN_MBOXIEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for MAILBOX_IEN */ 119 #define MAILBOX_IEN_MBOXIEN0_DEFAULT (_MAILBOX_IEN_MBOXIEN0_DEFAULT << 0) /**< Shifted mode DEFAULT for MAILBOX_IEN */ 120 #define MAILBOX_IEN_MBOXIEN1 (0x1UL << 1) /**< Mailbox Interrupt Enable */ 121 #define _MAILBOX_IEN_MBOXIEN1_SHIFT 1 /**< Shift value for MAILBOX_MBOXIEN1 */ 122 #define _MAILBOX_IEN_MBOXIEN1_MASK 0x2UL /**< Bit mask for MAILBOX_MBOXIEN1 */ 123 #define _MAILBOX_IEN_MBOXIEN1_DEFAULT 0x00000000UL /**< Mode DEFAULT for MAILBOX_IEN */ 124 #define MAILBOX_IEN_MBOXIEN1_DEFAULT (_MAILBOX_IEN_MBOXIEN1_DEFAULT << 1) /**< Shifted mode DEFAULT for MAILBOX_IEN */ 125 #define MAILBOX_IEN_MBOXIEN2 (0x1UL << 2) /**< Mailbox Interrupt Enable */ 126 #define _MAILBOX_IEN_MBOXIEN2_SHIFT 2 /**< Shift value for MAILBOX_MBOXIEN2 */ 127 #define _MAILBOX_IEN_MBOXIEN2_MASK 0x4UL /**< Bit mask for MAILBOX_MBOXIEN2 */ 128 #define _MAILBOX_IEN_MBOXIEN2_DEFAULT 0x00000000UL /**< Mode DEFAULT for MAILBOX_IEN */ 129 #define MAILBOX_IEN_MBOXIEN2_DEFAULT (_MAILBOX_IEN_MBOXIEN2_DEFAULT << 2) /**< Shifted mode DEFAULT for MAILBOX_IEN */ 130 #define MAILBOX_IEN_MBOXIEN3 (0x1UL << 3) /**< Mailbox Interrupt Enable */ 131 #define _MAILBOX_IEN_MBOXIEN3_SHIFT 3 /**< Shift value for MAILBOX_MBOXIEN3 */ 132 #define _MAILBOX_IEN_MBOXIEN3_MASK 0x8UL /**< Bit mask for MAILBOX_MBOXIEN3 */ 133 #define _MAILBOX_IEN_MBOXIEN3_DEFAULT 0x00000000UL /**< Mode DEFAULT for MAILBOX_IEN */ 134 #define MAILBOX_IEN_MBOXIEN3_DEFAULT (_MAILBOX_IEN_MBOXIEN3_DEFAULT << 3) /**< Shifted mode DEFAULT for MAILBOX_IEN */ 135 136 /** @} End of group EFR32MG24_MAILBOX_BitFields */ 137 /** @} End of group EFR32MG24_MAILBOX */ 138 /** @} End of group Parts */ 139 140 #endif /* EFR32MG24_MAILBOX_H */ 141
