1 /**************************************************************************//** 2 * @file 3 * @brief EFR32MG24 LFXO register and bit field definitions 4 ****************************************************************************** 5 * # License 6 * <b>Copyright 2022 Silicon Laboratories, Inc. www.silabs.com</b> 7 ****************************************************************************** 8 * 9 * SPDX-License-Identifier: Zlib 10 * 11 * The licensor of this software is Silicon Laboratories Inc. 12 * 13 * This software is provided 'as-is', without any express or implied 14 * warranty. In no event will the authors be held liable for any damages 15 * arising from the use of this software. 16 * 17 * Permission is granted to anyone to use this software for any purpose, 18 * including commercial applications, and to alter it and redistribute it 19 * freely, subject to the following restrictions: 20 * 21 * 1. The origin of this software must not be misrepresented; you must not 22 * claim that you wrote the original software. If you use this software 23 * in a product, an acknowledgment in the product documentation would be 24 * appreciated but is not required. 25 * 2. Altered source versions must be plainly marked as such, and must not be 26 * misrepresented as being the original software. 27 * 3. This notice may not be removed or altered from any source distribution. 28 * 29 *****************************************************************************/ 30 #ifndef EFR32MG24_LFXO_H 31 #define EFR32MG24_LFXO_H 32 #define LFXO_HAS_SET_CLEAR 33 34 /**************************************************************************//** 35 * @addtogroup Parts 36 * @{ 37 ******************************************************************************/ 38 /**************************************************************************//** 39 * @defgroup EFR32MG24_LFXO LFXO 40 * @{ 41 * @brief EFR32MG24 LFXO Register Declaration. 42 *****************************************************************************/ 43 44 /** LFXO Register Declaration. */ 45 typedef struct { 46 __IM uint32_t IPVERSION; /**< LFXO IP version */ 47 __IOM uint32_t CTRL; /**< LFXO Control Register */ 48 __IOM uint32_t CFG; /**< LFXO Configuration Register */ 49 uint32_t RESERVED0[1U]; /**< Reserved for future use */ 50 __IM uint32_t STATUS; /**< LFXO Status Register */ 51 __IOM uint32_t CAL; /**< LFXO Calibration Register */ 52 __IOM uint32_t IF; /**< Interrupt Flag Register */ 53 __IOM uint32_t IEN; /**< Interrupt Enable Register */ 54 __IM uint32_t SYNCBUSY; /**< LFXO Sync Busy Register */ 55 __IOM uint32_t LOCK; /**< Configuration Lock Register */ 56 uint32_t RESERVED1[1014U]; /**< Reserved for future use */ 57 __IM uint32_t IPVERSION_SET; /**< LFXO IP version */ 58 __IOM uint32_t CTRL_SET; /**< LFXO Control Register */ 59 __IOM uint32_t CFG_SET; /**< LFXO Configuration Register */ 60 uint32_t RESERVED2[1U]; /**< Reserved for future use */ 61 __IM uint32_t STATUS_SET; /**< LFXO Status Register */ 62 __IOM uint32_t CAL_SET; /**< LFXO Calibration Register */ 63 __IOM uint32_t IF_SET; /**< Interrupt Flag Register */ 64 __IOM uint32_t IEN_SET; /**< Interrupt Enable Register */ 65 __IM uint32_t SYNCBUSY_SET; /**< LFXO Sync Busy Register */ 66 __IOM uint32_t LOCK_SET; /**< Configuration Lock Register */ 67 uint32_t RESERVED3[1014U]; /**< Reserved for future use */ 68 __IM uint32_t IPVERSION_CLR; /**< LFXO IP version */ 69 __IOM uint32_t CTRL_CLR; /**< LFXO Control Register */ 70 __IOM uint32_t CFG_CLR; /**< LFXO Configuration Register */ 71 uint32_t RESERVED4[1U]; /**< Reserved for future use */ 72 __IM uint32_t STATUS_CLR; /**< LFXO Status Register */ 73 __IOM uint32_t CAL_CLR; /**< LFXO Calibration Register */ 74 __IOM uint32_t IF_CLR; /**< Interrupt Flag Register */ 75 __IOM uint32_t IEN_CLR; /**< Interrupt Enable Register */ 76 __IM uint32_t SYNCBUSY_CLR; /**< LFXO Sync Busy Register */ 77 __IOM uint32_t LOCK_CLR; /**< Configuration Lock Register */ 78 uint32_t RESERVED5[1014U]; /**< Reserved for future use */ 79 __IM uint32_t IPVERSION_TGL; /**< LFXO IP version */ 80 __IOM uint32_t CTRL_TGL; /**< LFXO Control Register */ 81 __IOM uint32_t CFG_TGL; /**< LFXO Configuration Register */ 82 uint32_t RESERVED6[1U]; /**< Reserved for future use */ 83 __IM uint32_t STATUS_TGL; /**< LFXO Status Register */ 84 __IOM uint32_t CAL_TGL; /**< LFXO Calibration Register */ 85 __IOM uint32_t IF_TGL; /**< Interrupt Flag Register */ 86 __IOM uint32_t IEN_TGL; /**< Interrupt Enable Register */ 87 __IM uint32_t SYNCBUSY_TGL; /**< LFXO Sync Busy Register */ 88 __IOM uint32_t LOCK_TGL; /**< Configuration Lock Register */ 89 } LFXO_TypeDef; 90 /** @} End of group EFR32MG24_LFXO */ 91 92 /**************************************************************************//** 93 * @addtogroup EFR32MG24_LFXO 94 * @{ 95 * @defgroup EFR32MG24_LFXO_BitFields LFXO Bit Fields 96 * @{ 97 *****************************************************************************/ 98 99 /* Bit fields for LFXO IPVERSION */ 100 #define _LFXO_IPVERSION_RESETVALUE 0x00000001UL /**< Default value for LFXO_IPVERSION */ 101 #define _LFXO_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for LFXO_IPVERSION */ 102 #define _LFXO_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for LFXO_IPVERSION */ 103 #define _LFXO_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for LFXO_IPVERSION */ 104 #define _LFXO_IPVERSION_IPVERSION_DEFAULT 0x00000001UL /**< Mode DEFAULT for LFXO_IPVERSION */ 105 #define LFXO_IPVERSION_IPVERSION_DEFAULT (_LFXO_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for LFXO_IPVERSION */ 106 107 /* Bit fields for LFXO CTRL */ 108 #define _LFXO_CTRL_RESETVALUE 0x00000002UL /**< Default value for LFXO_CTRL */ 109 #define _LFXO_CTRL_MASK 0x00000033UL /**< Mask for LFXO_CTRL */ 110 #define LFXO_CTRL_FORCEEN (0x1UL << 0) /**< LFXO Force Enable */ 111 #define _LFXO_CTRL_FORCEEN_SHIFT 0 /**< Shift value for LFXO_FORCEEN */ 112 #define _LFXO_CTRL_FORCEEN_MASK 0x1UL /**< Bit mask for LFXO_FORCEEN */ 113 #define _LFXO_CTRL_FORCEEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_CTRL */ 114 #define LFXO_CTRL_FORCEEN_DEFAULT (_LFXO_CTRL_FORCEEN_DEFAULT << 0) /**< Shifted mode DEFAULT for LFXO_CTRL */ 115 #define LFXO_CTRL_DISONDEMAND (0x1UL << 1) /**< LFXO Disable On-demand requests */ 116 #define _LFXO_CTRL_DISONDEMAND_SHIFT 1 /**< Shift value for LFXO_DISONDEMAND */ 117 #define _LFXO_CTRL_DISONDEMAND_MASK 0x2UL /**< Bit mask for LFXO_DISONDEMAND */ 118 #define _LFXO_CTRL_DISONDEMAND_DEFAULT 0x00000001UL /**< Mode DEFAULT for LFXO_CTRL */ 119 #define LFXO_CTRL_DISONDEMAND_DEFAULT (_LFXO_CTRL_DISONDEMAND_DEFAULT << 1) /**< Shifted mode DEFAULT for LFXO_CTRL */ 120 #define LFXO_CTRL_FAILDETEN (0x1UL << 4) /**< LFXO Failure Detection Enable */ 121 #define _LFXO_CTRL_FAILDETEN_SHIFT 4 /**< Shift value for LFXO_FAILDETEN */ 122 #define _LFXO_CTRL_FAILDETEN_MASK 0x10UL /**< Bit mask for LFXO_FAILDETEN */ 123 #define _LFXO_CTRL_FAILDETEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_CTRL */ 124 #define LFXO_CTRL_FAILDETEN_DEFAULT (_LFXO_CTRL_FAILDETEN_DEFAULT << 4) /**< Shifted mode DEFAULT for LFXO_CTRL */ 125 #define LFXO_CTRL_FAILDETEM4WUEN (0x1UL << 5) /**< LFXO Failure Detection EM4WU Enable */ 126 #define _LFXO_CTRL_FAILDETEM4WUEN_SHIFT 5 /**< Shift value for LFXO_FAILDETEM4WUEN */ 127 #define _LFXO_CTRL_FAILDETEM4WUEN_MASK 0x20UL /**< Bit mask for LFXO_FAILDETEM4WUEN */ 128 #define _LFXO_CTRL_FAILDETEM4WUEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_CTRL */ 129 #define LFXO_CTRL_FAILDETEM4WUEN_DEFAULT (_LFXO_CTRL_FAILDETEM4WUEN_DEFAULT << 5) /**< Shifted mode DEFAULT for LFXO_CTRL */ 130 131 /* Bit fields for LFXO CFG */ 132 #define _LFXO_CFG_RESETVALUE 0x00000701UL /**< Default value for LFXO_CFG */ 133 #define _LFXO_CFG_MASK 0x00000733UL /**< Mask for LFXO_CFG */ 134 #define LFXO_CFG_AGC (0x1UL << 0) /**< LFXO AGC Enable */ 135 #define _LFXO_CFG_AGC_SHIFT 0 /**< Shift value for LFXO_AGC */ 136 #define _LFXO_CFG_AGC_MASK 0x1UL /**< Bit mask for LFXO_AGC */ 137 #define _LFXO_CFG_AGC_DEFAULT 0x00000001UL /**< Mode DEFAULT for LFXO_CFG */ 138 #define LFXO_CFG_AGC_DEFAULT (_LFXO_CFG_AGC_DEFAULT << 0) /**< Shifted mode DEFAULT for LFXO_CFG */ 139 #define LFXO_CFG_HIGHAMPL (0x1UL << 1) /**< LFXO High Amplitude Enable */ 140 #define _LFXO_CFG_HIGHAMPL_SHIFT 1 /**< Shift value for LFXO_HIGHAMPL */ 141 #define _LFXO_CFG_HIGHAMPL_MASK 0x2UL /**< Bit mask for LFXO_HIGHAMPL */ 142 #define _LFXO_CFG_HIGHAMPL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_CFG */ 143 #define LFXO_CFG_HIGHAMPL_DEFAULT (_LFXO_CFG_HIGHAMPL_DEFAULT << 1) /**< Shifted mode DEFAULT for LFXO_CFG */ 144 #define _LFXO_CFG_MODE_SHIFT 4 /**< Shift value for LFXO_MODE */ 145 #define _LFXO_CFG_MODE_MASK 0x30UL /**< Bit mask for LFXO_MODE */ 146 #define _LFXO_CFG_MODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_CFG */ 147 #define _LFXO_CFG_MODE_XTAL 0x00000000UL /**< Mode XTAL for LFXO_CFG */ 148 #define _LFXO_CFG_MODE_BUFEXTCLK 0x00000001UL /**< Mode BUFEXTCLK for LFXO_CFG */ 149 #define _LFXO_CFG_MODE_DIGEXTCLK 0x00000002UL /**< Mode DIGEXTCLK for LFXO_CFG */ 150 #define LFXO_CFG_MODE_DEFAULT (_LFXO_CFG_MODE_DEFAULT << 4) /**< Shifted mode DEFAULT for LFXO_CFG */ 151 #define LFXO_CFG_MODE_XTAL (_LFXO_CFG_MODE_XTAL << 4) /**< Shifted mode XTAL for LFXO_CFG */ 152 #define LFXO_CFG_MODE_BUFEXTCLK (_LFXO_CFG_MODE_BUFEXTCLK << 4) /**< Shifted mode BUFEXTCLK for LFXO_CFG */ 153 #define LFXO_CFG_MODE_DIGEXTCLK (_LFXO_CFG_MODE_DIGEXTCLK << 4) /**< Shifted mode DIGEXTCLK for LFXO_CFG */ 154 #define _LFXO_CFG_TIMEOUT_SHIFT 8 /**< Shift value for LFXO_TIMEOUT */ 155 #define _LFXO_CFG_TIMEOUT_MASK 0x700UL /**< Bit mask for LFXO_TIMEOUT */ 156 #define _LFXO_CFG_TIMEOUT_DEFAULT 0x00000007UL /**< Mode DEFAULT for LFXO_CFG */ 157 #define _LFXO_CFG_TIMEOUT_CYCLES2 0x00000000UL /**< Mode CYCLES2 for LFXO_CFG */ 158 #define _LFXO_CFG_TIMEOUT_CYCLES256 0x00000001UL /**< Mode CYCLES256 for LFXO_CFG */ 159 #define _LFXO_CFG_TIMEOUT_CYCLES1K 0x00000002UL /**< Mode CYCLES1K for LFXO_CFG */ 160 #define _LFXO_CFG_TIMEOUT_CYCLES2K 0x00000003UL /**< Mode CYCLES2K for LFXO_CFG */ 161 #define _LFXO_CFG_TIMEOUT_CYCLES4K 0x00000004UL /**< Mode CYCLES4K for LFXO_CFG */ 162 #define _LFXO_CFG_TIMEOUT_CYCLES8K 0x00000005UL /**< Mode CYCLES8K for LFXO_CFG */ 163 #define _LFXO_CFG_TIMEOUT_CYCLES16K 0x00000006UL /**< Mode CYCLES16K for LFXO_CFG */ 164 #define _LFXO_CFG_TIMEOUT_CYCLES32K 0x00000007UL /**< Mode CYCLES32K for LFXO_CFG */ 165 #define LFXO_CFG_TIMEOUT_DEFAULT (_LFXO_CFG_TIMEOUT_DEFAULT << 8) /**< Shifted mode DEFAULT for LFXO_CFG */ 166 #define LFXO_CFG_TIMEOUT_CYCLES2 (_LFXO_CFG_TIMEOUT_CYCLES2 << 8) /**< Shifted mode CYCLES2 for LFXO_CFG */ 167 #define LFXO_CFG_TIMEOUT_CYCLES256 (_LFXO_CFG_TIMEOUT_CYCLES256 << 8) /**< Shifted mode CYCLES256 for LFXO_CFG */ 168 #define LFXO_CFG_TIMEOUT_CYCLES1K (_LFXO_CFG_TIMEOUT_CYCLES1K << 8) /**< Shifted mode CYCLES1K for LFXO_CFG */ 169 #define LFXO_CFG_TIMEOUT_CYCLES2K (_LFXO_CFG_TIMEOUT_CYCLES2K << 8) /**< Shifted mode CYCLES2K for LFXO_CFG */ 170 #define LFXO_CFG_TIMEOUT_CYCLES4K (_LFXO_CFG_TIMEOUT_CYCLES4K << 8) /**< Shifted mode CYCLES4K for LFXO_CFG */ 171 #define LFXO_CFG_TIMEOUT_CYCLES8K (_LFXO_CFG_TIMEOUT_CYCLES8K << 8) /**< Shifted mode CYCLES8K for LFXO_CFG */ 172 #define LFXO_CFG_TIMEOUT_CYCLES16K (_LFXO_CFG_TIMEOUT_CYCLES16K << 8) /**< Shifted mode CYCLES16K for LFXO_CFG */ 173 #define LFXO_CFG_TIMEOUT_CYCLES32K (_LFXO_CFG_TIMEOUT_CYCLES32K << 8) /**< Shifted mode CYCLES32K for LFXO_CFG */ 174 175 /* Bit fields for LFXO STATUS */ 176 #define _LFXO_STATUS_RESETVALUE 0x00000000UL /**< Default value for LFXO_STATUS */ 177 #define _LFXO_STATUS_MASK 0x80010001UL /**< Mask for LFXO_STATUS */ 178 #define LFXO_STATUS_RDY (0x1UL << 0) /**< LFXO Ready Status */ 179 #define _LFXO_STATUS_RDY_SHIFT 0 /**< Shift value for LFXO_RDY */ 180 #define _LFXO_STATUS_RDY_MASK 0x1UL /**< Bit mask for LFXO_RDY */ 181 #define _LFXO_STATUS_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_STATUS */ 182 #define LFXO_STATUS_RDY_DEFAULT (_LFXO_STATUS_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for LFXO_STATUS */ 183 #define LFXO_STATUS_ENS (0x1UL << 16) /**< LFXO Enable Status */ 184 #define _LFXO_STATUS_ENS_SHIFT 16 /**< Shift value for LFXO_ENS */ 185 #define _LFXO_STATUS_ENS_MASK 0x10000UL /**< Bit mask for LFXO_ENS */ 186 #define _LFXO_STATUS_ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_STATUS */ 187 #define LFXO_STATUS_ENS_DEFAULT (_LFXO_STATUS_ENS_DEFAULT << 16) /**< Shifted mode DEFAULT for LFXO_STATUS */ 188 #define LFXO_STATUS_LOCK (0x1UL << 31) /**< LFXO Locked Status */ 189 #define _LFXO_STATUS_LOCK_SHIFT 31 /**< Shift value for LFXO_LOCK */ 190 #define _LFXO_STATUS_LOCK_MASK 0x80000000UL /**< Bit mask for LFXO_LOCK */ 191 #define _LFXO_STATUS_LOCK_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_STATUS */ 192 #define _LFXO_STATUS_LOCK_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for LFXO_STATUS */ 193 #define _LFXO_STATUS_LOCK_LOCKED 0x00000001UL /**< Mode LOCKED for LFXO_STATUS */ 194 #define LFXO_STATUS_LOCK_DEFAULT (_LFXO_STATUS_LOCK_DEFAULT << 31) /**< Shifted mode DEFAULT for LFXO_STATUS */ 195 #define LFXO_STATUS_LOCK_UNLOCKED (_LFXO_STATUS_LOCK_UNLOCKED << 31) /**< Shifted mode UNLOCKED for LFXO_STATUS */ 196 #define LFXO_STATUS_LOCK_LOCKED (_LFXO_STATUS_LOCK_LOCKED << 31) /**< Shifted mode LOCKED for LFXO_STATUS */ 197 198 /* Bit fields for LFXO CAL */ 199 #define _LFXO_CAL_RESETVALUE 0x00000100UL /**< Default value for LFXO_CAL */ 200 #define _LFXO_CAL_MASK 0x0000037FUL /**< Mask for LFXO_CAL */ 201 #define _LFXO_CAL_CAPTUNE_SHIFT 0 /**< Shift value for LFXO_CAPTUNE */ 202 #define _LFXO_CAL_CAPTUNE_MASK 0x7FUL /**< Bit mask for LFXO_CAPTUNE */ 203 #define _LFXO_CAL_CAPTUNE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_CAL */ 204 #define LFXO_CAL_CAPTUNE_DEFAULT (_LFXO_CAL_CAPTUNE_DEFAULT << 0) /**< Shifted mode DEFAULT for LFXO_CAL */ 205 #define _LFXO_CAL_GAIN_SHIFT 8 /**< Shift value for LFXO_GAIN */ 206 #define _LFXO_CAL_GAIN_MASK 0x300UL /**< Bit mask for LFXO_GAIN */ 207 #define _LFXO_CAL_GAIN_DEFAULT 0x00000001UL /**< Mode DEFAULT for LFXO_CAL */ 208 #define LFXO_CAL_GAIN_DEFAULT (_LFXO_CAL_GAIN_DEFAULT << 8) /**< Shifted mode DEFAULT for LFXO_CAL */ 209 210 /* Bit fields for LFXO IF */ 211 #define _LFXO_IF_RESETVALUE 0x00000000UL /**< Default value for LFXO_IF */ 212 #define _LFXO_IF_MASK 0x0000000FUL /**< Mask for LFXO_IF */ 213 #define LFXO_IF_RDY (0x1UL << 0) /**< LFXO Ready Interrupt Flag */ 214 #define _LFXO_IF_RDY_SHIFT 0 /**< Shift value for LFXO_RDY */ 215 #define _LFXO_IF_RDY_MASK 0x1UL /**< Bit mask for LFXO_RDY */ 216 #define _LFXO_IF_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_IF */ 217 #define LFXO_IF_RDY_DEFAULT (_LFXO_IF_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for LFXO_IF */ 218 #define LFXO_IF_POSEDGE (0x1UL << 1) /**< Rising Edge Interrupt Flag */ 219 #define _LFXO_IF_POSEDGE_SHIFT 1 /**< Shift value for LFXO_POSEDGE */ 220 #define _LFXO_IF_POSEDGE_MASK 0x2UL /**< Bit mask for LFXO_POSEDGE */ 221 #define _LFXO_IF_POSEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_IF */ 222 #define LFXO_IF_POSEDGE_DEFAULT (_LFXO_IF_POSEDGE_DEFAULT << 1) /**< Shifted mode DEFAULT for LFXO_IF */ 223 #define LFXO_IF_NEGEDGE (0x1UL << 2) /**< Falling Edge Interrupt Flag */ 224 #define _LFXO_IF_NEGEDGE_SHIFT 2 /**< Shift value for LFXO_NEGEDGE */ 225 #define _LFXO_IF_NEGEDGE_MASK 0x4UL /**< Bit mask for LFXO_NEGEDGE */ 226 #define _LFXO_IF_NEGEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_IF */ 227 #define LFXO_IF_NEGEDGE_DEFAULT (_LFXO_IF_NEGEDGE_DEFAULT << 2) /**< Shifted mode DEFAULT for LFXO_IF */ 228 #define LFXO_IF_FAIL (0x1UL << 3) /**< LFXO Failure Interrupt Flag */ 229 #define _LFXO_IF_FAIL_SHIFT 3 /**< Shift value for LFXO_FAIL */ 230 #define _LFXO_IF_FAIL_MASK 0x8UL /**< Bit mask for LFXO_FAIL */ 231 #define _LFXO_IF_FAIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_IF */ 232 #define LFXO_IF_FAIL_DEFAULT (_LFXO_IF_FAIL_DEFAULT << 3) /**< Shifted mode DEFAULT for LFXO_IF */ 233 234 /* Bit fields for LFXO IEN */ 235 #define _LFXO_IEN_RESETVALUE 0x00000000UL /**< Default value for LFXO_IEN */ 236 #define _LFXO_IEN_MASK 0x0000000FUL /**< Mask for LFXO_IEN */ 237 #define LFXO_IEN_RDY (0x1UL << 0) /**< LFXO Ready Interrupt Enable */ 238 #define _LFXO_IEN_RDY_SHIFT 0 /**< Shift value for LFXO_RDY */ 239 #define _LFXO_IEN_RDY_MASK 0x1UL /**< Bit mask for LFXO_RDY */ 240 #define _LFXO_IEN_RDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_IEN */ 241 #define LFXO_IEN_RDY_DEFAULT (_LFXO_IEN_RDY_DEFAULT << 0) /**< Shifted mode DEFAULT for LFXO_IEN */ 242 #define LFXO_IEN_POSEDGE (0x1UL << 1) /**< Rising Edge Interrupt Enable */ 243 #define _LFXO_IEN_POSEDGE_SHIFT 1 /**< Shift value for LFXO_POSEDGE */ 244 #define _LFXO_IEN_POSEDGE_MASK 0x2UL /**< Bit mask for LFXO_POSEDGE */ 245 #define _LFXO_IEN_POSEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_IEN */ 246 #define LFXO_IEN_POSEDGE_DEFAULT (_LFXO_IEN_POSEDGE_DEFAULT << 1) /**< Shifted mode DEFAULT for LFXO_IEN */ 247 #define LFXO_IEN_NEGEDGE (0x1UL << 2) /**< Falling Edge Interrupt Enable */ 248 #define _LFXO_IEN_NEGEDGE_SHIFT 2 /**< Shift value for LFXO_NEGEDGE */ 249 #define _LFXO_IEN_NEGEDGE_MASK 0x4UL /**< Bit mask for LFXO_NEGEDGE */ 250 #define _LFXO_IEN_NEGEDGE_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_IEN */ 251 #define LFXO_IEN_NEGEDGE_DEFAULT (_LFXO_IEN_NEGEDGE_DEFAULT << 2) /**< Shifted mode DEFAULT for LFXO_IEN */ 252 #define LFXO_IEN_FAIL (0x1UL << 3) /**< LFXO Failure Interrupt Enable */ 253 #define _LFXO_IEN_FAIL_SHIFT 3 /**< Shift value for LFXO_FAIL */ 254 #define _LFXO_IEN_FAIL_MASK 0x8UL /**< Bit mask for LFXO_FAIL */ 255 #define _LFXO_IEN_FAIL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_IEN */ 256 #define LFXO_IEN_FAIL_DEFAULT (_LFXO_IEN_FAIL_DEFAULT << 3) /**< Shifted mode DEFAULT for LFXO_IEN */ 257 258 /* Bit fields for LFXO SYNCBUSY */ 259 #define _LFXO_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for LFXO_SYNCBUSY */ 260 #define _LFXO_SYNCBUSY_MASK 0x00000001UL /**< Mask for LFXO_SYNCBUSY */ 261 #define LFXO_SYNCBUSY_CAL (0x1UL << 0) /**< LFXO Synchronization status */ 262 #define _LFXO_SYNCBUSY_CAL_SHIFT 0 /**< Shift value for LFXO_CAL */ 263 #define _LFXO_SYNCBUSY_CAL_MASK 0x1UL /**< Bit mask for LFXO_CAL */ 264 #define _LFXO_SYNCBUSY_CAL_DEFAULT 0x00000000UL /**< Mode DEFAULT for LFXO_SYNCBUSY */ 265 #define LFXO_SYNCBUSY_CAL_DEFAULT (_LFXO_SYNCBUSY_CAL_DEFAULT << 0) /**< Shifted mode DEFAULT for LFXO_SYNCBUSY */ 266 267 /* Bit fields for LFXO LOCK */ 268 #define _LFXO_LOCK_RESETVALUE 0x00001A20UL /**< Default value for LFXO_LOCK */ 269 #define _LFXO_LOCK_MASK 0x0000FFFFUL /**< Mask for LFXO_LOCK */ 270 #define _LFXO_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for LFXO_LOCKKEY */ 271 #define _LFXO_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for LFXO_LOCKKEY */ 272 #define _LFXO_LOCK_LOCKKEY_DEFAULT 0x00001A20UL /**< Mode DEFAULT for LFXO_LOCK */ 273 #define _LFXO_LOCK_LOCKKEY_UNLOCK 0x00001A20UL /**< Mode UNLOCK for LFXO_LOCK */ 274 #define LFXO_LOCK_LOCKKEY_DEFAULT (_LFXO_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for LFXO_LOCK */ 275 #define LFXO_LOCK_LOCKKEY_UNLOCK (_LFXO_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for LFXO_LOCK */ 276 277 /** @} End of group EFR32MG24_LFXO_BitFields */ 278 /** @} End of group EFR32MG24_LFXO */ 279 /** @} End of group Parts */ 280 281 #endif /* EFR32MG24_LFXO_H */ 282
