1 /**************************************************************************//** 2 * @file 3 * @brief EFR32MG24 GPCRC register and bit field definitions 4 ****************************************************************************** 5 * # License 6 * <b>Copyright 2023 Silicon Laboratories, Inc. www.silabs.com</b> 7 ****************************************************************************** 8 * 9 * SPDX-License-Identifier: Zlib 10 * 11 * The licensor of this software is Silicon Laboratories Inc. 12 * 13 * This software is provided 'as-is', without any express or implied 14 * warranty. In no event will the authors be held liable for any damages 15 * arising from the use of this software. 16 * 17 * Permission is granted to anyone to use this software for any purpose, 18 * including commercial applications, and to alter it and redistribute it 19 * freely, subject to the following restrictions: 20 * 21 * 1. The origin of this software must not be misrepresented; you must not 22 * claim that you wrote the original software. If you use this software 23 * in a product, an acknowledgment in the product documentation would be 24 * appreciated but is not required. 25 * 2. Altered source versions must be plainly marked as such, and must not be 26 * misrepresented as being the original software. 27 * 3. This notice may not be removed or altered from any source distribution. 28 * 29 *****************************************************************************/ 30 #ifndef EFR32MG24_GPCRC_H 31 #define EFR32MG24_GPCRC_H 32 #define GPCRC_HAS_SET_CLEAR 33 34 /**************************************************************************//** 35 * @addtogroup Parts 36 * @{ 37 ******************************************************************************/ 38 /**************************************************************************//** 39 * @defgroup EFR32MG24_GPCRC GPCRC 40 * @{ 41 * @brief EFR32MG24 GPCRC Register Declaration. 42 *****************************************************************************/ 43 44 /** GPCRC Register Declaration. */ 45 typedef struct { 46 __IM uint32_t IPVERSION; /**< IP Version ID */ 47 __IOM uint32_t EN; /**< CRC Enable */ 48 __IOM uint32_t CTRL; /**< Control Register */ 49 __IOM uint32_t CMD; /**< Command Register */ 50 __IOM uint32_t INIT; /**< CRC Init Value */ 51 __IOM uint32_t POLY; /**< CRC Polynomial Value */ 52 __IOM uint32_t INPUTDATA; /**< Input 32-bit Data Register */ 53 __IOM uint32_t INPUTDATAHWORD; /**< Input 16-bit Data Register */ 54 __IOM uint32_t INPUTDATABYTE; /**< Input 8-bit Data Register */ 55 __IM uint32_t DATA; /**< CRC Data Register */ 56 __IM uint32_t DATAREV; /**< CRC Data Reverse Register */ 57 __IM uint32_t DATABYTEREV; /**< CRC Data Byte Reverse Register */ 58 uint32_t RESERVED0[1012U]; /**< Reserved for future use */ 59 __IM uint32_t IPVERSION_SET; /**< IP Version ID */ 60 __IOM uint32_t EN_SET; /**< CRC Enable */ 61 __IOM uint32_t CTRL_SET; /**< Control Register */ 62 __IOM uint32_t CMD_SET; /**< Command Register */ 63 __IOM uint32_t INIT_SET; /**< CRC Init Value */ 64 __IOM uint32_t POLY_SET; /**< CRC Polynomial Value */ 65 __IOM uint32_t INPUTDATA_SET; /**< Input 32-bit Data Register */ 66 __IOM uint32_t INPUTDATAHWORD_SET; /**< Input 16-bit Data Register */ 67 __IOM uint32_t INPUTDATABYTE_SET; /**< Input 8-bit Data Register */ 68 __IM uint32_t DATA_SET; /**< CRC Data Register */ 69 __IM uint32_t DATAREV_SET; /**< CRC Data Reverse Register */ 70 __IM uint32_t DATABYTEREV_SET; /**< CRC Data Byte Reverse Register */ 71 uint32_t RESERVED1[1012U]; /**< Reserved for future use */ 72 __IM uint32_t IPVERSION_CLR; /**< IP Version ID */ 73 __IOM uint32_t EN_CLR; /**< CRC Enable */ 74 __IOM uint32_t CTRL_CLR; /**< Control Register */ 75 __IOM uint32_t CMD_CLR; /**< Command Register */ 76 __IOM uint32_t INIT_CLR; /**< CRC Init Value */ 77 __IOM uint32_t POLY_CLR; /**< CRC Polynomial Value */ 78 __IOM uint32_t INPUTDATA_CLR; /**< Input 32-bit Data Register */ 79 __IOM uint32_t INPUTDATAHWORD_CLR; /**< Input 16-bit Data Register */ 80 __IOM uint32_t INPUTDATABYTE_CLR; /**< Input 8-bit Data Register */ 81 __IM uint32_t DATA_CLR; /**< CRC Data Register */ 82 __IM uint32_t DATAREV_CLR; /**< CRC Data Reverse Register */ 83 __IM uint32_t DATABYTEREV_CLR; /**< CRC Data Byte Reverse Register */ 84 uint32_t RESERVED2[1012U]; /**< Reserved for future use */ 85 __IM uint32_t IPVERSION_TGL; /**< IP Version ID */ 86 __IOM uint32_t EN_TGL; /**< CRC Enable */ 87 __IOM uint32_t CTRL_TGL; /**< Control Register */ 88 __IOM uint32_t CMD_TGL; /**< Command Register */ 89 __IOM uint32_t INIT_TGL; /**< CRC Init Value */ 90 __IOM uint32_t POLY_TGL; /**< CRC Polynomial Value */ 91 __IOM uint32_t INPUTDATA_TGL; /**< Input 32-bit Data Register */ 92 __IOM uint32_t INPUTDATAHWORD_TGL; /**< Input 16-bit Data Register */ 93 __IOM uint32_t INPUTDATABYTE_TGL; /**< Input 8-bit Data Register */ 94 __IM uint32_t DATA_TGL; /**< CRC Data Register */ 95 __IM uint32_t DATAREV_TGL; /**< CRC Data Reverse Register */ 96 __IM uint32_t DATABYTEREV_TGL; /**< CRC Data Byte Reverse Register */ 97 } GPCRC_TypeDef; 98 /** @} End of group EFR32MG24_GPCRC */ 99 100 /**************************************************************************//** 101 * @addtogroup EFR32MG24_GPCRC 102 * @{ 103 * @defgroup EFR32MG24_GPCRC_BitFields GPCRC Bit Fields 104 * @{ 105 *****************************************************************************/ 106 107 /* Bit fields for GPCRC IPVERSION */ 108 #define _GPCRC_IPVERSION_RESETVALUE 0x00000000UL /**< Default value for GPCRC_IPVERSION */ 109 #define _GPCRC_IPVERSION_MASK 0xFFFFFFFFUL /**< Mask for GPCRC_IPVERSION */ 110 #define _GPCRC_IPVERSION_IPVERSION_SHIFT 0 /**< Shift value for GPCRC_IPVERSION */ 111 #define _GPCRC_IPVERSION_IPVERSION_MASK 0xFFFFFFFFUL /**< Bit mask for GPCRC_IPVERSION */ 112 #define _GPCRC_IPVERSION_IPVERSION_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_IPVERSION */ 113 #define GPCRC_IPVERSION_IPVERSION_DEFAULT (_GPCRC_IPVERSION_IPVERSION_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_IPVERSION */ 114 115 /* Bit fields for GPCRC EN */ 116 #define _GPCRC_EN_RESETVALUE 0x00000000UL /**< Default value for GPCRC_EN */ 117 #define _GPCRC_EN_MASK 0x00000001UL /**< Mask for GPCRC_EN */ 118 #define GPCRC_EN_EN (0x1UL << 0) /**< CRC Enable */ 119 #define _GPCRC_EN_EN_SHIFT 0 /**< Shift value for GPCRC_EN */ 120 #define _GPCRC_EN_EN_MASK 0x1UL /**< Bit mask for GPCRC_EN */ 121 #define _GPCRC_EN_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_EN */ 122 #define _GPCRC_EN_EN_DISABLE 0x00000000UL /**< Mode DISABLE for GPCRC_EN */ 123 #define _GPCRC_EN_EN_ENABLE 0x00000001UL /**< Mode ENABLE for GPCRC_EN */ 124 #define GPCRC_EN_EN_DEFAULT (_GPCRC_EN_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_EN */ 125 #define GPCRC_EN_EN_DISABLE (_GPCRC_EN_EN_DISABLE << 0) /**< Shifted mode DISABLE for GPCRC_EN */ 126 #define GPCRC_EN_EN_ENABLE (_GPCRC_EN_EN_ENABLE << 0) /**< Shifted mode ENABLE for GPCRC_EN */ 127 128 /* Bit fields for GPCRC CTRL */ 129 #define _GPCRC_CTRL_RESETVALUE 0x00000000UL /**< Default value for GPCRC_CTRL */ 130 #define _GPCRC_CTRL_MASK 0x00002710UL /**< Mask for GPCRC_CTRL */ 131 #define GPCRC_CTRL_POLYSEL (0x1UL << 4) /**< Polynomial Select */ 132 #define _GPCRC_CTRL_POLYSEL_SHIFT 4 /**< Shift value for GPCRC_POLYSEL */ 133 #define _GPCRC_CTRL_POLYSEL_MASK 0x10UL /**< Bit mask for GPCRC_POLYSEL */ 134 #define _GPCRC_CTRL_POLYSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_CTRL */ 135 #define _GPCRC_CTRL_POLYSEL_CRC32 0x00000000UL /**< Mode CRC32 for GPCRC_CTRL */ 136 #define _GPCRC_CTRL_POLYSEL_CRC16 0x00000001UL /**< Mode CRC16 for GPCRC_CTRL */ 137 #define GPCRC_CTRL_POLYSEL_DEFAULT (_GPCRC_CTRL_POLYSEL_DEFAULT << 4) /**< Shifted mode DEFAULT for GPCRC_CTRL */ 138 #define GPCRC_CTRL_POLYSEL_CRC32 (_GPCRC_CTRL_POLYSEL_CRC32 << 4) /**< Shifted mode CRC32 for GPCRC_CTRL */ 139 #define GPCRC_CTRL_POLYSEL_CRC16 (_GPCRC_CTRL_POLYSEL_CRC16 << 4) /**< Shifted mode CRC16 for GPCRC_CTRL */ 140 #define GPCRC_CTRL_BYTEMODE (0x1UL << 8) /**< Byte Mode Enable */ 141 #define _GPCRC_CTRL_BYTEMODE_SHIFT 8 /**< Shift value for GPCRC_BYTEMODE */ 142 #define _GPCRC_CTRL_BYTEMODE_MASK 0x100UL /**< Bit mask for GPCRC_BYTEMODE */ 143 #define _GPCRC_CTRL_BYTEMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_CTRL */ 144 #define GPCRC_CTRL_BYTEMODE_DEFAULT (_GPCRC_CTRL_BYTEMODE_DEFAULT << 8) /**< Shifted mode DEFAULT for GPCRC_CTRL */ 145 #define GPCRC_CTRL_BITREVERSE (0x1UL << 9) /**< Byte-level Bit Reverse Enable */ 146 #define _GPCRC_CTRL_BITREVERSE_SHIFT 9 /**< Shift value for GPCRC_BITREVERSE */ 147 #define _GPCRC_CTRL_BITREVERSE_MASK 0x200UL /**< Bit mask for GPCRC_BITREVERSE */ 148 #define _GPCRC_CTRL_BITREVERSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_CTRL */ 149 #define _GPCRC_CTRL_BITREVERSE_NORMAL 0x00000000UL /**< Mode NORMAL for GPCRC_CTRL */ 150 #define _GPCRC_CTRL_BITREVERSE_REVERSED 0x00000001UL /**< Mode REVERSED for GPCRC_CTRL */ 151 #define GPCRC_CTRL_BITREVERSE_DEFAULT (_GPCRC_CTRL_BITREVERSE_DEFAULT << 9) /**< Shifted mode DEFAULT for GPCRC_CTRL */ 152 #define GPCRC_CTRL_BITREVERSE_NORMAL (_GPCRC_CTRL_BITREVERSE_NORMAL << 9) /**< Shifted mode NORMAL for GPCRC_CTRL */ 153 #define GPCRC_CTRL_BITREVERSE_REVERSED (_GPCRC_CTRL_BITREVERSE_REVERSED << 9) /**< Shifted mode REVERSED for GPCRC_CTRL */ 154 #define GPCRC_CTRL_BYTEREVERSE (0x1UL << 10) /**< Byte Reverse Mode */ 155 #define _GPCRC_CTRL_BYTEREVERSE_SHIFT 10 /**< Shift value for GPCRC_BYTEREVERSE */ 156 #define _GPCRC_CTRL_BYTEREVERSE_MASK 0x400UL /**< Bit mask for GPCRC_BYTEREVERSE */ 157 #define _GPCRC_CTRL_BYTEREVERSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_CTRL */ 158 #define _GPCRC_CTRL_BYTEREVERSE_NORMAL 0x00000000UL /**< Mode NORMAL for GPCRC_CTRL */ 159 #define _GPCRC_CTRL_BYTEREVERSE_REVERSED 0x00000001UL /**< Mode REVERSED for GPCRC_CTRL */ 160 #define GPCRC_CTRL_BYTEREVERSE_DEFAULT (_GPCRC_CTRL_BYTEREVERSE_DEFAULT << 10) /**< Shifted mode DEFAULT for GPCRC_CTRL */ 161 #define GPCRC_CTRL_BYTEREVERSE_NORMAL (_GPCRC_CTRL_BYTEREVERSE_NORMAL << 10) /**< Shifted mode NORMAL for GPCRC_CTRL */ 162 #define GPCRC_CTRL_BYTEREVERSE_REVERSED (_GPCRC_CTRL_BYTEREVERSE_REVERSED << 10) /**< Shifted mode REVERSED for GPCRC_CTRL */ 163 #define GPCRC_CTRL_AUTOINIT (0x1UL << 13) /**< Auto Init Enable */ 164 #define _GPCRC_CTRL_AUTOINIT_SHIFT 13 /**< Shift value for GPCRC_AUTOINIT */ 165 #define _GPCRC_CTRL_AUTOINIT_MASK 0x2000UL /**< Bit mask for GPCRC_AUTOINIT */ 166 #define _GPCRC_CTRL_AUTOINIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_CTRL */ 167 #define GPCRC_CTRL_AUTOINIT_DEFAULT (_GPCRC_CTRL_AUTOINIT_DEFAULT << 13) /**< Shifted mode DEFAULT for GPCRC_CTRL */ 168 169 /* Bit fields for GPCRC CMD */ 170 #define _GPCRC_CMD_RESETVALUE 0x00000000UL /**< Default value for GPCRC_CMD */ 171 #define _GPCRC_CMD_MASK 0x80000001UL /**< Mask for GPCRC_CMD */ 172 #define GPCRC_CMD_INIT (0x1UL << 0) /**< Initialization Enable */ 173 #define _GPCRC_CMD_INIT_SHIFT 0 /**< Shift value for GPCRC_INIT */ 174 #define _GPCRC_CMD_INIT_MASK 0x1UL /**< Bit mask for GPCRC_INIT */ 175 #define _GPCRC_CMD_INIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_CMD */ 176 #define GPCRC_CMD_INIT_DEFAULT (_GPCRC_CMD_INIT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_CMD */ 177 178 /* Bit fields for GPCRC INIT */ 179 #define _GPCRC_INIT_RESETVALUE 0x00000000UL /**< Default value for GPCRC_INIT */ 180 #define _GPCRC_INIT_MASK 0xFFFFFFFFUL /**< Mask for GPCRC_INIT */ 181 #define _GPCRC_INIT_INIT_SHIFT 0 /**< Shift value for GPCRC_INIT */ 182 #define _GPCRC_INIT_INIT_MASK 0xFFFFFFFFUL /**< Bit mask for GPCRC_INIT */ 183 #define _GPCRC_INIT_INIT_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_INIT */ 184 #define GPCRC_INIT_INIT_DEFAULT (_GPCRC_INIT_INIT_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_INIT */ 185 186 /* Bit fields for GPCRC POLY */ 187 #define _GPCRC_POLY_RESETVALUE 0x00000000UL /**< Default value for GPCRC_POLY */ 188 #define _GPCRC_POLY_MASK 0x0000FFFFUL /**< Mask for GPCRC_POLY */ 189 #define _GPCRC_POLY_POLY_SHIFT 0 /**< Shift value for GPCRC_POLY */ 190 #define _GPCRC_POLY_POLY_MASK 0xFFFFUL /**< Bit mask for GPCRC_POLY */ 191 #define _GPCRC_POLY_POLY_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_POLY */ 192 #define GPCRC_POLY_POLY_DEFAULT (_GPCRC_POLY_POLY_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_POLY */ 193 194 /* Bit fields for GPCRC INPUTDATA */ 195 #define _GPCRC_INPUTDATA_RESETVALUE 0x00000000UL /**< Default value for GPCRC_INPUTDATA */ 196 #define _GPCRC_INPUTDATA_MASK 0xFFFFFFFFUL /**< Mask for GPCRC_INPUTDATA */ 197 #define _GPCRC_INPUTDATA_INPUTDATA_SHIFT 0 /**< Shift value for GPCRC_INPUTDATA */ 198 #define _GPCRC_INPUTDATA_INPUTDATA_MASK 0xFFFFFFFFUL /**< Bit mask for GPCRC_INPUTDATA */ 199 #define _GPCRC_INPUTDATA_INPUTDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_INPUTDATA */ 200 #define GPCRC_INPUTDATA_INPUTDATA_DEFAULT (_GPCRC_INPUTDATA_INPUTDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_INPUTDATA */ 201 202 /* Bit fields for GPCRC INPUTDATAHWORD */ 203 #define _GPCRC_INPUTDATAHWORD_RESETVALUE 0x00000000UL /**< Default value for GPCRC_INPUTDATAHWORD */ 204 #define _GPCRC_INPUTDATAHWORD_MASK 0x0000FFFFUL /**< Mask for GPCRC_INPUTDATAHWORD */ 205 #define _GPCRC_INPUTDATAHWORD_INPUTDATAHWORD_SHIFT 0 /**< Shift value for GPCRC_INPUTDATAHWORD */ 206 #define _GPCRC_INPUTDATAHWORD_INPUTDATAHWORD_MASK 0xFFFFUL /**< Bit mask for GPCRC_INPUTDATAHWORD */ 207 #define _GPCRC_INPUTDATAHWORD_INPUTDATAHWORD_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_INPUTDATAHWORD */ 208 #define GPCRC_INPUTDATAHWORD_INPUTDATAHWORD_DEFAULT (_GPCRC_INPUTDATAHWORD_INPUTDATAHWORD_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_INPUTDATAHWORD*/ 209 210 /* Bit fields for GPCRC INPUTDATABYTE */ 211 #define _GPCRC_INPUTDATABYTE_RESETVALUE 0x00000000UL /**< Default value for GPCRC_INPUTDATABYTE */ 212 #define _GPCRC_INPUTDATABYTE_MASK 0x000000FFUL /**< Mask for GPCRC_INPUTDATABYTE */ 213 #define _GPCRC_INPUTDATABYTE_INPUTDATABYTE_SHIFT 0 /**< Shift value for GPCRC_INPUTDATABYTE */ 214 #define _GPCRC_INPUTDATABYTE_INPUTDATABYTE_MASK 0xFFUL /**< Bit mask for GPCRC_INPUTDATABYTE */ 215 #define _GPCRC_INPUTDATABYTE_INPUTDATABYTE_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_INPUTDATABYTE */ 216 #define GPCRC_INPUTDATABYTE_INPUTDATABYTE_DEFAULT (_GPCRC_INPUTDATABYTE_INPUTDATABYTE_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_INPUTDATABYTE*/ 217 218 /* Bit fields for GPCRC DATA */ 219 #define _GPCRC_DATA_RESETVALUE 0x00000000UL /**< Default value for GPCRC_DATA */ 220 #define _GPCRC_DATA_MASK 0xFFFFFFFFUL /**< Mask for GPCRC_DATA */ 221 #define _GPCRC_DATA_DATA_SHIFT 0 /**< Shift value for GPCRC_DATA */ 222 #define _GPCRC_DATA_DATA_MASK 0xFFFFFFFFUL /**< Bit mask for GPCRC_DATA */ 223 #define _GPCRC_DATA_DATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_DATA */ 224 #define GPCRC_DATA_DATA_DEFAULT (_GPCRC_DATA_DATA_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_DATA */ 225 226 /* Bit fields for GPCRC DATAREV */ 227 #define _GPCRC_DATAREV_RESETVALUE 0x00000000UL /**< Default value for GPCRC_DATAREV */ 228 #define _GPCRC_DATAREV_MASK 0xFFFFFFFFUL /**< Mask for GPCRC_DATAREV */ 229 #define _GPCRC_DATAREV_DATAREV_SHIFT 0 /**< Shift value for GPCRC_DATAREV */ 230 #define _GPCRC_DATAREV_DATAREV_MASK 0xFFFFFFFFUL /**< Bit mask for GPCRC_DATAREV */ 231 #define _GPCRC_DATAREV_DATAREV_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_DATAREV */ 232 #define GPCRC_DATAREV_DATAREV_DEFAULT (_GPCRC_DATAREV_DATAREV_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_DATAREV */ 233 234 /* Bit fields for GPCRC DATABYTEREV */ 235 #define _GPCRC_DATABYTEREV_RESETVALUE 0x00000000UL /**< Default value for GPCRC_DATABYTEREV */ 236 #define _GPCRC_DATABYTEREV_MASK 0xFFFFFFFFUL /**< Mask for GPCRC_DATABYTEREV */ 237 #define _GPCRC_DATABYTEREV_DATABYTEREV_SHIFT 0 /**< Shift value for GPCRC_DATABYTEREV */ 238 #define _GPCRC_DATABYTEREV_DATABYTEREV_MASK 0xFFFFFFFFUL /**< Bit mask for GPCRC_DATABYTEREV */ 239 #define _GPCRC_DATABYTEREV_DATABYTEREV_DEFAULT 0x00000000UL /**< Mode DEFAULT for GPCRC_DATABYTEREV */ 240 #define GPCRC_DATABYTEREV_DATABYTEREV_DEFAULT (_GPCRC_DATABYTEREV_DATABYTEREV_DEFAULT << 0) /**< Shifted mode DEFAULT for GPCRC_DATABYTEREV */ 241 242 /** @} End of group EFR32MG24_GPCRC_BitFields */ 243 /** @} End of group EFR32MG24_GPCRC */ 244 /** @} End of group Parts */ 245 246 #endif /* EFR32MG24_GPCRC_H */ 247
